Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3341269

1

T5

1

T6

1

T8

2301

auto[1]

35401

1

T15

118

T17

75

T46

42

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

784165

1

T5

1

T6

1

T8

2301

auto[1]

2592505

1

T15

4858

T17

3592

T46

8510

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	621302	1			T5	1		T6	1		T8	668
auto[524288:1048575]	382194	1			T8	58		T12	252		T14	2451
auto[1048576:1572863]	360165	1			T12	180		T15	5		T17	312
auto[1572864:2097151]	402105	1			T12	380		T14	5		T15	515
auto[2097152:2621439]	429084	1			T8	107		T12	40		T15	2648
auto[2621440:3145727]	363490	1			T8	679		T12	95		T17	292
auto[3145728:3670015]	418545	1			T12	106		T17	1606		T58	774
auto[3670016:4194303]	399785	1			T8	789		T9	4		T12	162

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2626796

1

T5

1

T6

1

T8

27

auto[1]

749874

1

T8

2274

T9

1

T12

1283

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2885874

1

T5

1

T6

1

T8

2301

auto[1]

490796

1

T15

17

T17

524

T80

405

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	155431	1			T5	1		T6	1		T8	668
auto[0]	auto[0]	auto[0:524287]	auto[1]	404938	1			T15	1619		T17	742		T43	5
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	77472	1			T8	58		T12	252		T14	2451
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	240348	1			T15	1		T46	943		T43	513
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	85789	1			T12	180		T15	1		T17	7
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	214026	1			T15	4		T17	296		T46	1024
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	89679	1			T12	380		T14	5		T15	3
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	246436	1			T15	512		T17	133		T46	2835
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	94564	1			T8	107		T12	40		T15	8
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	254324	1			T15	2605		T17	256		T46	3167
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	70125	1			T8	679		T12	95		T17	6
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	232678	1			T17	267		T43	1		T39	256
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	80732	1			T12	106		T17	6		T58	774
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	270370	1			T17	1317		T43	2		T39	2
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	113199	1			T8	789		T9	4		T12	162
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	226088	1			T17	1		T46	512		T39	327
auto[0]	auto[1]	auto[0:524287]	auto[0]	1720	1			T96	4		T40	4		T73	2
auto[0]	auto[1]	auto[0:524287]	auto[1]	53523	1			T73	1		T89	512		T37	385
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	935	1			T15	4		T40	13		T73	4
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	59273	1			T15	4		T40	1883		T73	769
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	4062	1			T17	1		T96	13		T72	18
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	53199	1			T73	1		T76	4		T53	512
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	673	1			T40	14		T72	10		T74	6
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	59637	1			T40	1		T72	5		T74	683
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	1015	1			T80	193		T72	40		T74	2
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	75756	1			T72	259		T74	1179		T76	1
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	2452	1			T39	1		T40	2		T72	13
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	52808	1			T17	1		T72	512		T73	1293
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	956	1			T80	212		T40	20		T72	8
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	63133	1			T17	256		T40	2		T30	256
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	1297	1			T17	5		T40	5		T72	8
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	54631	1			T17	257		T40	256		T72	1290
auto[1]	auto[0]	auto[0:524287]	auto[0]	510	1			T15	2		T17	1		T43	1
auto[1]	auto[0]	auto[0:524287]	auto[1]	4215	1			T15	24		T73	1		T74	2
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	391	1			T15	1		T43	1		T72	6
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	3086	1			T15	47		T43	3		T73	50
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	394	1			T17	1		T40	6		T30	2
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	2442	1			T17	7		T30	18		T53	120
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	420	1			T17	1		T46	6		T40	6
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	4709	1			T17	4		T46	29		T76	88
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	452	1			T15	1		T76	1		T30	1
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	2188	1			T15	34		T76	44		T30	7
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	387	1			T17	1		T43	1		T72	15
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	4543	1			T17	17		T43	2		T72	5
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	359	1			T17	3		T46	4		T43	2
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	2362	1			T17	24		T43	3		T40	25
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	403	1			T17	1		T46	3		T39	2
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	2814	1			T17	11		T39	72		T73	25
auto[1]	auto[1]	auto[0:524287]	auto[0]	101	1			T73	1		T37	1		T55	6
auto[1]	auto[1]	auto[0:524287]	auto[1]	864	1			T73	21		T37	4		T55	282
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	82	1			T15	1		T73	1		T55	5
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	607	1			T15	8		T73	6		T55	236
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	84	1			T72	13		T57	5		T246	1
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	169	1			T246	4		T194	25		T87	6
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	82	1			T74	2		T55	9		T57	3
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	469	1			T74	6		T32	28		T247	1
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	127	1			T72	3		T76	1		T30	4
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	658	1			T76	48		T30	20		T32	75
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	87	1			T73	2		T30	3		T37	1
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	410	1			T73	4		T30	84		T86	5
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	88	1			T37	1		T247	1		T86	2
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	545	1			T37	3		T247	2		T86	1
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	97	1			T17	1		T76	1		T89	1
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	1256	1			T17	3		T76	33		T89	36

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	2114839	1			T5	1		T6	1		T8	27
auto[0]	auto[0]	auto[1]	741360	1			T8	2274		T9	1		T12	1283
auto[0]	auto[1]	auto[0]	477234	1			T15	8		T17	520		T80	219
auto[0]	auto[1]	auto[1]	7836	1			T80	186		T96	13		T73	1
auto[1]	auto[0]	auto[0]	29130	1			T15	109		T17	70		T46	38
auto[1]	auto[0]	auto[1]	545	1			T17	1		T46	4		T40	5
auto[1]	auto[1]	auto[0]	5593	1			T15	9		T17	4		T72	15
auto[1]	auto[1]	auto[1]	133	1			T72	1		T73	1		T55	1