Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2607566	1			T1	1		T2	1		T3	1
all_pins[1]	2607566	1			T1	1		T2	1		T3	1
all_pins[2]	2607566	1			T1	1		T2	1		T3	1
all_pins[3]	2607566	1			T1	1		T2	1		T3	1
all_pins[4]	2607566	1			T1	1		T2	1		T3	1
all_pins[5]	2607566	1			T1	1		T2	1		T3	1
all_pins[6]	2607566	1			T1	1		T2	1		T3	1
all_pins[7]	2607566	1			T1	1		T2	1		T3	1

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	20843049	1			T1	8		T2	8		T3	8
values[0x1]	17479	1			T79	36		T20	53		T31	20
transitions[0x0=>0x1]	16338	1			T79	29		T20	36		T31	18
transitions[0x1=>0x0]	16348	1			T79	29		T20	36		T31	18

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2606993	1			T1	1		T2	1		T3	1
all_pins[0]	values[0x1]	573	1			T79	3		T20	8		T31	4
all_pins[0]	transitions[0x0=>0x1]	496	1			T79	3		T20	4		T31	3
all_pins[0]	transitions[0x1=>0x0]	149	1			T79	5		T20	6		T176	1
all_pins[1]	values[0x0]	2607340	1			T1	1		T2	1		T3	1
all_pins[1]	values[0x1]	226	1			T79	5		T20	10		T31	1
all_pins[1]	transitions[0x0=>0x1]	163	1			T79	3		T20	7		T158	4
all_pins[1]	transitions[0x1=>0x0]	183	1			T79	3		T20	4		T31	3
all_pins[2]	values[0x0]	2607320	1			T1	1		T2	1		T3	1
all_pins[2]	values[0x1]	246	1			T79	5		T20	7		T31	4
all_pins[2]	transitions[0x0=>0x1]	185	1			T79	4		T20	4		T31	4
all_pins[2]	transitions[0x1=>0x0]	153	1			T79	6		T20	1		T31	3
all_pins[3]	values[0x0]	2607352	1			T1	1		T2	1		T3	1
all_pins[3]	values[0x1]	214	1			T79	7		T20	4		T31	3
all_pins[3]	transitions[0x0=>0x1]	163	1			T79	5		T20	2		T31	3
all_pins[3]	transitions[0x1=>0x0]	132	1			T79	5		T20	4		T33	3
all_pins[4]	values[0x0]	2607383	1			T1	1		T2	1		T3	1
all_pins[4]	values[0x1]	183	1			T79	7		T20	6		T33	3
all_pins[4]	transitions[0x0=>0x1]	148	1			T79	6		T20	6		T33	3
all_pins[4]	transitions[0x1=>0x0]	868	1			T79	3		T20	3		T31	3
all_pins[5]	values[0x0]	2606663	1			T1	1		T2	1		T3	1
all_pins[5]	values[0x1]	903	1			T79	4		T20	3		T31	3
all_pins[5]	transitions[0x0=>0x1]	145	1			T79	4		T20	3		T31	3
all_pins[5]	transitions[0x1=>0x0]	14168	1			T79	3		T20	9		T31	3
all_pins[6]	values[0x0]	2592640	1			T1	1		T2	1		T3	1
all_pins[6]	values[0x1]	14926	1			T79	3		T20	9		T31	3
all_pins[6]	transitions[0x0=>0x1]	14885	1			T79	2		T20	7		T31	3
all_pins[6]	transitions[0x1=>0x0]	167	1			T79	1		T20	4		T31	2
all_pins[7]	values[0x0]	2607358	1			T1	1		T2	1		T3	1
all_pins[7]	values[0x1]	208	1			T79	2		T20	6		T31	2
all_pins[7]	transitions[0x0=>0x1]	153	1			T79	2		T20	3		T31	2
all_pins[7]	transitions[0x1=>0x0]	528	1			T79	3		T20	5		T31	4