Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18114

1

T5

4

T8

14

T9

2

auto[1]

13061

1

T6

6

T15

113

T34

14

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3863	1			T30	60		T53	32		T56	222
values[1]	4425	1			T15	55		T35	2		T46	40
values[2]	3181	1			T49	12		T30	20		T53	84
values[3]	3616	1			T5	4		T9	2		T12	16
values[4]	3950	1			T46	20		T80	20		T52	14
values[5]	4721	1			T36	8		T50	20		T227	8
values[6]	3878	1			T8	14		T15	68		T224	2
values[7]	3541	1			T6	6		T10	12		T34	14

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	5008	1			T46	20		T80	20		T40	20
values[1]	3356	1			T8	14		T34	14		T35	2
values[2]	3647	1			T36	8		T58	2		T227	8
values[3]	3333	1			T6	6		T9	2		T49	12
values[4]	3987	1			T15	55		T46	20		T51	16
values[5]	3832	1			T5	4		T96	16		T40	20
values[6]	4314	1			T10	12		T15	143		T100	20
values[7]	3698	1			T12	16		T52	14		T40	20

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	185	1			T30	12		T199	11		T248	12
auto[0]	values[0]	values[1]	307	1			T158	14		T249	24		T250	10
auto[0]	values[0]	values[2]	342	1			T53	27		T56	24		T194	15
auto[0]	values[0]	values[3]	367	1			T194	11		T195	66		T202	8
auto[0]	values[0]	values[4]	205	1			T30	14		T177	13		T135	11
auto[0]	values[0]	values[5]	356	1			T56	42		T194	10		T251	2
auto[0]	values[0]	values[6]	272	1			T30	10		T98	12		T252	12
auto[0]	values[0]	values[7]	376	1			T56	99		T90	13		T253	2
auto[0]	values[1]	values[0]	433	1			T46	9		T254	12		T194	18
auto[0]	values[1]	values[1]	179	1			T35	2		T46	11		T53	14
auto[0]	values[1]	values[2]	282	1			T40	16		T90	13		T135	11
auto[0]	values[1]	values[3]	275	1			T203	11		T98	14		T201	10
auto[0]	values[1]	values[4]	459	1			T57	9		T177	9		T255	14
auto[0]	values[1]	values[5]	228	1			T56	15		T98	9		T252	10
auto[0]	values[1]	values[6]	572	1			T15	7		T40	11		T75	36
auto[0]	values[1]	values[7]	237	1			T90	11		T159	13		T202	11
auto[0]	values[2]	values[0]	172	1			T194	22		T159	16		T256	2
auto[0]	values[2]	values[1]	104	1			T53	13		T257	2		T194	12
auto[0]	values[2]	values[2]	184	1			T30	13		T98	15		T192	14
auto[0]	values[2]	values[3]	217	1			T49	12		T98	9		T198	13
auto[0]	values[2]	values[4]	316	1			T258	10		T229	10		T259	2
auto[0]	values[2]	values[5]	362	1			T200	13		T260	17		T211	10
auto[0]	values[2]	values[6]	237	1			T135	10		T98	13		T198	11
auto[0]	values[2]	values[7]	153	1			T55	13		T194	12		T261	10
auto[0]	values[3]	values[0]	470	1			T134	14		T262	2		T195	10
auto[0]	values[3]	values[1]	217	1			T55	10		T194	14		T249	18
auto[0]	values[3]	values[2]	370	1			T58	2		T30	12		T57	15
auto[0]	values[3]	values[3]	235	1			T9	2		T30	11		T159	12
auto[0]	values[3]	values[4]	232	1			T15	52		T135	4		T194	12
auto[0]	values[3]	values[5]	239	1			T5	4		T53	45		T32	8
auto[0]	values[3]	values[6]	218	1			T15	14		T100	20		T30	10
auto[0]	values[3]	values[7]	238	1			T12	16		T203	6		T263	22
auto[0]	values[4]	values[0]	465	1			T80	20		T232	4		T56	15
auto[0]	values[4]	values[1]	166	1			T118	22		T53	14		T55	6
auto[0]	values[4]	values[2]	274	1			T264	26		T55	10		T98	7
auto[0]	values[4]	values[3]	316	1			T207	22		T200	11		T218	12
auto[0]	values[4]	values[4]	326	1			T46	13		T53	89		T265	83
auto[0]	values[4]	values[5]	264	1			T40	13		T266	2		T200	10
auto[0]	values[4]	values[6]	277	1			T213	2		T101	2		T53	13
auto[0]	values[4]	values[7]	188	1			T158	11		T267	14		T205	16
auto[0]	values[5]	values[0]	497	1			T30	12		T53	104		T56	9
auto[0]	values[5]	values[1]	245	1			T50	20		T56	17		T159	6
auto[0]	values[5]	values[2]	289	1			T36	8		T227	8		T53	12
auto[0]	values[5]	values[3]	159	1			T56	13		T159	20		T198	11
auto[0]	values[5]	values[4]	320	1			T47	12		T53	9		T55	13
auto[0]	values[5]	values[5]	330	1			T96	16		T97	10		T55	12
auto[0]	values[5]	values[6]	317	1			T55	12		T135	33		T200	16
auto[0]	values[5]	values[7]	365	1			T56	23		T135	21		T203	9
auto[0]	values[6]	values[0]	242	1			T40	6		T56	12		T177	12
auto[0]	values[6]	values[1]	239	1			T8	14		T40	14		T173	2
auto[0]	values[6]	values[2]	223	1			T90	30		T98	14		T200	15
auto[0]	values[6]	values[3]	130	1			T268	6		T98	13		T200	8
auto[0]	values[6]	values[4]	303	1			T30	18		T32	93		T135	14
auto[0]	values[6]	values[5]	406	1			T57	25		T269	4		T32	102
auto[0]	values[6]	values[6]	400	1			T15	12		T224	2		T56	62
auto[0]	values[6]	values[7]	357	1			T40	13		T30	25		T32	9
auto[0]	values[7]	values[0]	225	1			T135	14		T158	9		T194	13
auto[0]	values[7]	values[1]	275	1			T30	21		T270	14		T216	159
auto[0]	values[7]	values[2]	324	1			T55	10		T32	46		T90	13
auto[0]	values[7]	values[3]	106	1			T177	12		T195	12		T271	11
auto[0]	values[7]	values[4]	303	1			T55	9		T238	6		T90	9
auto[0]	values[7]	values[5]	325	1			T30	28		T211	16		T192	12
auto[0]	values[7]	values[6]	226	1			T10	12		T135	9		T203	10
auto[0]	values[7]	values[7]	193	1			T190	36		T272	13		T273	6
auto[1]	values[0]	values[0]	163	1			T30	8		T199	9		T60	8
auto[1]	values[0]	values[1]	237	1			T133	14		T158	50		T249	9
auto[1]	values[0]	values[2]	143	1			T53	5		T56	36		T194	5
auto[1]	values[0]	values[3]	184	1			T194	9		T195	25		T202	12
auto[1]	values[0]	values[4]	126	1			T30	6		T177	7		T135	9
auto[1]	values[0]	values[5]	165	1			T56	11		T194	10		T192	7
auto[1]	values[0]	values[6]	244	1			T30	10		T98	8		T252	8
auto[1]	values[0]	values[7]	191	1			T56	10		T90	10		T242	9
auto[1]	values[1]	values[0]	240	1			T46	11		T194	2		T205	7
auto[1]	values[1]	values[1]	164	1			T46	9		T53	6		T56	10
auto[1]	values[1]	values[2]	133	1			T40	4		T90	38		T135	9
auto[1]	values[1]	values[3]	268	1			T203	9		T98	6		T198	9
auto[1]	values[1]	values[4]	216	1			T57	11		T177	11		T202	10
auto[1]	values[1]	values[5]	237	1			T56	5		T98	11		T252	10
auto[1]	values[1]	values[6]	241	1			T15	48		T40	9		T55	8
auto[1]	values[1]	values[7]	261	1			T90	9		T159	43		T202	13
auto[1]	values[2]	values[0]	272	1			T194	9		T159	68		T211	5
auto[1]	values[2]	values[1]	189	1			T53	71		T194	44		T228	2
auto[1]	values[2]	values[2]	208	1			T30	7		T98	5		T274	6
auto[1]	values[2]	values[3]	108	1			T98	11		T198	12		T202	7
auto[1]	values[2]	values[4]	201	1			T192	15		T275	34		T276	42
auto[1]	values[2]	values[5]	72	1			T200	7		T211	19		T277	6
auto[1]	values[2]	values[6]	287	1			T135	10		T98	7		T198	26
auto[1]	values[2]	values[7]	99	1			T55	7		T178	6		T194	10
auto[1]	values[3]	values[0]	81	1			T195	10		T278	7		T211	7
auto[1]	values[3]	values[1]	184	1			T55	10		T194	6		T249	3
auto[1]	values[3]	values[2]	179	1			T54	16		T30	8		T57	5
auto[1]	values[3]	values[3]	272	1			T30	9		T159	8		T279	24
auto[1]	values[3]	values[4]	266	1			T15	3		T135	98		T194	16
auto[1]	values[3]	values[5]	116	1			T53	5		T32	86		T280	16
auto[1]	values[3]	values[6]	154	1			T15	6		T30	11		T90	48
auto[1]	values[3]	values[7]	145	1			T203	14		T198	6		T281	8
auto[1]	values[4]	values[0]	323	1			T56	5		T98	11		T282	6
auto[1]	values[4]	values[1]	159	1			T53	6		T55	14		T219	20
auto[1]	values[4]	values[2]	166	1			T55	10		T98	13		T218	3
auto[1]	values[4]	values[3]	234	1			T200	9		T218	8		T159	6
auto[1]	values[4]	values[4]	150	1			T46	7		T53	7		T90	16
auto[1]	values[4]	values[5]	140	1			T40	7		T200	10		T283	18
auto[1]	values[4]	values[6]	236	1			T53	7		T55	7		T158	10
auto[1]	values[4]	values[7]	266	1			T52	14		T158	10		T205	4
auto[1]	values[5]	values[0]	665	1			T30	114		T53	11		T56	99
auto[1]	values[5]	values[1]	225	1			T244	22		T56	9		T159	21
auto[1]	values[5]	values[2]	182	1			T53	27		T191	6		T60	7
auto[1]	values[5]	values[3]	144	1			T56	7		T159	49		T198	9
auto[1]	values[5]	values[4]	287	1			T53	161		T55	7		T98	7
auto[1]	values[5]	values[5]	183	1			T55	8		T57	11		T177	7
auto[1]	values[5]	values[6]	270	1			T55	8		T135	8		T200	4
auto[1]	values[5]	values[7]	243	1			T56	74		T135	7		T203	13
auto[1]	values[6]	values[0]	309	1			T40	14		T56	8		T177	8
auto[1]	values[6]	values[1]	178	1			T40	6		T200	5		T195	10
auto[1]	values[6]	values[2]	142	1			T90	13		T98	6		T200	5
auto[1]	values[6]	values[3]	138	1			T98	7		T200	12		T192	7
auto[1]	values[6]	values[4]	127	1			T30	2		T32	8		T135	6
auto[1]	values[6]	values[5]	208	1			T57	15		T32	7		T194	19
auto[1]	values[6]	values[6]	211	1			T15	56		T56	7		T32	7
auto[1]	values[6]	values[7]	265	1			T40	7		T30	25		T32	33
auto[1]	values[7]	values[0]	266	1			T135	38		T158	13		T194	69
auto[1]	values[7]	values[1]	288	1			T34	14		T30	196		T216	7
auto[1]	values[7]	values[2]	206	1			T55	10		T32	6		T90	12
auto[1]	values[7]	values[3]	180	1			T6	6		T177	8		T195	8
auto[1]	values[7]	values[4]	150	1			T51	16		T55	11		T90	21
auto[1]	values[7]	values[5]	201	1			T30	8		T211	5		T192	53
auto[1]	values[7]	values[6]	152	1			T135	17		T203	10		T198	7
auto[1]	values[7]	values[7]	121	1			T272	7		T284	12		T285	9