Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

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Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	419	1			T12	2		T15	1		T46	1
auto[ReadAddrCrossIntoMailbox]	343	1			T12	2		T46	1		T40	2
auto[ReadAddrCrossOutOfMailbox]	340	1			T12	4		T15	2		T46	1
auto[ReadAddrCrossAllMailbox]	230	1			T12	2		T46	3		T30	3
auto[ReadAddrOutsideMailbox]	3543	1			T5	2		T8	10		T12	2

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2404

1

T5

1

T8

5

T12

6

auto[1]

2471

1

T5

1

T8

5

T12

6

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	804	1			T8	4		T15	6		T35	2
read_ops[0x0b]	824	1			T5	2		T15	3		T46	4
read_ops[0x3b]	813	1			T12	6		T34	2		T50	2
read_ops[0x6b]	847	1			T8	2		T12	2		T15	5
read_ops[0xbb]	773	1			T15	1		T36	2		T49	2
read_ops[0xeb]	814	1			T8	4		T12	4		T15	4

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	18	1			T100	1		T55	1		T177	2
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	35	1			T100	1		T30	1		T57	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	35	1			T90	1		T200	3		T218	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	26	1			T57	2		T203	1		T200	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	37	1			T15	1		T46	1		T30	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	32	1			T56	1		T203	2		T200	2
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	17	1			T177	1		T90	1		T286	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	17	1			T30	1		T32	2		T286	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	292	1			T8	2		T15	5		T35	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	295	1			T8	2		T35	1		T46	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	34	1			T30	2		T90	2		T218	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	34	1			T46	1		T57	1		T98	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	33	1			T40	1		T53	1		T56	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	26	1			T57	1		T98	1		T218	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	34	1			T56	1		T32	1		T135	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	30	1			T218	1		T195	1		T249	2
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	22	1			T46	2		T32	1		T200	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	17	1			T203	1		T98	1		T200	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	280	1			T5	1		T46	1		T227	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	314	1			T5	1		T15	3		T227	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	38	1			T12	1		T100	1		T232	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	39	1			T12	1		T100	1		T30	2
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	26	1			T12	1		T30	1		T55	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	25	1			T12	1		T53	1		T56	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	37	1			T57	2		T98	1		T158	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	25	1			T90	1		T203	1		T249	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	16	1			T12	1		T90	1		T159	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	17	1			T12	1		T53	1		T234	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	289	1			T34	1		T50	1		T51	2
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	301	1			T34	1		T50	1		T51	2
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	38	1			T57	1		T32	1		T90	2
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	30	1			T177	1		T137	1		T203	2
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	28	1			T53	1		T56	1		T286	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	38	1			T46	1		T30	2		T55	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	20	1			T15	1		T56	1		T32	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	37	1			T40	1		T30	1		T55	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	28	1			T57	1		T90	2		T98	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	30	1			T30	1		T98	1		T286	2
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	301	1			T8	1		T12	1		T15	2
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	297	1			T8	1		T12	1		T15	2
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	33	1			T30	1		T56	1		T57	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	39	1			T159	1		T287	2		T199	2
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	25	1			T40	1		T30	1		T56	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	30	1			T30	1		T98	1		T286	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	19	1			T30	1		T203	1		T98	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	19	1			T286	1		T159	1		T278	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	19	1			T135	1		T203	1		T218	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	21	1			T30	1		T194	1		T278	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	280	1			T15	1		T36	1		T49	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	288	1			T36	1		T49	1		T40	3
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	46	1			T100	4		T30	1		T57	2
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	35	1			T15	1		T100	4		T30	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	32	1			T56	1		T203	1		T98	3
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	19	1			T53	1		T57	2		T158	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	21	1			T12	2		T135	1		T200	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	29	1			T12	2		T218	1		T249	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	11	1			T46	1		T194	1		T198	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	15	1			T192	1		T275	1		T288	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	295	1			T8	2		T15	1		T34	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	311	1			T8	2		T15	2		T34	1