Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3800	1			T15	55		T36	8		T100	20
values[1]	4249	1			T10	12		T12	16		T58	2
values[2]	3804	1			T118	22		T40	20		T30	70
values[3]	4420	1			T15	68		T34	14		T50	20
values[4]	4060	1			T227	8		T213	2		T30	237
values[5]	3357	1			T6	6		T35	2		T46	20
values[6]	4132	1			T5	4		T15	75		T80	20
values[7]	3353	1			T8	14		T9	2		T49	12

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3381	1			T36	8		T100	20		T54	16
values[1]	3831	1			T10	12		T12	16		T15	55
values[2]	4090	1			T58	2		T50	20		T30	278
values[3]	3919	1			T6	6		T15	55		T34	14
values[4]	3768	1			T8	14		T40	40		T75	36
values[5]	4097	1			T9	2		T15	20		T49	12
values[6]	4253	1			T227	8		T52	14		T40	20
values[7]	3836	1			T5	4		T15	68		T35	2

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30414

1

T5

4

T6

6

T8

14

auto[1]

761

1

T15

2

T46

3

T51

4

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	304	1			T36	8		T100	20		T200	20
auto[0]	values[0]	values[1]	404	1			T40	20		T47	12		T55	20
auto[0]	values[0]	values[2]	411	1			T56	109		T255	14		T195	59
auto[0]	values[0]	values[3]	394	1			T15	54		T57	40		T98	15
auto[0]	values[0]	values[4]	756	1			T56	20		T177	20		T135	20
auto[0]	values[0]	values[5]	314	1			T268	6		T56	17		T216	35
auto[0]	values[0]	values[6]	605	1			T218	20		T159	89		T261	10
auto[0]	values[0]	values[7]	522	1			T135	20		T203	31		T98	39
auto[0]	values[1]	values[0]	453	1			T218	19		T198	34		T192	45
auto[0]	values[1]	values[1]	505	1			T10	12		T12	16		T53	50
auto[0]	values[1]	values[2]	749	1			T58	2		T53	32		T32	20
auto[0]	values[1]	values[3]	591	1			T30	20		T55	20		T90	51
auto[0]	values[1]	values[4]	452	1			T264	26		T55	20		T56	25
auto[0]	values[1]	values[5]	490	1			T46	19		T224	2		T32	94
auto[0]	values[1]	values[6]	587	1			T200	20		T217	10		T260	17
auto[0]	values[1]	values[7]	336	1			T32	51		T194	18		T252	20
auto[0]	values[2]	values[0]	561	1			T138	6		T200	19		T159	20
auto[0]	values[2]	values[1]	339	1			T118	22		T32	109		T257	2
auto[0]	values[2]	values[2]	421	1			T30	20		T98	20		T199	20
auto[0]	values[2]	values[3]	570	1			T30	30		T55	18		T56	19
auto[0]	values[2]	values[4]	431	1			T40	19		T56	20		T198	20
auto[0]	values[2]	values[5]	394	1			T135	26		T200	20		T198	20
auto[0]	values[2]	values[6]	430	1			T55	18		T56	108		T289	12
auto[0]	values[2]	values[7]	574	1			T30	20		T57	20		T158	65
auto[0]	values[3]	values[0]	387	1			T56	53		T135	28		T258	10
auto[0]	values[3]	values[1]	461	1			T244	22		T135	20		T190	36
auto[0]	values[3]	values[2]	533	1			T50	20		T30	20		T290	12
auto[0]	values[3]	values[3]	695	1			T34	14		T56	73		T203	20
auto[0]	values[3]	values[4]	317	1			T75	36		T53	20		T56	23
auto[0]	values[3]	values[5]	732	1			T55	18		T56	40		T269	4
auto[0]	values[3]	values[6]	617	1			T177	17		T158	21		T211	29
auto[0]	values[3]	values[7]	585	1			T15	68		T30	20		T135	39
auto[0]	values[4]	values[0]	466	1			T32	101		T198	37		T242	42
auto[0]	values[4]	values[1]	586	1			T30	19		T32	41		T98	20
auto[0]	values[4]	values[2]	615	1			T30	214		T159	55		T202	20
auto[0]	values[4]	values[3]	425	1			T90	19		T137	22		T159	53
auto[0]	values[4]	values[4]	305	1			T177	20		T135	52		T243	80
auto[0]	values[4]	values[5]	734	1			T53	207		T177	20		T203	21
auto[0]	values[4]	values[6]	375	1			T227	8		T158	19		T198	20
auto[0]	values[4]	values[7]	469	1			T213	2		T90	25		T235	8
auto[0]	values[5]	values[0]	222	1			T57	17		T263	22		T252	19
auto[0]	values[5]	values[1]	366	1			T30	20		T291	10		T198	30
auto[0]	values[5]	values[2]	392	1			T30	18		T98	59		T211	18
auto[0]	values[5]	values[3]	460	1			T6	6		T46	18		T96	16
auto[0]	values[5]	values[4]	328	1			T198	20		T292	16		T60	40
auto[0]	values[5]	values[5]	559	1			T53	166		T207	22		T135	20
auto[0]	values[5]	values[6]	454	1			T52	8		T158	20		T205	20
auto[0]	values[5]	values[7]	466	1			T35	2		T51	12		T55	20
auto[0]	values[6]	values[0]	460	1			T54	14		T30	20		T53	18
auto[0]	values[6]	values[1]	701	1			T15	55		T30	121		T56	20
auto[0]	values[6]	values[2]	468	1			T55	20		T158	22		T195	19
auto[0]	values[6]	values[3]	379	1			T53	39		T137	20		T293	12
auto[0]	values[6]	values[4]	445	1			T40	19		T294	6		T135	20
auto[0]	values[6]	values[5]	399	1			T15	19		T80	20		T53	20
auto[0]	values[6]	values[6]	603	1			T208	18		T90	20		T137	32
auto[0]	values[6]	values[7]	569	1			T5	4		T101	2		T295	10
auto[0]	values[7]	values[0]	446	1			T219	20		T159	39		T296	14
auto[0]	values[7]	values[1]	363	1			T46	20		T40	38		T254	12
auto[0]	values[7]	values[2]	395	1			T53	83		T57	20		T98	18
auto[0]	values[7]	values[3]	298	1			T56	69		T209	4		T195	19
auto[0]	values[7]	values[4]	656	1			T8	14		T57	19		T133	14
auto[0]	values[7]	values[5]	388	1			T9	2		T49	12		T97	10
auto[0]	values[7]	values[6]	468	1			T40	20		T30	35		T232	4
auto[0]	values[7]	values[7]	234	1			T173	2		T90	19		T278	20
auto[1]	values[0]	values[0]	11	1			T194	1		T271	1		T297	4
auto[1]	values[0]	values[1]	9	1			T90	2		T194	1		T198	1
auto[1]	values[0]	values[2]	11	1			T195	4		T298	4		T275	1
auto[1]	values[0]	values[3]	14	1			T15	1		T98	5		T299	2
auto[1]	values[0]	values[4]	10	1			T194	2		T202	1		T206	3
auto[1]	values[0]	values[5]	13	1			T56	3		T277	2		T300	3
auto[1]	values[0]	values[6]	11	1			T159	2		T211	1		T271	1
auto[1]	values[0]	values[7]	11	1			T203	2		T98	1		T301	2
auto[1]	values[1]	values[0]	9	1			T218	1		T198	1		T192	1
auto[1]	values[1]	values[1]	9	1			T194	1		T211	1		T165	2
auto[1]	values[1]	values[2]	6	1			T252	1		T186	1		T61	1
auto[1]	values[1]	values[3]	14	1			T279	4		T302	2		T192	2
auto[1]	values[1]	values[4]	11	1			T56	1		T275	1		T237	2
auto[1]	values[1]	values[5]	13	1			T46	1		T194	3		T303	2
auto[1]	values[1]	values[6]	15	1			T198	1		T276	1		T271	2
auto[1]	values[1]	values[7]	9	1			T32	1		T194	2		T304	5
auto[1]	values[2]	values[0]	7	1			T200	1		T211	1		T285	1
auto[1]	values[2]	values[1]	8	1			T205	2		T212	2		T305	1
auto[1]	values[2]	values[2]	9	1			T277	2		T306	1		T307	5
auto[1]	values[2]	values[3]	15	1			T55	2		T56	1		T178	2
auto[1]	values[2]	values[4]	9	1			T40	1		T278	2		T308	4
auto[1]	values[2]	values[5]	7	1			T242	1		T276	1		T271	2
auto[1]	values[2]	values[6]	14	1			T55	2		T198	5		T225	1
auto[1]	values[2]	values[7]	15	1			T158	2		T202	1		T205	1
auto[1]	values[3]	values[0]	4	1			T225	2		T186	1		T309	1
auto[1]	values[3]	values[1]	14	1			T194	1		T225	5		T237	1
auto[1]	values[3]	values[2]	11	1			T30	1		T212	1		T308	1
auto[1]	values[3]	values[3]	18	1			T195	1		T310	2		T60	3
auto[1]	values[3]	values[4]	6	1			T56	1		T311	1		T142	2
auto[1]	values[3]	values[5]	12	1			T55	2		T90	1		T159	3
auto[1]	values[3]	values[6]	20	1			T177	3		T158	1		T276	1
auto[1]	values[3]	values[7]	8	1			T135	2		T98	1		T198	2
auto[1]	values[4]	values[0]	5	1			T242	1		T306	1		T300	2
auto[1]	values[4]	values[1]	17	1			T30	1		T32	1		T249	1
auto[1]	values[4]	values[2]	19	1			T30	3		T159	1		T64	5
auto[1]	values[4]	values[3]	8	1			T90	2		T159	3		T195	1
auto[1]	values[4]	values[4]	9	1			T243	2		T312	2		T313	1
auto[1]	values[4]	values[5]	13	1			T53	4		T203	1		T243	1
auto[1]	values[4]	values[6]	6	1			T158	1		T304	1		T60	1
auto[1]	values[4]	values[7]	8	1			T276	1		T271	2		T197	1
auto[1]	values[5]	values[0]	6	1			T57	3		T252	1		T311	2
auto[1]	values[5]	values[1]	11	1			T198	1		T199	2		T283	1
auto[1]	values[5]	values[2]	20	1			T30	2		T98	1		T211	3
auto[1]	values[5]	values[3]	17	1			T46	2		T55	1		T314	2
auto[1]	values[5]	values[4]	10	1			T60	2		T315	1		T316	2
auto[1]	values[5]	values[5]	14	1			T53	4		T305	2		T140	2
auto[1]	values[5]	values[6]	17	1			T52	6		T158	1		T317	2
auto[1]	values[5]	values[7]	15	1			T51	4		T252	1		T284	2
auto[1]	values[6]	values[0]	24	1			T54	2		T53	2		T177	2
auto[1]	values[6]	values[1]	21	1			T30	5		T195	1		T304	3
auto[1]	values[6]	values[2]	12	1			T195	1		T191	4		T211	1
auto[1]	values[6]	values[3]	9	1			T195	1		T243	1		T281	1
auto[1]	values[6]	values[4]	4	1			T40	1		T277	1		T318	2
auto[1]	values[6]	values[5]	10	1			T15	1		T202	1		T205	2
auto[1]	values[6]	values[6]	18	1			T199	2		T60	1		T186	2
auto[1]	values[6]	values[7]	10	1			T212	2		T186	1		T319	1
auto[1]	values[7]	values[0]	16	1			T159	2		T60	1		T61	2
auto[1]	values[7]	values[1]	17	1			T40	2		T90	3		T191	1
auto[1]	values[7]	values[2]	18	1			T53	1		T98	2		T249	3
auto[1]	values[7]	values[3]	12	1			T195	1		T243	1		T320	2
auto[1]	values[7]	values[4]	19	1			T57	1		T321	2		T277	2
auto[1]	values[7]	values[5]	5	1			T98	2		T275	1		T322	1
auto[1]	values[7]	values[6]	13	1			T30	1		T55	1		T194	3
auto[1]	values[7]	values[7]	5	1			T90	1		T186	1		T38	3