Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	871	1			T79	20		T20	34		T31	17
all_values[1]	871	1			T79	20		T20	34		T31	17
all_values[2]	871	1			T79	20		T20	34		T31	17
all_values[3]	871	1			T79	20		T20	34		T31	17
all_values[4]	871	1			T79	20		T20	34		T31	17
all_values[5]	871	1			T79	20		T20	34		T31	17
all_values[6]	871	1			T79	20		T20	34		T31	17
all_values[7]	871	1			T79	20		T20	34		T31	17

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3738

1

T79

86

T20

136

T31

65

auto[1]

3230

1

T79

74

T20

136

T31

71

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2801

1

T79

54

T20

132

T31

61

auto[1]

4167

1

T79

106

T20

140

T31

75

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3958

1

T79

80

T20

176

T31

78

auto[1]

3010

1

T79

80

T20

96

T31

58

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	185	1			T79	4		T20	11		T31	2
all_values[0]	auto[0]	auto[0]	auto[1]	79	1			T79	3		T20	1		T33	1
all_values[0]	auto[0]	auto[1]	auto[0]	148	1			T79	3		T20	5		T31	3
all_values[0]	auto[0]	auto[1]	auto[1]	76	1			T20	5		T31	3		T158	1
all_values[0]	auto[1]	auto[0]	auto[1]	196	1			T79	5		T20	7		T31	2
all_values[0]	auto[1]	auto[1]	auto[1]	187	1			T79	5		T20	5		T31	7
all_values[1]	auto[0]	auto[0]	auto[0]	196	1			T79	4		T20	5		T31	5
all_values[1]	auto[0]	auto[0]	auto[1]	87	1			T20	10		T33	3		T176	3
all_values[1]	auto[0]	auto[1]	auto[0]	134	1			T79	4		T20	2		T31	7
all_values[1]	auto[0]	auto[1]	auto[1]	84	1			T79	1		T20	5		T31	1
all_values[1]	auto[1]	auto[0]	auto[1]	200	1			T79	7		T20	7		T33	1
all_values[1]	auto[1]	auto[1]	auto[1]	170	1			T79	4		T20	5		T31	4
all_values[2]	auto[0]	auto[0]	auto[0]	169	1			T79	3		T20	5		T31	3
all_values[2]	auto[0]	auto[0]	auto[1]	86	1			T79	3		T20	2		T31	1
all_values[2]	auto[0]	auto[1]	auto[0]	148	1			T79	3		T20	10		T31	3
all_values[2]	auto[0]	auto[1]	auto[1]	86	1			T79	1		T20	4		T31	2
all_values[2]	auto[1]	auto[0]	auto[1]	205	1			T79	6		T20	4		T31	4
all_values[2]	auto[1]	auto[1]	auto[1]	177	1			T79	4		T20	9		T31	4
all_values[3]	auto[0]	auto[0]	auto[0]	178	1			T79	2		T20	7		T31	5
all_values[3]	auto[0]	auto[0]	auto[1]	82	1			T79	4		T31	2		T176	1
all_values[3]	auto[0]	auto[1]	auto[0]	148	1			T79	3		T20	14		T31	2
all_values[3]	auto[0]	auto[1]	auto[1]	100	1			T79	3		T20	3		T31	2
all_values[3]	auto[1]	auto[0]	auto[1]	193	1			T79	1		T20	7		T31	4
all_values[3]	auto[1]	auto[1]	auto[1]	170	1			T79	7		T20	3		T31	2
all_values[4]	auto[0]	auto[0]	auto[0]	171	1			T20	8		T31	6		T33	1
all_values[4]	auto[0]	auto[0]	auto[1]	76	1			T20	1		T31	1		T33	1
all_values[4]	auto[0]	auto[1]	auto[0]	178	1			T79	6		T20	8		T31	4
all_values[4]	auto[0]	auto[1]	auto[1]	71	1			T79	3		T20	3		T176	2
all_values[4]	auto[1]	auto[0]	auto[1]	210	1			T79	1		T20	9		T31	6
all_values[4]	auto[1]	auto[1]	auto[1]	165	1			T79	10		T20	5		T33	5
all_values[5]	auto[0]	auto[0]	auto[0]	266	1			T79	7		T20	13		T31	4
all_values[5]	auto[0]	auto[1]	auto[0]	229	1			T79	3		T20	8		T31	5
all_values[5]	auto[1]	auto[0]	auto[1]	202	1			T79	8		T20	10		T31	3
all_values[5]	auto[1]	auto[1]	auto[1]	174	1			T79	2		T20	3		T31	5
all_values[6]	auto[0]	auto[0]	auto[0]	195	1			T79	3		T20	8		T31	1
all_values[6]	auto[0]	auto[0]	auto[1]	83	1			T79	2		T20	4		T31	3
all_values[6]	auto[0]	auto[1]	auto[0]	157	1			T79	3		T20	9		T31	3
all_values[6]	auto[0]	auto[1]	auto[1]	82	1			T79	1		T20	4		T31	2
all_values[6]	auto[1]	auto[0]	auto[1]	187	1			T79	6		T20	3		T31	5
all_values[6]	auto[1]	auto[1]	auto[1]	167	1			T79	5		T20	6		T31	3
all_values[7]	auto[0]	auto[0]	auto[0]	177	1			T79	6		T20	10		T31	3
all_values[7]	auto[0]	auto[0]	auto[1]	87	1			T79	5		T176	1		T158	1
all_values[7]	auto[0]	auto[1]	auto[0]	122	1			T20	9		T31	5		T33	4
all_values[7]	auto[0]	auto[1]	auto[1]	78	1			T20	2		T158	2		T160	1
all_values[7]	auto[1]	auto[0]	auto[1]	228	1			T79	6		T20	4		T31	5
all_values[7]	auto[1]	auto[1]	auto[1]	179	1			T79	3		T20	9		T31	4

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal