Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1794

1

T3

7

T7

7

T11

8

auto[1]

1772

1

T3

5

T7

11

T11

7

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1841

1

T11

15

T17

2

T28

23

auto[1]

1725

1

T3

12

T7

18

T25

14

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2886

1

T3

12

T7

18

T11

11

auto[1]

680

1

T11

4

T17

2

T28

12

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	708	1			T3	1		T7	3		T11	5
valid[1]	720	1			T3	4		T7	4		T11	1
valid[2]	713	1			T3	6		T7	3		T11	2
valid[3]	686	1			T3	1		T7	4		T11	4
valid[4]	739	1			T7	4		T11	3		T25	2

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	122	1			T11	3		T28	1		T59	1
auto[0]	auto[0]	valid[0]	auto[1]	186	1			T3	1		T25	2		T27	1
auto[0]	auto[0]	valid[1]	auto[0]	114	1			T28	1		T42	2		T44	2
auto[0]	auto[0]	valid[1]	auto[1]	176	1			T3	3		T7	1		T25	1
auto[0]	auto[0]	valid[2]	auto[0]	134	1			T11	1		T28	2		T331	1
auto[0]	auto[0]	valid[2]	auto[1]	170	1			T3	3		T7	2		T25	1
auto[0]	auto[0]	valid[3]	auto[0]	116	1			T11	1		T28	2		T42	2
auto[0]	auto[0]	valid[3]	auto[1]	164	1			T7	3		T25	2		T27	1
auto[0]	auto[0]	valid[4]	auto[0]	112	1			T11	1		T42	2		T43	1
auto[0]	auto[0]	valid[4]	auto[1]	160	1			T7	1		T25	1		T27	2
auto[0]	auto[1]	valid[0]	auto[0]	112	1			T11	2		T28	1		T42	1
auto[0]	auto[1]	valid[0]	auto[1]	163	1			T7	3		T25	1		T27	5
auto[0]	auto[1]	valid[1]	auto[0]	104	1			T11	1		T28	2		T42	1
auto[0]	auto[1]	valid[1]	auto[1]	177	1			T3	1		T7	3		T27	1
auto[0]	auto[1]	valid[2]	auto[0]	117	1			T11	1		T28	1		T42	3
auto[0]	auto[1]	valid[2]	auto[1]	162	1			T3	3		T7	1		T25	2
auto[0]	auto[1]	valid[3]	auto[0]	96	1			T11	1		T28	1		T42	1
auto[0]	auto[1]	valid[3]	auto[1]	178	1			T3	1		T7	1		T25	3
auto[0]	auto[1]	valid[4]	auto[0]	134	1			T42	3		T44	1		T20	3
auto[0]	auto[1]	valid[4]	auto[1]	189	1			T7	3		T25	1		T27	4
auto[1]	auto[0]	valid[0]	auto[0]	65	1			T17	1		T42	1		T354	1
auto[1]	auto[0]	valid[1]	auto[0]	75	1			T42	1		T74	1		T30	1
auto[1]	auto[0]	valid[2]	auto[0]	70	1			T17	1		T28	1		T42	2
auto[1]	auto[0]	valid[3]	auto[0]	56	1			T11	1		T28	3		T210	1
auto[1]	auto[0]	valid[4]	auto[0]	74	1			T11	1		T28	3		T43	2
auto[1]	auto[1]	valid[0]	auto[0]	60	1			T43	1		T335	1		T31	1
auto[1]	auto[1]	valid[1]	auto[0]	74	1			T28	1		T42	2		T337	1
auto[1]	auto[1]	valid[2]	auto[0]	60	1			T28	3		T194	1		T347	1
auto[1]	auto[1]	valid[3]	auto[0]	76	1			T11	1		T42	1		T44	2
auto[1]	auto[1]	valid[4]	auto[0]	70	1			T11	1		T28	1		T42	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal