Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

47017

1

T4

2

T11

314

T17

123

auto[1]

17166

1

T3

12

T7

259

T25

14

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

47018

1

T3

12

T4

1

T7

259

auto[1]

17165

1

T4

1

T11

96

T17

56

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	32584	1			T3	12		T4	1		T7	142
others[1]	5629	1			T7	15		T11	37		T17	15
others[2]	5471	1			T7	24		T11	33		T17	20
others[3]	6217	1			T7	25		T11	27		T17	8
interest[1]	3591	1			T7	13		T11	26		T17	13
interest[4]	21305	1			T3	12		T4	1		T7	96
interest[64]	10691	1			T4	1		T7	40		T11	52

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	14812	1			T4	1		T11	100		T17	33
auto[0]	auto[0]	others[1]	2684	1			T11	27		T17	8		T26	1
auto[0]	auto[0]	others[2]	2538	1			T11	24		T17	7		T28	21
auto[0]	auto[0]	others[3]	2956	1			T11	11		T17	2		T26	1
auto[0]	auto[0]	interest[1]	1697	1			T11	20		T17	5		T28	17
auto[0]	auto[0]	interest[4]	9593	1			T4	1		T11	53		T17	22
auto[0]	auto[0]	interest[64]	5165	1			T11	36		T17	12		T28	34
auto[0]	auto[1]	others[0]	8965	1			T3	12		T7	142		T25	14
auto[0]	auto[1]	others[1]	1473	1			T7	15		T17	1		T27	28
auto[0]	auto[1]	others[2]	1489	1			T7	24		T17	4		T27	28
auto[0]	auto[1]	others[3]	1632	1			T7	25		T17	4		T27	35
auto[0]	auto[1]	interest[1]	939	1			T7	13		T17	6		T27	29
auto[0]	auto[1]	interest[4]	5997	1			T3	12		T7	96		T25	14
auto[0]	auto[1]	interest[64]	2668	1			T7	40		T17	4		T27	54
auto[1]	auto[0]	others[0]	8807	1			T11	39		T17	24		T26	3
auto[1]	auto[0]	others[1]	1472	1			T11	10		T17	6		T26	1
auto[1]	auto[0]	others[2]	1444	1			T11	9		T17	9		T28	9
auto[1]	auto[0]	others[3]	1629	1			T11	16		T17	2		T26	1
auto[1]	auto[0]	interest[1]	955	1			T11	6		T17	2		T28	4
auto[1]	auto[0]	interest[4]	5715	1			T11	28		T17	19		T26	1
auto[1]	auto[0]	interest[64]	2858	1			T4	1		T11	16		T17	13

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal