Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2984880	1			T2	1		T3	1		T4	1
all_values[1]	2984880	1			T2	1		T3	1		T4	1
all_values[2]	2984880	1			T2	1		T3	1		T4	1
all_values[3]	2984880	1			T2	1		T3	1		T4	1
all_values[4]	2984880	1			T2	1		T3	1		T4	1
all_values[5]	2984880	1			T2	1		T3	1		T4	1
all_values[6]	2984880	1			T2	1		T3	1		T4	1
all_values[7]	2984880	1			T2	1		T3	1		T4	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23326752

1

T2

8

T3

8

T4

8

auto[1]

552288

1

T34

54

T37

57

T38

35

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23851678

1

T2

8

T3

8

T4

8

auto[1]

27362

1

T34

37

T69

30

T97

4

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2942813	1			T2	1		T3	1		T4	1
all_values[0]	auto[0]	auto[1]	12453	1			T34	4		T69	30		T97	2
all_values[0]	auto[1]	auto[0]	28797	1			T34	3		T37	7		T38	4
all_values[0]	auto[1]	auto[1]	817	1			T34	3		T37	1		T39	2
all_values[1]	auto[0]	auto[0]	2932829	1			T2	1		T3	1		T4	1
all_values[1]	auto[0]	auto[1]	8360	1			T34	3		T97	2		T36	144
all_values[1]	auto[1]	auto[0]	43306	1			T34	4		T37	2		T38	3
all_values[1]	auto[1]	auto[1]	385	1			T39	4		T179	9		T90	2
all_values[2]	auto[0]	auto[0]	2888538	1			T2	1		T3	1		T4	1
all_values[2]	auto[0]	auto[1]	3017	1			T34	1		T36	75		T71	3
all_values[2]	auto[1]	auto[0]	92952	1			T34	7		T37	7		T39	4
all_values[2]	auto[1]	auto[1]	373	1			T34	4		T37	2		T38	1
all_values[3]	auto[0]	auto[0]	2911039	1			T2	1		T3	1		T4	1
all_values[3]	auto[0]	auto[1]	205	1			T34	2		T37	3		T38	1
all_values[3]	auto[1]	auto[0]	73410	1			T34	7		T37	6		T38	5
all_values[3]	auto[1]	auto[1]	226	1			T34	3		T37	3		T38	3
all_values[4]	auto[0]	auto[0]	2877283	1			T2	1		T3	1		T4	1
all_values[4]	auto[0]	auto[1]	211	1			T37	4		T38	1		T39	2
all_values[4]	auto[1]	auto[0]	107195	1			T34	7		T37	3		T38	2
all_values[4]	auto[1]	auto[1]	191	1			T34	2		T37	4		T38	3
all_values[5]	auto[0]	auto[0]	2931820	1			T2	1		T3	1		T4	1
all_values[5]	auto[0]	auto[1]	167	1			T34	3		T37	3		T38	2
all_values[5]	auto[1]	auto[0]	52704	1			T37	4		T38	1		T39	3
all_values[5]	auto[1]	auto[1]	189	1			T34	1		T37	3		T38	1
all_values[6]	auto[0]	auto[0]	2879266	1			T2	1		T3	1		T4	1
all_values[6]	auto[0]	auto[1]	188	1			T34	2		T38	2		T39	4
all_values[6]	auto[1]	auto[0]	105242	1			T34	4		T37	8		T38	3
all_values[6]	auto[1]	auto[1]	184	1			T34	3		T38	3		T39	2
all_values[7]	auto[0]	auto[0]	2938362	1			T2	1		T3	1		T4	1
all_values[7]	auto[0]	auto[1]	201	1			T34	2		T37	2		T38	1
all_values[7]	auto[1]	auto[0]	46122	1			T34	2		T37	6		T38	4
all_values[7]	auto[1]	auto[1]	195	1			T34	4		T37	1		T38	2