Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.74 98.65 96.80 99.01 89.36 98.51 95.57 99.26


Total tests in report: 1130
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
48.35 48.35 75.76 75.76 50.13 50.13 53.26 53.26 17.78 17.78 59.75 59.75 72.89 72.89 8.86 8.86 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_tpm_rw.1533585510
69.50 21.16 95.05 19.30 88.42 38.29 84.68 31.42 33.33 15.56 93.67 33.92 80.36 7.47 10.99 2.13 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_read_buffer_direct.2049650109
80.00 10.50 96.98 1.92 91.68 3.25 85.57 0.89 75.56 42.22 96.21 2.54 85.06 4.70 28.96 17.97 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_flash_mode_ignore_cmds.382047291
83.10 3.10 97.42 0.45 92.80 1.13 87.15 1.58 75.56 0.00 96.79 0.58 85.20 0.14 46.78 17.82 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_stress_all.3957504882
85.68 2.58 97.50 0.07 93.03 0.23 87.45 0.30 75.56 0.00 96.89 0.10 85.34 0.14 64.01 17.23 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_stress_all.1487823745
87.95 2.26 97.93 0.43 93.63 0.60 88.34 0.89 86.67 11.11 97.29 0.39 85.48 0.14 66.29 2.28 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_upload.94344404
89.93 1.98 98.48 0.55 94.88 1.24 90.12 1.78 93.33 6.67 98.18 0.89 85.75 0.28 68.76 2.48 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_tpm_read_hw_reg.1454963593
91.61 1.68 98.50 0.02 95.06 0.18 91.50 1.38 93.33 0.00 98.22 0.03 94.05 8.30 70.59 1.83 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_tl_intg_err.206151200
92.67 1.06 98.53 0.03 95.20 0.14 91.50 0.00 93.33 0.00 98.25 0.03 94.05 0.00 77.82 7.23 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_flash_and_tpm_min_idle.3350990662
93.35 0.68 98.54 0.02 95.20 0.00 96.25 4.74 93.33 0.00 98.25 0.00 94.05 0.00 77.82 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_ram_cfg.1086010174
93.84 0.50 98.54 0.00 95.20 0.00 96.25 0.00 93.33 0.00 98.25 0.00 94.05 0.00 81.29 3.47 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_stress_all.221750228
94.29 0.44 98.54 0.00 95.30 0.10 98.81 2.57 93.33 0.00 98.30 0.05 94.19 0.14 81.53 0.25 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_sec_cm.3131741145
94.73 0.44 98.58 0.04 95.45 0.15 98.81 0.00 93.33 0.00 98.42 0.12 94.19 0.00 84.31 2.77 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_flash_and_tpm_min_idle.493498850
95.01 0.28 98.58 0.00 95.45 0.00 98.81 0.00 93.33 0.00 98.42 0.00 94.19 0.00 86.29 1.98 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_flash_and_tpm.2194294787
95.28 0.27 98.58 0.00 96.25 0.79 98.81 0.00 93.33 0.00 98.46 0.03 94.33 0.14 87.23 0.94 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_tl_errors.3699106551
95.53 0.25 98.59 0.01 96.27 0.03 98.81 0.00 93.33 0.00 98.47 0.02 94.33 0.00 88.91 1.68 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_flash_and_tpm_min_idle.250414051
95.72 0.19 98.59 0.00 96.38 0.10 98.81 0.00 93.33 0.00 98.47 0.00 94.47 0.14 90.00 1.09 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_flash_mode_ignore_cmds.3112972253
95.90 0.18 98.59 0.00 96.38 0.00 98.81 0.00 93.33 0.00 98.47 0.00 94.47 0.00 91.24 1.24 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_stress_all.3259254278
96.04 0.14 98.59 0.00 96.38 0.00 98.81 0.00 93.33 0.00 98.47 0.00 94.61 0.14 92.08 0.84 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_flash_and_tpm.2955036950
96.16 0.12 98.59 0.00 96.38 0.00 98.81 0.00 93.33 0.00 98.47 0.00 94.61 0.00 92.92 0.84 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_flash_all.117063626
96.28 0.12 98.59 0.00 96.38 0.00 98.81 0.00 93.33 0.00 98.47 0.00 95.44 0.83 92.92 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_aliasing.1439324511
96.38 0.10 98.59 0.00 96.38 0.00 98.81 0.00 93.33 0.00 98.47 0.00 95.44 0.00 93.61 0.69 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_flash_and_tpm.958016547
96.48 0.10 98.59 0.00 96.38 0.00 98.81 0.00 93.33 0.00 98.47 0.00 95.44 0.00 94.31 0.69 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_stress_all.4196208349
96.55 0.08 98.59 0.00 96.38 0.00 98.81 0.00 93.33 0.00 98.47 0.00 95.44 0.00 94.85 0.54 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_flash_and_tpm_min_idle.3798308382
96.62 0.07 98.59 0.00 96.39 0.01 98.81 0.00 93.33 0.00 98.47 0.00 95.44 0.00 95.30 0.45 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_flash_and_tpm_min_idle.2376529143
96.68 0.06 98.59 0.00 96.50 0.12 98.81 0.00 93.33 0.00 98.47 0.00 95.44 0.00 95.59 0.30 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_tpm_all.3047228291
96.73 0.06 98.59 0.00 96.50 0.00 98.81 0.00 93.33 0.00 98.47 0.00 95.44 0.00 95.99 0.40 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_flash_and_tpm.2164768956
96.79 0.06 98.59 0.00 96.50 0.00 98.81 0.00 93.33 0.00 98.47 0.00 95.44 0.00 96.39 0.40 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_stress_all.3195415379
96.83 0.04 98.59 0.00 96.50 0.00 98.81 0.00 93.33 0.00 98.47 0.00 95.44 0.00 96.68 0.30 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_flash_and_tpm.3926764500
96.87 0.04 98.62 0.03 96.54 0.04 99.01 0.20 93.33 0.00 98.47 0.00 95.44 0.00 96.68 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_alert_test.3377264567
96.91 0.04 98.62 0.00 96.54 0.00 99.01 0.00 93.33 0.00 98.47 0.00 95.44 0.00 96.93 0.25 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_flash_all.3815281016
96.94 0.03 98.62 0.00 96.55 0.01 99.01 0.00 93.33 0.00 98.47 0.00 95.44 0.00 97.13 0.20 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_flash_mode.2522295999
96.96 0.03 98.62 0.00 96.55 0.00 99.01 0.00 93.33 0.00 98.47 0.00 95.44 0.00 97.33 0.20 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/5.spi_device_tl_intg_err.3376779904
96.99 0.03 98.62 0.00 96.55 0.00 99.01 0.00 93.33 0.00 98.47 0.00 95.44 0.00 97.52 0.20 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_flash_mode_ignore_cmds.2608856847
97.02 0.03 98.62 0.00 96.55 0.00 99.01 0.00 93.33 0.00 98.47 0.00 95.44 0.00 97.72 0.20 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_stress_all.989382741
97.05 0.03 98.62 0.00 96.55 0.00 99.01 0.00 93.33 0.00 98.47 0.00 95.57 0.14 97.77 0.05 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_stress_all.1898706835
97.07 0.02 98.62 0.00 96.66 0.10 99.01 0.00 93.33 0.00 98.47 0.00 95.57 0.00 97.82 0.05 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_tl_errors.2403641366
97.09 0.02 98.62 0.00 96.66 0.00 99.01 0.00 93.33 0.00 98.47 0.00 95.57 0.00 97.97 0.15 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_flash_mode.1024521573
97.11 0.02 98.62 0.00 96.66 0.00 99.01 0.00 93.33 0.00 98.47 0.00 95.57 0.00 98.12 0.15 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_flash_and_tpm.1025584639
97.13 0.02 98.62 0.00 96.66 0.00 99.01 0.00 93.33 0.00 98.47 0.00 95.57 0.00 98.27 0.15 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_flash_mode_ignore_cmds.3045977280
97.15 0.02 98.62 0.00 96.66 0.00 99.01 0.00 93.33 0.00 98.47 0.00 95.57 0.00 98.42 0.15 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_flash_all.3669254167
97.17 0.01 98.62 0.00 96.66 0.00 99.01 0.00 93.33 0.00 98.47 0.00 95.57 0.00 98.51 0.10 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/16.spi_device_tl_intg_err.4102938580
97.18 0.01 98.62 0.00 96.66 0.00 99.01 0.00 93.33 0.00 98.47 0.00 95.57 0.00 98.61 0.10 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_stress_all.1966224593
97.20 0.01 98.62 0.00 96.66 0.00 99.01 0.00 93.33 0.00 98.47 0.00 95.57 0.00 98.71 0.10 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_flash_mode.1383221038
97.21 0.01 98.62 0.00 96.66 0.00 99.01 0.00 93.33 0.00 98.47 0.00 95.57 0.00 98.81 0.10 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_stress_all.1541837153
97.23 0.01 98.62 0.00 96.66 0.00 99.01 0.00 93.33 0.00 98.47 0.00 95.57 0.00 98.91 0.10 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_flash_and_tpm.4257672001
97.24 0.01 98.62 0.00 96.66 0.00 99.01 0.00 93.33 0.00 98.47 0.00 95.57 0.00 99.01 0.10 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_flash_mode_ignore_cmds.2913160075
97.25 0.01 98.64 0.02 96.70 0.04 99.01 0.00 93.33 0.00 98.47 0.00 95.57 0.00 99.01 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_csb_read.1970397436
97.26 0.01 98.64 0.00 96.75 0.05 99.01 0.00 93.33 0.00 98.47 0.00 95.57 0.00 99.01 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_tl_errors.2343963026
97.26 0.01 98.64 0.00 96.75 0.00 99.01 0.00 93.33 0.00 98.47 0.00 95.57 0.00 99.06 0.05 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_flash_all.2764029443
97.27 0.01 98.64 0.00 96.75 0.00 99.01 0.00 93.33 0.00 98.47 0.00 95.57 0.00 99.11 0.05 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_flash_and_tpm_min_idle.4111675369
97.28 0.01 98.64 0.00 96.75 0.00 99.01 0.00 93.33 0.00 98.47 0.00 95.57 0.00 99.16 0.05 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_flash_mode.3357247661
97.28 0.01 98.64 0.00 96.75 0.00 99.01 0.00 93.33 0.00 98.47 0.00 95.57 0.00 99.21 0.05 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_flash_and_tpm.3303832574
97.29 0.01 98.64 0.00 96.75 0.00 99.01 0.00 93.33 0.00 98.47 0.00 95.57 0.00 99.26 0.05 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_stress_all.1030515052
97.30 0.01 98.64 0.00 96.77 0.03 99.01 0.00 93.33 0.00 98.49 0.02 95.57 0.00 99.26 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_intercept.3497564219
97.30 0.01 98.65 0.01 96.77 0.00 99.01 0.00 93.33 0.00 98.51 0.02 95.57 0.00 99.26 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_mailbox.347089539
97.30 0.01 98.65 0.00 96.80 0.03 99.01 0.00 93.33 0.00 98.51 0.00 95.57 0.00 99.26 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_hw_reset.3304109883

Tests that do not contribute to grading

Name
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_bit_bash.2815030702
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.3317838359
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_rw.2872656325
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_intr_test.2892458619
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_mem_partial_access.2635715904
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_mem_walk.2358573090
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.742860877
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_tl_errors.3522117210
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_aliasing.2777047230
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_bit_bash.911998468
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_hw_reset.125577435
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.1205041980
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_rw.2719781673
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_intr_test.2701255597
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_mem_partial_access.3013928389
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_mem_walk.2766997704
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.271960838
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_tl_intg_err.3382970812
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.34596176
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_csr_rw.3648401735
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_intr_test.2741255041
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.2137852679
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_tl_intg_err.2570491897
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.836884400
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_csr_rw.2094510945
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_intr_test.1089231039
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.3270453809
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_tl_errors.3514867305
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/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_upload.974220338



Total test records in report: 1130
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_sec_cm.3494189533 Oct 09 10:25:16 AM UTC 24 Oct 09 10:25:19 AM UTC 24 93807420 ps
T2 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_ram_cfg.1086010174 Oct 09 10:23:47 AM UTC 24 Oct 09 10:23:50 AM UTC 24 15642534 ps
T3 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_csb_read.1970397436 Oct 09 10:23:47 AM UTC 24 Oct 09 10:23:50 AM UTC 24 65393519 ps
T4 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_tpm_sts_read.2304090305 Oct 09 10:23:50 AM UTC 24 Oct 09 10:23:52 AM UTC 24 49409670 ps
T5 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_tpm_rw.1533585510 Oct 09 10:23:50 AM UTC 24 Oct 09 10:23:53 AM UTC 24 368588087 ps
T6 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_alert_test.1653912326 Oct 09 10:25:20 AM UTC 24 Oct 09 10:25:23 AM UTC 24 14429612 ps
T7 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_alert_test.3377264567 Oct 09 10:23:53 AM UTC 24 Oct 09 10:23:55 AM UTC 24 26556033 ps
T8 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_tpm_read_hw_reg.1690108047 Oct 09 10:23:53 AM UTC 24 Oct 09 10:23:55 AM UTC 24 21741631 ps
T9 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_csb_read.3477763394 Oct 09 10:23:53 AM UTC 24 Oct 09 10:23:56 AM UTC 24 70260930 ps
T10 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_csb_read.2660474994 Oct 09 10:25:20 AM UTC 24 Oct 09 10:25:23 AM UTC 24 21089860 ps
T12 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_sec_cm.3131741145 Oct 09 10:23:53 AM UTC 24 Oct 09 10:23:56 AM UTC 24 382251758 ps
T11 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_cfg_cmd.2712394954 Oct 09 10:23:52 AM UTC 24 Oct 09 10:23:56 AM UTC 24 206014767 ps
T13 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_tpm_sts_read.2388981664 Oct 09 10:23:54 AM UTC 24 Oct 09 10:23:56 AM UTC 24 24661425 ps
T14 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_tpm_rw.3340645905 Oct 09 10:23:54 AM UTC 24 Oct 09 10:23:56 AM UTC 24 49569744 ps
T15 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_pass_cmd_filtering.2970152964 Oct 09 10:23:51 AM UTC 24 Oct 09 10:23:57 AM UTC 24 540487306 ps
T16 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_flash_mode.332371943 Oct 09 10:23:52 AM UTC 24 Oct 09 10:23:58 AM UTC 24 334863024 ps
T17 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_tpm_read_hw_reg.1454963593 Oct 09 10:23:48 AM UTC 24 Oct 09 10:23:59 AM UTC 24 5630359002 ps
T18 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_pass_addr_payload_swap.4233171380 Oct 09 10:23:52 AM UTC 24 Oct 09 10:23:59 AM UTC 24 99536491 ps
T19 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_intercept.3227069922 Oct 09 10:23:52 AM UTC 24 Oct 09 10:24:00 AM UTC 24 202237666 ps
T20 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_cfg_cmd.2240382376 Oct 09 10:23:57 AM UTC 24 Oct 09 10:24:03 AM UTC 24 344341658 ps
T21 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_sec_cm.2954915123 Oct 09 10:24:01 AM UTC 24 Oct 09 10:24:03 AM UTC 24 124005751 ps
T26 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_tpm_all.3852997094 Oct 09 10:23:50 AM UTC 24 Oct 09 10:24:04 AM UTC 24 9320844220 ps
T22 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_read_buffer_direct.2049650109 Oct 09 10:23:52 AM UTC 24 Oct 09 10:24:04 AM UTC 24 1370666291 ps
T23 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_read_buffer_direct.4088238379 Oct 09 10:23:57 AM UTC 24 Oct 09 10:24:05 AM UTC 24 208967239 ps
T104 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_alert_test.3934657374 Oct 09 10:24:04 AM UTC 24 Oct 09 10:24:06 AM UTC 24 94274811 ps
T27 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_csb_read.272896350 Oct 09 10:24:04 AM UTC 24 Oct 09 10:24:06 AM UTC 24 18165971 ps
T28 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_tpm_sts_read.443557065 Oct 09 10:24:07 AM UTC 24 Oct 09 10:24:09 AM UTC 24 85962836 ps
T32 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_tpm_rw.3042795354 Oct 09 10:24:07 AM UTC 24 Oct 09 10:24:09 AM UTC 24 33756292 ps
T24 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_upload.94344404 Oct 09 10:23:52 AM UTC 24 Oct 09 10:24:09 AM UTC 24 16608588580 ps
T29 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_tpm_read_hw_reg.1754504824 Oct 09 10:24:05 AM UTC 24 Oct 09 10:24:10 AM UTC 24 879411467 ps
T25 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_flash_mode.559496013 Oct 09 10:23:57 AM UTC 24 Oct 09 10:24:15 AM UTC 24 2116537884 ps
T103 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_cfg_cmd.3044327716 Oct 09 10:24:12 AM UTC 24 Oct 09 10:24:17 AM UTC 24 155070534 ps
T65 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_upload.3351893925 Oct 09 10:23:57 AM UTC 24 Oct 09 10:24:20 AM UTC 24 3877832878 ps
T377 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_flash_mode_ignore_cmds.3801377144 Oct 09 10:24:18 AM UTC 24 Oct 09 10:24:20 AM UTC 24 26819476 ps
T40 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_pass_addr_payload_swap.2564558833 Oct 09 10:23:56 AM UTC 24 Oct 09 10:24:21 AM UTC 24 35274771369 ps
T62 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_pass_addr_payload_swap.2726162947 Oct 09 10:24:10 AM UTC 24 Oct 09 10:24:24 AM UTC 24 4036175002 ps
T53 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_pass_cmd_filtering.2229720932 Oct 09 10:24:08 AM UTC 24 Oct 09 10:24:24 AM UTC 24 22957446478 ps
T58 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_intercept.485834484 Oct 09 10:24:10 AM UTC 24 Oct 09 10:24:24 AM UTC 24 696716950 ps
T59 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_flash_mode.2522295999 Oct 09 10:24:16 AM UTC 24 Oct 09 10:24:25 AM UTC 24 124127833 ps
T63 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_mailbox.1382056318 Oct 09 10:23:57 AM UTC 24 Oct 09 10:24:26 AM UTC 24 2271631631 ps
T102 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_read_buffer_direct.3130335551 Oct 09 10:24:18 AM UTC 24 Oct 09 10:24:27 AM UTC 24 328500578 ps
T61 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_upload.68876841 Oct 09 10:24:12 AM UTC 24 Oct 09 10:24:27 AM UTC 24 2638220123 ps
T378 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_alert_test.3518763291 Oct 09 10:24:26 AM UTC 24 Oct 09 10:24:28 AM UTC 24 28613379 ps
T101 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_intercept.730247115 Oct 09 10:23:57 AM UTC 24 Oct 09 10:24:28 AM UTC 24 1524247446 ps
T33 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_sec_cm.2030623675 Oct 09 10:24:25 AM UTC 24 Oct 09 10:24:28 AM UTC 24 39534440 ps
T30 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_tpm_sts_read.1303312697 Oct 09 10:25:27 AM UTC 24 Oct 09 10:25:29 AM UTC 24 91019377 ps
T379 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_csb_read.451240751 Oct 09 10:24:27 AM UTC 24 Oct 09 10:24:29 AM UTC 24 37736845 ps
T31 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_tpm_sts_read.3162208560 Oct 09 10:24:29 AM UTC 24 Oct 09 10:24:31 AM UTC 24 91290656 ps
T41 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_flash_mode_ignore_cmds.3112972253 Oct 09 10:23:57 AM UTC 24 Oct 09 10:24:31 AM UTC 24 6766174195 ps
T47 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_tpm_rw.3705482498 Oct 09 10:24:29 AM UTC 24 Oct 09 10:24:33 AM UTC 24 47391398 ps
T81 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_tpm_read_hw_reg.2346121434 Oct 09 10:24:28 AM UTC 24 Oct 09 10:24:33 AM UTC 24 304713537 ps
T82 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_pass_cmd_filtering.187495169 Oct 09 10:23:55 AM UTC 24 Oct 09 10:24:36 AM UTC 24 14414463584 ps
T83 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_upload.1584302572 Oct 09 10:24:32 AM UTC 24 Oct 09 10:24:37 AM UTC 24 133831089 ps
T42 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_tpm_all.3047228291 Oct 09 10:24:06 AM UTC 24 Oct 09 10:24:38 AM UTC 24 2539368257 ps
T98 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_cfg_cmd.4080196094 Oct 09 10:24:34 AM UTC 24 Oct 09 10:24:39 AM UTC 24 359888660 ps
T43 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_tpm_all.702198675 Oct 09 10:23:54 AM UTC 24 Oct 09 10:24:39 AM UTC 24 25083597129 ps
T56 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_flash_mode.3998044974 Oct 09 10:24:35 AM UTC 24 Oct 09 10:24:40 AM UTC 24 1630487742 ps
T34 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_stress_all.3287793736 Oct 09 10:24:41 AM UTC 24 Oct 09 10:24:44 AM UTC 24 210740064 ps
T99 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_read_buffer_direct.1900489338 Oct 09 10:24:38 AM UTC 24 Oct 09 10:24:45 AM UTC 24 221265464 ps
T184 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_alert_test.3595088547 Oct 09 10:24:44 AM UTC 24 Oct 09 10:24:46 AM UTC 24 159909381 ps
T35 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_sec_cm.2617034037 Oct 09 10:24:44 AM UTC 24 Oct 09 10:24:47 AM UTC 24 222732335 ps
T185 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_csb_read.1926610369 Oct 09 10:24:45 AM UTC 24 Oct 09 10:24:48 AM UTC 24 41561062 ps
T48 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_tpm_all.2371005696 Oct 09 10:24:28 AM UTC 24 Oct 09 10:24:48 AM UTC 24 17589623808 ps
T115 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_tpm_sts_read.3539596196 Oct 09 10:24:49 AM UTC 24 Oct 09 10:24:51 AM UTC 24 56431123 ps
T79 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_tpm_rw.3400543292 Oct 09 10:24:51 AM UTC 24 Oct 09 10:24:53 AM UTC 24 13622851 ps
T60 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_pass_addr_payload_swap.2518279691 Oct 09 10:24:30 AM UTC 24 Oct 09 10:24:54 AM UTC 24 23982032439 ps
T72 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_pass_addr_payload_swap.245823825 Oct 09 10:24:54 AM UTC 24 Oct 09 10:25:00 AM UTC 24 1450642872 ps
T46 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_flash_mode_ignore_cmds.382047291 Oct 09 10:23:52 AM UTC 24 Oct 09 10:25:03 AM UTC 24 4859908584 ps
T73 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_pass_cmd_filtering.293531778 Oct 09 10:24:52 AM UTC 24 Oct 09 10:25:04 AM UTC 24 896794049 ps
T74 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_pass_cmd_filtering.3357798407 Oct 09 10:24:29 AM UTC 24 Oct 09 10:25:06 AM UTC 24 7383374518 ps
T380 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_upload.2777215146 Oct 09 10:25:04 AM UTC 24 Oct 09 10:25:09 AM UTC 24 64437445 ps
T49 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_flash_and_tpm.2164768956 Oct 09 10:23:59 AM UTC 24 Oct 09 10:25:09 AM UTC 24 17997811219 ps
T75 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_mailbox.1939362087 Oct 09 10:25:01 AM UTC 24 Oct 09 10:25:10 AM UTC 24 354441236 ps
T76 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_cfg_cmd.86078553 Oct 09 10:25:05 AM UTC 24 Oct 09 10:25:10 AM UTC 24 495573210 ps
T77 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_mailbox.4212564826 Oct 09 10:24:32 AM UTC 24 Oct 09 10:25:11 AM UTC 24 2613624312 ps
T78 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_mailbox.347089539 Oct 09 10:23:52 AM UTC 24 Oct 09 10:25:14 AM UTC 24 8584052993 ps
T212 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_intercept.2144121609 Oct 09 10:24:55 AM UTC 24 Oct 09 10:25:15 AM UTC 24 2647357242 ps
T120 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_intercept.2233004883 Oct 09 10:24:30 AM UTC 24 Oct 09 10:25:19 AM UTC 24 3656390170 ps
T171 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_read_buffer_direct.3889206935 Oct 09 10:25:10 AM UTC 24 Oct 09 10:25:25 AM UTC 24 2484603995 ps
T381 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_tpm_read_hw_reg.3820743161 Oct 09 10:25:23 AM UTC 24 Oct 09 10:25:26 AM UTC 24 20550930 ps
T50 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_flash_mode_ignore_cmds.1229438810 Oct 09 10:25:10 AM UTC 24 Oct 09 10:25:27 AM UTC 24 3470086534 ps
T376 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_tpm_read_hw_reg.1243733109 Oct 09 10:24:49 AM UTC 24 Oct 09 10:25:29 AM UTC 24 30872987100 ps
T262 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_pass_cmd_filtering.2426029008 Oct 09 10:25:28 AM UTC 24 Oct 09 10:25:34 AM UTC 24 555752357 ps
T216 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_mailbox.192860834 Oct 09 10:24:11 AM UTC 24 Oct 09 10:25:35 AM UTC 24 26970682834 ps
T255 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_pass_addr_payload_swap.4157204753 Oct 09 10:25:30 AM UTC 24 Oct 09 10:25:37 AM UTC 24 211753389 ps
T80 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_tpm_rw.597931471 Oct 09 10:25:27 AM UTC 24 Oct 09 10:25:39 AM UTC 24 286200135 ps
T193 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_intercept.3481946614 Oct 09 10:25:30 AM UTC 24 Oct 09 10:25:41 AM UTC 24 651426231 ps
T382 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_cfg_cmd.986859906 Oct 09 10:25:38 AM UTC 24 Oct 09 10:25:42 AM UTC 24 199750928 ps
T258 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_upload.3355792087 Oct 09 10:25:35 AM UTC 24 Oct 09 10:25:43 AM UTC 24 371404718 ps
T66 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_flash_all.509681753 Oct 09 10:25:11 AM UTC 24 Oct 09 10:25:43 AM UTC 24 9568575094 ps
T57 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_flash_mode.87175780 Oct 09 10:25:07 AM UTC 24 Oct 09 10:25:49 AM UTC 24 9303894113 ps
T172 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_read_buffer_direct.3531235770 Oct 09 10:25:43 AM UTC 24 Oct 09 10:25:51 AM UTC 24 1234104532 ps
T100 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_tpm_all.2539714681 Oct 09 10:24:49 AM UTC 24 Oct 09 10:25:54 AM UTC 24 9491798419 ps
T383 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_alert_test.2578435174 Oct 09 10:25:52 AM UTC 24 Oct 09 10:25:54 AM UTC 24 82822953 ps
T173 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_flash_mode.66815243 Oct 09 10:25:40 AM UTC 24 Oct 09 10:25:56 AM UTC 24 431341586 ps
T375 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_tpm_sts_read.1157984579 Oct 09 10:27:40 AM UTC 24 Oct 09 10:27:43 AM UTC 24 145106847 ps
T384 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_csb_read.2508339874 Oct 09 10:25:55 AM UTC 24 Oct 09 10:25:57 AM UTC 24 61323946 ps
T69 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_flash_and_tpm_min_idle.493498850 Oct 09 10:23:59 AM UTC 24 Oct 09 10:26:00 AM UTC 24 4613153542 ps
T385 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_tpm_sts_read.2780479286 Oct 09 10:25:58 AM UTC 24 Oct 09 10:26:01 AM UTC 24 37403592 ps
T386 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_tpm_read_hw_reg.3423720349 Oct 09 10:25:56 AM UTC 24 Oct 09 10:26:02 AM UTC 24 2249681990 ps
T368 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_tpm_rw.2653226264 Oct 09 10:26:02 AM UTC 24 Oct 09 10:26:04 AM UTC 24 209340969 ps
T250 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_pass_cmd_filtering.1817578587 Oct 09 10:26:02 AM UTC 24 Oct 09 10:26:08 AM UTC 24 534463534 ps
T114 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_tpm_all.1331854559 Oct 09 10:25:27 AM UTC 24 Oct 09 10:26:08 AM UTC 24 22108657824 ps
T268 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_intercept.2402750367 Oct 09 10:26:05 AM UTC 24 Oct 09 10:26:09 AM UTC 24 46932414 ps
T64 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_flash_mode_ignore_cmds.2913160075 Oct 09 10:24:37 AM UTC 24 Oct 09 10:26:15 AM UTC 24 7956088107 ps
T208 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_cfg_cmd.2527331842 Oct 09 10:26:10 AM UTC 24 Oct 09 10:26:16 AM UTC 24 817018469 ps
T273 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_mailbox.2519215943 Oct 09 10:25:35 AM UTC 24 Oct 09 10:26:16 AM UTC 24 2897159406 ps
T54 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_flash_all.4254428609 Oct 09 10:23:58 AM UTC 24 Oct 09 10:26:18 AM UTC 24 18602638626 ps
T55 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_flash_mode_ignore_cmds.929760721 Oct 09 10:25:42 AM UTC 24 Oct 09 10:26:20 AM UTC 24 6668890332 ps
T70 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_pass_addr_payload_swap.4272305308 Oct 09 10:26:03 AM UTC 24 Oct 09 10:26:27 AM UTC 24 4134429808 ps
T96 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_upload.2903241665 Oct 09 10:26:09 AM UTC 24 Oct 09 10:26:29 AM UTC 24 8022356711 ps
T192 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_flash_all.1609790197 Oct 09 10:25:44 AM UTC 24 Oct 09 10:26:30 AM UTC 24 40161201405 ps
T387 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_alert_test.3391239862 Oct 09 10:26:31 AM UTC 24 Oct 09 10:26:33 AM UTC 24 15506765 ps
T97 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_flash_and_tpm_min_idle.2404405980 Oct 09 10:25:49 AM UTC 24 Oct 09 10:26:35 AM UTC 24 2144637329 ps
T388 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_csb_read.1251950646 Oct 09 10:26:34 AM UTC 24 Oct 09 10:26:36 AM UTC 24 89592220 ps
T389 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_read_buffer_direct.3410353026 Oct 09 10:26:17 AM UTC 24 Oct 09 10:26:37 AM UTC 24 2959270029 ps
T390 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_tpm_sts_read.894839167 Oct 09 10:26:39 AM UTC 24 Oct 09 10:26:42 AM UTC 24 122138026 ps
T371 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_tpm_rw.683802025 Oct 09 10:26:42 AM UTC 24 Oct 09 10:26:47 AM UTC 24 160230555 ps
T51 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_flash_mode_ignore_cmds.2448565380 Oct 09 10:26:17 AM UTC 24 Oct 09 10:26:48 AM UTC 24 5384274348 ps
T36 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_stress_all.1487823745 Oct 09 10:24:24 AM UTC 24 Oct 09 10:26:49 AM UTC 24 6689811753 ps
T187 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_flash_all.3887063297 Oct 09 10:23:52 AM UTC 24 Oct 09 10:26:51 AM UTC 24 74598185651 ps
T369 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_tpm_all.3452800875 Oct 09 10:26:38 AM UTC 24 Oct 09 10:26:52 AM UTC 24 3069823411 ps
T391 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_tpm_read_hw_reg.3585628659 Oct 09 10:26:37 AM UTC 24 Oct 09 10:26:52 AM UTC 24 3910448336 ps
T238 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_pass_addr_payload_swap.2383445700 Oct 09 10:26:49 AM UTC 24 Oct 09 10:26:55 AM UTC 24 547079037 ps
T284 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_cfg_cmd.3917033195 Oct 09 10:26:53 AM UTC 24 Oct 09 10:26:58 AM UTC 24 76419358 ps
T260 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_mailbox.3763765927 Oct 09 10:26:09 AM UTC 24 Oct 09 10:26:58 AM UTC 24 6645784445 ps
T209 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_upload.791599211 Oct 09 10:26:53 AM UTC 24 Oct 09 10:26:58 AM UTC 24 505294588 ps
T257 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_flash_mode.1352380563 Oct 09 10:26:16 AM UTC 24 Oct 09 10:26:59 AM UTC 24 1582326829 ps
T248 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_mailbox.1713540463 Oct 09 10:26:52 AM UTC 24 Oct 09 10:27:00 AM UTC 24 314469713 ps
T365 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_tpm_all.468383104 Oct 09 10:25:58 AM UTC 24 Oct 09 10:27:00 AM UTC 24 28125142483 ps
T272 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_pass_cmd_filtering.293549821 Oct 09 10:26:49 AM UTC 24 Oct 09 10:27:06 AM UTC 24 1945786556 ps
T392 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_read_buffer_direct.1850046949 Oct 09 10:26:59 AM UTC 24 Oct 09 10:27:07 AM UTC 24 702822013 ps
T393 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_alert_test.3731364012 Oct 09 10:27:07 AM UTC 24 Oct 09 10:27:09 AM UTC 24 20244341 ps
T394 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_csb_read.2802175871 Oct 09 10:27:08 AM UTC 24 Oct 09 10:27:10 AM UTC 24 52162181 ps
T395 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_flash_mode.4130621944 Oct 09 10:26:55 AM UTC 24 Oct 09 10:27:11 AM UTC 24 1304364865 ps
T71 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_flash_and_tpm_min_idle.685677399 Oct 09 10:23:52 AM UTC 24 Oct 09 10:27:15 AM UTC 24 113665934548 ps
T396 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_tpm_sts_read.562878525 Oct 09 10:27:13 AM UTC 24 Oct 09 10:27:16 AM UTC 24 147766403 ps
T227 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_intercept.2574016989 Oct 09 10:26:50 AM UTC 24 Oct 09 10:27:18 AM UTC 24 1827365515 ps
T188 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_flash_all.2244415945 Oct 09 10:26:18 AM UTC 24 Oct 09 10:27:20 AM UTC 24 3552705584 ps
T367 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_tpm_rw.3295120389 Oct 09 10:27:16 AM UTC 24 Oct 09 10:27:20 AM UTC 24 188529410 ps
T288 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_pass_cmd_filtering.2051988744 Oct 09 10:27:16 AM UTC 24 Oct 09 10:27:21 AM UTC 24 2692218534 ps
T397 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_tpm_read_hw_reg.147655734 Oct 09 10:27:11 AM UTC 24 Oct 09 10:27:24 AM UTC 24 1424703759 ps
T264 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_upload.401462508 Oct 09 10:27:22 AM UTC 24 Oct 09 10:27:26 AM UTC 24 631667573 ps
T281 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_cfg_cmd.1810908306 Oct 09 10:27:22 AM UTC 24 Oct 09 10:27:26 AM UTC 24 110018629 ps
T52 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_flash_and_tpm.1059421323 Oct 09 10:25:12 AM UTC 24 Oct 09 10:27:29 AM UTC 24 32092623769 ps
T37 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_stress_all.3624670344 Oct 09 10:25:50 AM UTC 24 Oct 09 10:27:30 AM UTC 24 6795880090 ps
T304 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_pass_addr_payload_swap.510010721 Oct 09 10:27:17 AM UTC 24 Oct 09 10:27:33 AM UTC 24 2636468966 ps
T313 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_intercept.487678279 Oct 09 10:27:19 AM UTC 24 Oct 09 10:27:34 AM UTC 24 1786505734 ps
T366 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_tpm_all.309221188 Oct 09 10:27:12 AM UTC 24 Oct 09 10:27:36 AM UTC 24 3002889022 ps
T234 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_flash_mode_ignore_cmds.3790665372 Oct 09 10:27:27 AM UTC 24 Oct 09 10:27:36 AM UTC 24 1961812676 ps
T67 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_flash_and_tpm_min_idle.2376529143 Oct 09 10:24:22 AM UTC 24 Oct 09 10:27:37 AM UTC 24 10886822422 ps
T398 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_alert_test.2629429082 Oct 09 10:27:37 AM UTC 24 Oct 09 10:27:39 AM UTC 24 13482224 ps
T399 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_read_buffer_direct.1193910467 Oct 09 10:27:27 AM UTC 24 Oct 09 10:27:39 AM UTC 24 2082839443 ps
T400 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_tpm_rw.1788653318 Oct 09 10:27:41 AM UTC 24 Oct 09 10:27:45 AM UTC 24 259221336 ps
T401 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_csb_read.29034651 Oct 09 10:27:38 AM UTC 24 Oct 09 10:27:40 AM UTC 24 15952340 ps
T402 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_tpm_read_hw_reg.508650426 Oct 09 10:27:40 AM UTC 24 Oct 09 10:27:51 AM UTC 24 3518951721 ps
T189 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_flash_mode_ignore_cmds.3273627715 Oct 09 10:26:58 AM UTC 24 Oct 09 10:27:52 AM UTC 24 2403164102 ps
T235 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_intercept.2997188547 Oct 09 10:27:46 AM UTC 24 Oct 09 10:27:54 AM UTC 24 176787514 ps
T243 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_pass_addr_payload_swap.85615350 Oct 09 10:27:43 AM UTC 24 Oct 09 10:27:55 AM UTC 24 1410061209 ps
T254 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_flash_mode.2836337679 Oct 09 10:27:25 AM UTC 24 Oct 09 10:27:56 AM UTC 24 6905356635 ps
T267 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_pass_cmd_filtering.3187924217 Oct 09 10:27:41 AM UTC 24 Oct 09 10:27:57 AM UTC 24 8420895137 ps
T282 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_cfg_cmd.1567744918 Oct 09 10:27:55 AM UTC 24 Oct 09 10:27:59 AM UTC 24 36092035 ps
T68 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_flash_all.117063626 Oct 09 10:24:39 AM UTC 24 Oct 09 10:27:59 AM UTC 24 62498919058 ps
T403 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_read_buffer_direct.808928979 Oct 09 10:27:57 AM UTC 24 Oct 09 10:28:05 AM UTC 24 89203775 ps
T213 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_mailbox.1728927353 Oct 09 10:27:21 AM UTC 24 Oct 09 10:28:06 AM UTC 24 8027133605 ps
T259 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_flash_and_tpm_min_idle.2167204771 Oct 09 10:27:01 AM UTC 24 Oct 09 10:28:08 AM UTC 24 5283510966 ps
T404 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_alert_test.3918859565 Oct 09 10:28:09 AM UTC 24 Oct 09 10:28:11 AM UTC 24 11354580 ps
T108 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_flash_and_tpm_min_idle.3350990662 Oct 09 10:25:12 AM UTC 24 Oct 09 10:28:13 AM UTC 24 24282195560 ps
T405 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_csb_read.2880998903 Oct 09 10:28:12 AM UTC 24 Oct 09 10:28:15 AM UTC 24 33813355 ps
T218 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_flash_and_tpm.958016547 Oct 09 10:23:52 AM UTC 24 Oct 09 10:29:50 AM UTC 24 30955374596 ps
T362 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_tpm_all.3556218091 Oct 09 10:27:40 AM UTC 24 Oct 09 10:28:16 AM UTC 24 4011771023 ps
T406 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_tpm_sts_read.2140081010 Oct 09 10:28:17 AM UTC 24 Oct 09 10:28:20 AM UTC 24 66402508 ps
T219 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_flash_and_tpm_min_idle.250414051 Oct 09 10:27:34 AM UTC 24 Oct 09 10:28:21 AM UTC 24 15884831886 ps
T407 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_tpm_rw.4121847225 Oct 09 10:28:20 AM UTC 24 Oct 09 10:28:23 AM UTC 24 55663912 ps
T271 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_upload.974220338 Oct 09 10:27:53 AM UTC 24 Oct 09 10:28:27 AM UTC 24 4469322055 ps
T309 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_pass_cmd_filtering.3818885008 Oct 09 10:28:22 AM UTC 24 Oct 09 10:28:30 AM UTC 24 223382711 ps
T191 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_flash_and_tpm_min_idle.3216061175 Oct 09 10:28:06 AM UTC 24 Oct 09 10:28:31 AM UTC 24 3669181697 ps
T266 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_intercept.3646959527 Oct 09 10:28:28 AM UTC 24 Oct 09 10:28:37 AM UTC 24 390161830 ps
T211 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_flash_and_tpm.2324286148 Oct 09 10:26:22 AM UTC 24 Oct 09 10:28:40 AM UTC 24 7945183380 ps
T408 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_cfg_cmd.2293276900 Oct 09 10:28:37 AM UTC 24 Oct 09 10:28:42 AM UTC 24 57895621 ps
T221 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_upload.850933482 Oct 09 10:28:32 AM UTC 24 Oct 09 10:28:43 AM UTC 24 1110004513 ps
T409 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_tpm_read_hw_reg.3383147452 Oct 09 10:28:15 AM UTC 24 Oct 09 10:28:46 AM UTC 24 4849536021 ps
T38 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_stress_all.1023481985 Oct 09 10:27:36 AM UTC 24 Oct 09 10:28:47 AM UTC 24 12771861836 ps
T236 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_flash_all.4091491357 Oct 09 10:27:59 AM UTC 24 Oct 09 10:28:48 AM UTC 24 8228333394 ps
T361 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_tpm_all.1703979610 Oct 09 10:28:17 AM UTC 24 Oct 09 10:28:49 AM UTC 24 4023191793 ps
T190 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_flash_and_tpm.2356228224 Oct 09 10:24:21 AM UTC 24 Oct 09 10:28:49 AM UTC 24 37467639207 ps
T295 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_pass_addr_payload_swap.1898140168 Oct 09 10:28:24 AM UTC 24 Oct 09 10:28:49 AM UTC 24 11907425289 ps
T224 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_mailbox.3365066408 Oct 09 10:27:53 AM UTC 24 Oct 09 10:28:52 AM UTC 24 28779809601 ps
T109 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_flash_and_tpm.2194294787 Oct 09 10:24:40 AM UTC 24 Oct 09 10:28:52 AM UTC 24 25422385498 ps
T39 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_stress_all.1966224593 Oct 09 10:23:53 AM UTC 24 Oct 09 10:28:52 AM UTC 24 67933505733 ps
T410 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_alert_test.2501426011 Oct 09 10:28:50 AM UTC 24 Oct 09 10:28:52 AM UTC 24 24679699 ps
T411 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_csb_read.2744172651 Oct 09 10:28:50 AM UTC 24 Oct 09 10:28:52 AM UTC 24 226488132 ps
T207 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_flash_mode_ignore_cmds.4080465243 Oct 09 10:27:57 AM UTC 24 Oct 09 10:28:55 AM UTC 24 8091120253 ps
T412 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_tpm_sts_read.4202150196 Oct 09 10:28:54 AM UTC 24 Oct 09 10:28:56 AM UTC 24 106421839 ps
T413 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_tpm_rw.3248115683 Oct 09 10:28:54 AM UTC 24 Oct 09 10:28:57 AM UTC 24 72567180 ps
T414 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_read_buffer_direct.1633289425 Oct 09 10:28:43 AM UTC 24 Oct 09 10:28:58 AM UTC 24 2913859666 ps
T415 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_tpm_read_hw_reg.3491512121 Oct 09 10:28:53 AM UTC 24 Oct 09 10:29:04 AM UTC 24 1596280699 ps
T416 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_flash_mode.4224486573 Oct 09 10:28:41 AM UTC 24 Oct 09 10:29:05 AM UTC 24 952670859 ps
T261 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_flash_all.205877387 Oct 09 10:26:59 AM UTC 24 Oct 09 10:29:06 AM UTC 24 41620642873 ps
T186 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_stress_all.1187050877 Oct 09 10:28:08 AM UTC 24 Oct 09 10:29:08 AM UTC 24 6288150132 ps
T116 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_cfg_cmd.4292429095 Oct 09 10:29:05 AM UTC 24 Oct 09 10:29:10 AM UTC 24 699643092 ps
T417 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_flash_mode.1680997061 Oct 09 10:29:05 AM UTC 24 Oct 09 10:29:10 AM UTC 24 280605190 ps
T178 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_stress_all.3259254278 Oct 09 10:24:01 AM UTC 24 Oct 09 10:29:10 AM UTC 24 18671414682 ps
T418 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_pass_cmd_filtering.996520959 Oct 09 10:28:55 AM UTC 24 Oct 09 10:29:11 AM UTC 24 603703583 ps
T374 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_flash_and_tpm.1561612258 Oct 09 10:28:49 AM UTC 24 Oct 09 10:29:11 AM UTC 24 4336176213 ps
T419 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_mailbox.2121194432 Oct 09 10:28:58 AM UTC 24 Oct 09 10:29:11 AM UTC 24 414495424 ps
T420 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_flash_all.258122909 Oct 09 10:29:11 AM UTC 24 Oct 09 10:29:13 AM UTC 24 21117894 ps
T421 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_alert_test.3728445265 Oct 09 10:29:12 AM UTC 24 Oct 09 10:29:14 AM UTC 24 30091383 ps
T422 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_csb_read.3407100326 Oct 09 10:29:12 AM UTC 24 Oct 09 10:29:14 AM UTC 24 48327360 ps
T423 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_read_buffer_direct.3699049938 Oct 09 10:29:09 AM UTC 24 Oct 09 10:29:15 AM UTC 24 335300960 ps
T354 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_flash_mode.491813662 Oct 09 10:27:56 AM UTC 24 Oct 09 10:29:16 AM UTC 24 17249830599 ps
T249 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_upload.3183821285 Oct 09 10:28:59 AM UTC 24 Oct 09 10:29:19 AM UTC 24 4092613946 ps
T424 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_tpm_sts_read.1432126959 Oct 09 10:29:17 AM UTC 24 Oct 09 10:29:19 AM UTC 24 84633030 ps
T425 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_tpm_read_hw_reg.504719659 Oct 09 10:29:15 AM UTC 24 Oct 09 10:29:19 AM UTC 24 2024042364 ps
T370 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_tpm_rw.1606029034 Oct 09 10:29:17 AM UTC 24 Oct 09 10:29:19 AM UTC 24 26384273 ps
T312 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_flash_all.108150740 Oct 09 10:28:47 AM UTC 24 Oct 09 10:29:20 AM UTC 24 8393139051 ps
T275 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_pass_cmd_filtering.731819322 Oct 09 10:29:17 AM UTC 24 Oct 09 10:29:21 AM UTC 24 83042668 ps
T363 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_tpm_all.1847961324 Oct 09 10:28:54 AM UTC 24 Oct 09 10:29:22 AM UTC 24 3504519524 ps
T426 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_pass_addr_payload_swap.2380872200 Oct 09 10:28:56 AM UTC 24 Oct 09 10:29:22 AM UTC 24 19315787774 ps
T310 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_intercept.2912584235 Oct 09 10:29:20 AM UTC 24 Oct 09 10:29:26 AM UTC 24 120280732 ps
T290 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_cfg_cmd.1527961777 Oct 09 10:29:21 AM UTC 24 Oct 09 10:29:27 AM UTC 24 462467925 ps
T319 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_upload.1985446485 Oct 09 10:29:20 AM UTC 24 Oct 09 10:29:28 AM UTC 24 4670531999 ps
T427 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_read_buffer_direct.3824797754 Oct 09 10:29:23 AM UTC 24 Oct 09 10:29:32 AM UTC 24 344285458 ps
T364 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_tpm_all.1680343833 Oct 09 10:29:15 AM UTC 24 Oct 09 10:29:37 AM UTC 24 3742745493 ps
T428 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_alert_test.2222161852 Oct 09 10:29:38 AM UTC 24 Oct 09 10:29:40 AM UTC 24 14443173 ps
T429 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_csb_read.3887812344 Oct 09 10:29:41 AM UTC 24 Oct 09 10:29:43 AM UTC 24 63948013 ps
T179 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_stress_all.3957504882 Oct 09 10:26:30 AM UTC 24 Oct 09 10:29:44 AM UTC 24 20043221062 ps
T231 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_flash_and_tpm_min_idle.3798308382 Oct 09 10:26:28 AM UTC 24 Oct 09 10:29:46 AM UTC 24 38130537689 ps
T305 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_pass_addr_payload_swap.2997983696 Oct 09 10:29:20 AM UTC 24 Oct 09 10:29:46 AM UTC 24 28411868081 ps
T117 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_intercept.3497564219 Oct 09 10:28:57 AM UTC 24 Oct 09 10:29:49 AM UTC 24 4125989296 ps
T307 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_mailbox.1289197632 Oct 09 10:28:31 AM UTC 24 Oct 09 10:29:48 AM UTC 24 18500149914 ps
T244 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_flash_all.2071069247 Oct 09 10:29:27 AM UTC 24 Oct 09 10:29:48 AM UTC 24 4565389675 ps
T430 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_tpm_sts_read.3733924040 Oct 09 10:29:46 AM UTC 24 Oct 09 10:29:49 AM UTC 24 165567156 ps
T269 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_flash_and_tpm_min_idle.2307512128 Oct 09 10:29:11 AM UTC 24 Oct 09 10:29:49 AM UTC 24 5982188830 ps
T431 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_tpm_rw.3065060220 Oct 09 10:29:48 AM UTC 24 Oct 09 10:29:54 AM UTC 24 465162805 ps
T432 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_mailbox.2390200851 Oct 09 10:29:50 AM UTC 24 Oct 09 10:29:54 AM UTC 24 117305389 ps
T357 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_flash_mode.1024521573 Oct 09 10:29:22 AM UTC 24 Oct 09 10:29:54 AM UTC 24 2812083318 ps
T276 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_pass_cmd_filtering.2298066868 Oct 09 10:29:49 AM UTC 24 Oct 09 10:29:55 AM UTC 24 8545807418 ps
T433 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_cfg_cmd.3071370467 Oct 09 10:29:51 AM UTC 24 Oct 09 10:29:56 AM UTC 24 77070233 ps
T318 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_upload.3877453106 Oct 09 10:29:50 AM UTC 24 Oct 09 10:29:57 AM UTC 24 899059785 ps
T434 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_flash_mode.1499114216 Oct 09 10:29:55 AM UTC 24 Oct 09 10:30:00 AM UTC 24 34089835 ps
T214 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_flash_all.3815281016 Oct 09 10:24:20 AM UTC 24 Oct 09 10:30:01 AM UTC 24 101712124725 ps
T435 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_read_buffer_direct.2481873899 Oct 09 10:29:55 AM UTC 24 Oct 09 10:30:02 AM UTC 24 1262576900 ps
T436 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_alert_test.353980051 Oct 09 10:30:01 AM UTC 24 Oct 09 10:30:03 AM UTC 24 11592048 ps
T437 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_csb_read.2157074055 Oct 09 10:30:02 AM UTC 24 Oct 09 10:30:04 AM UTC 24 17347957 ps
T438 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_tpm_all.4083885443 Oct 09 10:31:43 AM UTC 24 Oct 09 10:31:52 AM UTC 24 497556735 ps
T439 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_tpm_read_hw_reg.2642931581 Oct 09 10:29:45 AM UTC 24 Oct 09 10:30:06 AM UTC 24 33350009964 ps
T440 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_tpm_sts_read.3178337168 Oct 09 10:30:06 AM UTC 24 Oct 09 10:30:09 AM UTC 24 249025664 ps
T233 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_intercept.4042415733 Oct 09 10:29:50 AM UTC 24 Oct 09 10:30:10 AM UTC 24 1301178247 ps
T239 /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_pass_addr_payload_swap.3452845121 Oct 09 10:29:49 AM UTC 24 Oct 09 10:30:11 AM UTC 24 1242969033 ps
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