Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	35269	1			T11	6		T20	2		T24	10
auto[SpiFlashAddrCfg]	7723	1			T15	2		T18	2		T24	2
auto[SpiFlashAddr3b]	9419	1			T15	6		T16	2		T24	4
auto[SpiFlashAddr4b]	7813	1			T15	4		T16	1		T24	4

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33912

1

T11

6

T15

12

T16

3

auto[1]

26312

1

T18

2

T40

10

T62

2

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32162

1

T11

6

T15

4

T16

1

auto[1]

28062

1

T15

8

T16

2

T24

6

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	40256	1			T11	6		T15	4		T16	1
values[1]	1089	1			T61	6		T82	2		T46	7
values[2]	1427	1			T24	2		T41	2		T46	5
values[3]	1461	1			T59	1		T41	2		T82	2
values[4]	1467	1			T40	2		T61	6		T41	2
values[5]	1493	1			T15	2		T16	2		T61	4
values[6]	1551	1			T24	2		T53	2		T41	7
values[7]	1511	1			T15	4		T24	4		T25	2
values[8]	9969	1			T15	2		T18	2		T25	1

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

35275

1

T11

6

T15

12

T18

2

auto[1]

24949

1

T16

3

T25

3

T59

1

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

56864

1

T11

6

T15

10

T16

3

write

3360

1

T15

2

T24

2

T53

2

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

19376

1

T11

6

T15

4

T16

2

valids[0x1]

40848

1

T15

8

T16

1

T24

12

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1498	1			T24	4		T101	4		T41	3
internal_process_ops[0x5a]	1542	1			T24	2		T101	4		T41	3
internal_process_ops[0x05]	21503	1			T63	2		T41	3		T72	2
internal_process_ops[0x35]	1613	1			T24	2		T62	2		T61	2
internal_process_ops[0x15]	1583	1			T101	2		T41	3		T46	4
internal_process_ops[0x03]	1111	1			T15	2		T16	1		T25	2
internal_process_ops[0x0b]	1066	1			T15	2		T25	1		T101	4
internal_process_ops[0x3b]	1048	1			T16	2		T24	2		T61	2
internal_process_ops[0x6b]	1030	1			T40	2		T53	2		T61	4
internal_process_ops[0xbb]	1146	1			T53	6		T41	1		T82	2
internal_process_ops[0xeb]	1139	1			T101	2		T83	2		T46	5

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

58538

1

T11

6

T15

12

T16

3

auto[1]

1686

1

T41

4

T60

4

T46

7

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

57757

1

T11

6

T15

12

T16

3

auto[1]

2467

1

T41

1

T46

16

T49

8

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

12443

1

T11

6

T20

2

T24

10

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

7566

1

T62

2

T60

10

T72

2

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

2149

1

T24

2

T61

4

T101

6

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

2023

1

T18

2

T60

2

T46

8

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2708

1

T15

6

T24

2

T65

2

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2377

1

T40

6

T60

2

T72

4

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

2216

1

T15

4

T24

4

T53

14

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1980

1

T40

4

T60

2

T46

15

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

121

1

T46

3

T73

2

T49

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

98

1

T71

1

T68

2

T108

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

98

1

T46

1

T49

1

T36

3

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

106

1

T46

1

T64

6

T70

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

127

1

T15

2

T46

1

T49

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

99

1

T52

4

T37

1

T68

3

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

104

1

T46

1

T49

1

T69

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

110

1

T46

4

T69

4

T67

4

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

128

1

T24

2

T53

2

T64

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

80

1

T66

1

T64

2

T52

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

87

1

T46

1

T67

2

T68

4

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

134

1

T46

1

T49

3

T64

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

123

1

T46

2

T66

2

T69

3

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

119

1

T64

2

T36

1

T71

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

122

1

T46

3

T64

1

T36

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

157

1

T60

4

T46

1

T69

2

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

8165

1

T41

27

T54

81

T55

39

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

6282

1

T41

5

T54

57

T55

14

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1331

1

T41

12

T56

1

T54

5

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1377

1

T41

3

T54

12

T55

9

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

1861

1

T16

2

T25

2

T59

1

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1681

1

T41

9

T54

26

T55

16

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1344

1

T16

1

T25

1

T41

8

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1361

1

T41

6

T54

7

T55

8

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

104

1

T54

2

T187

3

T188

3

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

94

1

T41

2

T54

1

T187

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

101

1

T55

1

T97

2

T51

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

91

1

T54

1

T55

1

T188

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

82

1

T41

1

T55

2

T188

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

111

1

T54

4

T51

1

T187

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

114

1

T41

1

T54

2

T55

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

96

1

T54

1

T187

1

T189

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

96

1

T54

1

T51

3

T187

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

101

1

T55

2

T51

1

T189

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

71

1

T54

1

T97

2

T190

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

95

1

T54

2

T187

1

T189

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

114

1

T54

1

T97

1

T191

3

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

98

1

T41

2

T188

1

T189

3

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

82

1

T192

1

T187

1

T188

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

97

1

T54

2

T36

1

T188

1

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	4204	1			T11	6		T20	2		T24	2
auto[0]	values[0]	valids[0x1]	19177	1			T15	4		T24	10		T40	4
auto[0]	values[1]	valids[0x1]	606	1			T61	6		T82	2		T46	7
auto[0]	values[2]	valids[0x0]	548	1			T24	2		T46	3		T49	2
auto[0]	values[2]	valids[0x1]	294	1			T46	2		T49	5		T77	4
auto[0]	values[3]	valids[0x0]	584	1			T46	4		T49	4		T50	5
auto[0]	values[3]	valids[0x1]	290	1			T82	2		T72	2		T46	2
auto[0]	values[4]	valids[0x0]	554	1			T40	2		T61	4		T46	2
auto[0]	values[4]	valids[0x1]	343	1			T61	2		T46	2		T49	3
auto[0]	values[5]	valids[0x0]	593	1			T61	4		T82	2		T83	2
auto[0]	values[5]	valids[0x1]	319	1			T15	2		T46	1		T50	1
auto[0]	values[6]	valids[0x0]	560	1			T24	2		T53	2		T46	6
auto[0]	values[6]	valids[0x1]	365	1			T46	3		T49	2		T50	2
auto[0]	values[7]	valids[0x0]	579	1			T15	4		T24	2		T40	2
auto[0]	values[7]	valids[0x1]	282	1			T24	2		T65	2		T193	2
auto[0]	values[8]	valids[0x0]	3705	1			T18	2		T40	2		T53	10
auto[0]	values[8]	valids[0x1]	2272	1			T15	2		T101	4		T60	2
auto[1]	values[0]	valids[0x0]	3560	1			T41	16		T54	37		T55	23
auto[1]	values[0]	valids[0x1]	13315	1			T16	1		T41	29		T54	121
auto[1]	values[1]	valids[0x1]	483	1			T54	3		T55	2		T192	2
auto[1]	values[2]	valids[0x0]	344	1			T41	1		T55	3		T192	4
auto[1]	values[2]	valids[0x1]	241	1			T41	1		T54	2		T192	2
auto[1]	values[3]	valids[0x0]	339	1			T41	1		T173	1		T54	3
auto[1]	values[3]	valids[0x1]	248	1			T59	1		T41	1		T54	2
auto[1]	values[4]	valids[0x0]	327	1			T41	2		T54	2		T192	3
auto[1]	values[4]	valids[0x1]	243	1			T54	6		T55	1		T97	5
auto[1]	values[5]	valids[0x0]	339	1			T16	2		T41	1		T57	1
auto[1]	values[5]	valids[0x1]	242	1			T41	4		T54	3		T55	2
auto[1]	values[6]	valids[0x0]	356	1			T41	6		T56	1		T57	1
auto[1]	values[6]	valids[0x1]	270	1			T41	1		T54	2		T55	2
auto[1]	values[7]	valids[0x0]	390	1			T41	6		T54	5		T55	4
auto[1]	values[7]	valids[0x1]	260	1			T25	2		T54	3		T192	6
auto[1]	values[8]	valids[0x0]	2394	1			T41	5		T54	29		T55	23
auto[1]	values[8]	valids[0x1]	1598	1			T25	1		T41	6		T56	2