Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3354886

1

T11

12

T15

1

T16

175

auto[1]

38954

1

T41

3

T46

1133

T49

168

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

922041

1

T11

12

T15

1

T16

175

auto[1]

2471799

1

T24

1024

T63

5668

T61

6

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	549521	1			T11	5		T15	1		T16	20
auto[524288:1048575]	399091	1			T11	1		T16	153		T58	242
auto[1048576:1572863]	412847	1			T11	1		T16	2		T103	1
auto[1572864:2097151]	427471	1			T20	22		T58	235		T59	4
auto[2097152:2621439]	426866	1			T103	3		T58	1115		T101	1992
auto[2621440:3145727]	402211	1			T19	2		T103	211		T63	785
auto[3145728:3670015]	413041	1			T11	5		T19	323		T20	18
auto[3670016:4194303]	362792	1			T19	314		T25	6		T58	496

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2505105

1

T11

10

T15

1

T16

4

auto[1]

888735

1

T11

2

T16

171

T19

974

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2955989

1

T11

12

T15

1

T16

175

auto[1]

437851

1

T41

13

T46

86

T49

1436

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	170336	1			T11	5		T15	1		T16	20
auto[0]	auto[0]	auto[0:524287]	auto[1]	341450	1			T24	1024		T63	2833		T61	6
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	94071	1			T11	1		T16	153		T58	242
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	242770	1			T41	545		T46	385		T50	128
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	128429	1			T11	1		T16	2		T103	1
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	230534	1			T46	2490		T216	1		T66	1
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	117933	1			T20	22		T58	235		T59	4
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	239322	1			T63	2835		T41	3213		T49	2745
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	115251	1			T103	3		T58	1115		T101	1992
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	241771	1			T46	1281		T216	7		T66	2741
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	110998	1			T19	2		T103	211		T63	785
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	236304	1			T101	1		T46	256		T216	255
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	100541	1			T11	5		T19	323		T20	18
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	245205	1			T41	384		T46	256		T49	2586
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	69697	1			T19	314		T25	6		T58	496
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	238125	1			T101	2		T41	515		T46	1803
auto[0]	auto[1]	auto[0:524287]	auto[0]	1352	1			T46	7		T49	1		T69	1
auto[0]	auto[1]	auto[0:524287]	auto[1]	29100	1			T49	1		T64	256		T54	256
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	1029	1			T41	2		T46	17		T49	1
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	55475	1			T49	1		T69	517		T54	128
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	1368	1			T46	11		T69	1		T54	1
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	48457	1			T69	2155		T192	128		T97	128
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	1066	1			T41	11		T46	12		T49	2
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	65151	1			T49	688		T187	2697		T67	680
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	2921	1			T69	3		T55	5		T51	4
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	63683	1			T69	2823		T36	128		T189	1536
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	1119	1			T46	6		T49	1		T54	2
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	49076	1			T54	1		T36	5		T108	1
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	707	1			T64	31		T54	2		T55	25
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	62201	1			T64	4541		T54	2		T36	3
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	798	1			T46	7		T49	9		T69	2
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	48646	1			T49	647		T69	1		T64	3
auto[1]	auto[0]	auto[0:524287]	auto[0]	625	1			T46	3		T49	1		T69	4
auto[1]	auto[0]	auto[0:524287]	auto[1]	6073	1			T49	29		T69	197		T54	8
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	514	1			T46	11		T69	3		T64	30
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	4496	1			T46	1036		T69	110		T55	512
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	379	1			T46	7		T66	1		T64	4
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	2890	1			T66	32		T54	15		T51	621
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	391	1			T41	3		T46	3		T66	1
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	3007	1			T66	3		T69	88		T54	8
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	407	1			T46	27		T66	1		T69	1
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	2407	1			T66	7		T69	42		T55	282
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	502	1			T69	4		T97	1		T51	9
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	3037	1			T69	120		T36	23		T71	1
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	492	1			T46	18		T69	1		T55	12
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	3327	1			T69	48		T187	14		T188	10
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	413	1			T46	2		T49	2		T64	4
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	4292	1			T49	51		T97	3		T36	6
auto[1]	auto[1]	auto[0:524287]	auto[0]	67	1			T36	1		T189	2		T39	1
auto[1]	auto[1]	auto[0:524287]	auto[1]	518	1			T39	1		T261	27		T179	3
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	88	1			T46	16		T49	1		T69	1
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	648	1			T49	8		T69	28		T36	2
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	75	1			T36	1		T67	1		T189	3
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	715	1			T36	2		T67	4		T178	7
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	82	1			T46	3		T49	1		T187	1
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	519	1			T49	14		T187	16		T67	87
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	61	1			T108	2		T178	3		T214	2
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	365	1			T108	9		T178	1		T214	14
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	117	1			T54	1		T189	4		T108	1
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	1058	1			T54	21		T108	6		T261	37
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	109	1			T54	2		T51	7		T36	3
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	459	1			T54	16		T36	22		T187	1
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	103	1			T46	7		T49	3		T69	1
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	718	1			T49	58		T69	3		T67	10

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	2040293	1			T11	10		T15	1		T16	4
auto[0]	auto[0]	auto[1]	882444	1			T11	2		T16	171		T19	974
auto[0]	auto[1]	auto[0]	426651	1			T41	13		T46	60		T49	1348
auto[0]	auto[1]	auto[1]	5498	1			T49	3		T54	1		T187	1
auto[1]	auto[0]	auto[0]	32584	1			T41	2		T46	1102		T49	83
auto[1]	auto[0]	auto[1]	668	1			T41	1		T46	5		T66	1
auto[1]	auto[1]	auto[0]	5577	1			T46	22		T49	84		T69	33
auto[1]	auto[1]	auto[1]	125	1			T46	4		T49	1		T54	1