Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2984880	1			T2	1		T3	1		T4	1
all_pins[1]	2984880	1			T2	1		T3	1		T4	1
all_pins[2]	2984880	1			T2	1		T3	1		T4	1
all_pins[3]	2984880	1			T2	1		T3	1		T4	1
all_pins[4]	2984880	1			T2	1		T3	1		T4	1
all_pins[5]	2984880	1			T2	1		T3	1		T4	1
all_pins[6]	2984880	1			T2	1		T3	1		T4	1
all_pins[7]	2984880	1			T2	1		T3	1		T4	1

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	23769884	1			T2	8		T3	8		T4	8
values[0x1]	109156	1			T34	20		T37	14		T38	13
transitions[0x0=>0x1]	107664	1			T34	16		T37	13		T38	10
transitions[0x1=>0x0]	107675	1			T34	17		T37	13		T38	10

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2983991	1			T2	1		T3	1		T4	1
all_pins[0]	values[0x1]	889	1			T34	3		T37	1		T39	2
all_pins[0]	transitions[0x0=>0x1]	734	1			T34	3		T37	1		T39	2
all_pins[0]	transitions[0x1=>0x0]	274	1			T39	4		T179	6		T90	1
all_pins[1]	values[0x0]	2984451	1			T2	1		T3	1		T4	1
all_pins[1]	values[0x1]	429	1			T39	4		T179	9		T90	2
all_pins[1]	transitions[0x0=>0x1]	309	1			T39	1		T179	6		T44	1
all_pins[1]	transitions[0x1=>0x0]	269	1			T34	4		T37	2		T38	1
all_pins[2]	values[0x0]	2984491	1			T2	1		T3	1		T4	1
all_pins[2]	values[0x1]	389	1			T34	4		T37	2		T38	1
all_pins[2]	transitions[0x0=>0x1]	324	1			T34	4		T37	2		T38	1
all_pins[2]	transitions[0x1=>0x0]	161	1			T34	3		T37	3		T38	3
all_pins[3]	values[0x0]	2984654	1			T2	1		T3	1		T4	1
all_pins[3]	values[0x1]	226	1			T34	3		T37	3		T38	3
all_pins[3]	transitions[0x0=>0x1]	170	1			T34	3		T37	3		T38	3
all_pins[3]	transitions[0x1=>0x0]	135	1			T34	2		T37	4		T38	3
all_pins[4]	values[0x0]	2984689	1			T2	1		T3	1		T4	1
all_pins[4]	values[0x1]	191	1			T34	2		T37	4		T38	3
all_pins[4]	transitions[0x0=>0x1]	149	1			T34	2		T37	3		T38	3
all_pins[4]	transitions[0x1=>0x0]	1960	1			T34	1		T37	2		T38	1
all_pins[5]	values[0x0]	2982878	1			T2	1		T3	1		T4	1
all_pins[5]	values[0x1]	2002	1			T34	1		T37	3		T38	1
all_pins[5]	transitions[0x0=>0x1]	1052	1			T34	1		T37	3		T39	2
all_pins[5]	transitions[0x1=>0x0]	103885	1			T34	3		T38	2		T39	2
all_pins[6]	values[0x0]	2880045	1			T2	1		T3	1		T4	1
all_pins[6]	values[0x1]	104835	1			T34	3		T38	3		T39	2
all_pins[6]	transitions[0x0=>0x1]	104793	1			T34	1		T38	1		T39	1
all_pins[6]	transitions[0x1=>0x0]	153	1			T34	2		T37	1		T39	2
all_pins[7]	values[0x0]	2984685	1			T2	1		T3	1		T4	1
all_pins[7]	values[0x1]	195	1			T34	4		T37	1		T38	2
all_pins[7]	transitions[0x0=>0x1]	133	1			T34	2		T37	1		T38	2
all_pins[7]	transitions[0x1=>0x0]	838	1			T34	2		T37	1		T39	1