Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20411

1

T11

6

T15

12

T20

2

auto[1]

14864

1

T18

2

T40

10

T62

2

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4445	1			T24	20		T103	10		T63	2
values[1]	5267	1			T18	2		T49	73		T50	20
values[2]	4451	1			T11	6		T15	12		T61	26
values[3]	3950	1			T83	2		T46	20		T49	29
values[4]	3910	1			T101	20		T46	20		T49	50
values[5]	3951	1			T20	2		T62	2		T58	2
values[6]	4489	1			T65	2		T82	14		T78	8
values[7]	4812	1			T40	10		T53	16		T46	40

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4398	1			T101	20		T49	20		T262	2
values[1]	4143	1			T15	12		T103	10		T60	20
values[2]	4340	1			T18	2		T20	2		T63	2
values[3]	3915	1			T11	6		T72	6		T46	20
values[4]	4759	1			T65	2		T62	2		T53	16
values[5]	4264	1			T24	20		T46	20		T50	20
values[6]	5318	1			T40	10		T58	2		T46	40
values[7]	4138	1			T82	14		T83	2		T73	10

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	173	1			T214	8		T263	12		T165	11
auto[0]	values[0]	values[1]	396	1			T103	10		T49	60		T77	10
auto[0]	values[0]	values[2]	401	1			T63	2		T36	11		T109	11
auto[0]	values[0]	values[3]	336	1			T46	16		T234	17		T178	9
auto[0]	values[0]	values[4]	311	1			T98	12		T69	13		T36	13
auto[0]	values[0]	values[5]	498	1			T24	20		T96	106		T71	10
auto[0]	values[0]	values[6]	478	1			T46	8		T264	4		T108	12
auto[0]	values[0]	values[7]	230	1			T258	8		T69	15		T64	12
auto[0]	values[1]	values[0]	225	1			T179	23		T231	22		T226	4
auto[0]	values[1]	values[1]	316	1			T68	13		T259	14		T265	2
auto[0]	values[1]	values[2]	559	1			T49	63		T69	146		T266	12
auto[0]	values[1]	values[3]	362	1			T36	30		T52	13		T109	10
auto[0]	values[1]	values[4]	255	1			T69	11		T52	8		T67	12
auto[0]	values[1]	values[5]	241	1			T50	14		T267	2		T68	11
auto[0]	values[1]	values[6]	430	1			T250	10		T64	8		T38	11
auto[0]	values[1]	values[7]	435	1			T108	13		T109	11		T225	11
auto[0]	values[2]	values[0]	302	1			T36	12		T38	12		T179	11
auto[0]	values[2]	values[1]	336	1			T15	12		T46	12		T268	2
auto[0]	values[2]	values[2]	217	1			T68	11		T109	6		T179	20
auto[0]	values[2]	values[3]	317	1			T11	6		T234	4		T67	18
auto[0]	values[2]	values[4]	484	1			T61	26		T49	39		T69	11
auto[0]	values[2]	values[5]	367	1			T108	25		T225	9		T251	59
auto[0]	values[2]	values[6]	285	1			T46	9		T69	8		T36	8
auto[0]	values[2]	values[7]	188	1			T73	10		T269	18		T270	2
auto[0]	values[3]	values[0]	339	1			T216	14		T108	15		T217	131
auto[0]	values[3]	values[1]	355	1			T46	16		T68	11		T271	12
auto[0]	values[3]	values[2]	221	1			T49	18		T36	11		T67	12
auto[0]	values[3]	values[3]	239	1			T69	86		T272	10		T259	14
auto[0]	values[3]	values[4]	414	1			T69	103		T273	6		T71	28
auto[0]	values[3]	values[5]	169	1			T208	2		T44	13		T274	16
auto[0]	values[3]	values[6]	372	1			T37	33		T109	11		T178	10
auto[0]	values[3]	values[7]	309	1			T83	2		T69	14		T64	14
auto[0]	values[4]	values[0]	273	1			T101	20		T262	2		T108	15
auto[0]	values[4]	values[1]	204	1			T71	14		T275	4		T225	12
auto[0]	values[4]	values[2]	190	1			T221	10		T179	28		T276	8
auto[0]	values[4]	values[3]	398	1			T248	6		T108	31		T109	39
auto[0]	values[4]	values[4]	353	1			T277	28		T278	10		T217	10
auto[0]	values[4]	values[5]	244	1			T46	13		T260	12		T178	15
auto[0]	values[4]	values[6]	353	1			T49	43		T64	13		T68	13
auto[0]	values[4]	values[7]	330	1			T68	10		T95	12		T279	6
auto[0]	values[5]	values[0]	178	1			T69	12		T220	12		T280	6
auto[0]	values[5]	values[1]	106	1			T64	9		T281	2		T109	14
auto[0]	values[5]	values[2]	402	1			T20	2		T178	12		T179	9
auto[0]	values[5]	values[3]	109	1			T227	12		T282	2		T178	8
auto[0]	values[5]	values[4]	276	1			T64	14		T36	16		T67	16
auto[0]	values[5]	values[5]	240	1			T108	11		T220	8		T283	11
auto[0]	values[5]	values[6]	327	1			T58	2		T68	10		T180	10
auto[0]	values[5]	values[7]	503	1			T74	12		T50	4		T64	12
auto[0]	values[6]	values[0]	380	1			T69	118		T37	28		T67	8
auto[0]	values[6]	values[1]	562	1			T66	60		T67	50		T178	16
auto[0]	values[6]	values[2]	209	1			T120	14		T64	11		T209	49
auto[0]	values[6]	values[3]	296	1			T212	8		T220	21		T252	13
auto[0]	values[6]	values[4]	384	1			T65	2		T52	73		T37	11
auto[0]	values[6]	values[5]	390	1			T284	10		T214	11		T45	14
auto[0]	values[6]	values[6]	280	1			T78	8		T68	12		T108	12
auto[0]	values[6]	values[7]	242	1			T82	14		T285	4		T286	36
auto[0]	values[7]	values[0]	515	1			T49	10		T224	14		T287	8
auto[0]	values[7]	values[1]	280	1			T46	23		T193	8		T36	21
auto[0]	values[7]	values[2]	219	1			T76	2		T288	6		T235	10
auto[0]	values[7]	values[3]	290	1			T64	10		T52	11		T37	134
auto[0]	values[7]	values[4]	317	1			T53	16		T249	14		T44	19
auto[0]	values[7]	values[5]	204	1			T68	16		T231	26		T289	20
auto[0]	values[7]	values[6]	504	1			T69	10		T179	10		T44	10
auto[0]	values[7]	values[7]	293	1			T36	48		T67	25		T290	16
auto[1]	values[0]	values[0]	135	1			T214	12		T263	10		T165	9
auto[1]	values[0]	values[1]	272	1			T49	11		T247	12		T222	9
auto[1]	values[0]	values[2]	250	1			T70	20		T36	9		T109	11
auto[1]	values[0]	values[3]	154	1			T72	6		T46	4		T234	3
auto[1]	values[0]	values[4]	254	1			T69	7		T36	7		T37	8
auto[1]	values[0]	values[5]	240	1			T71	10		T52	7		T178	13
auto[1]	values[0]	values[6]	163	1			T46	12		T108	8		T179	12
auto[1]	values[0]	values[7]	154	1			T69	5		T64	8		T109	28
auto[1]	values[1]	values[0]	405	1			T179	25		T231	8		T291	26
auto[1]	values[1]	values[1]	116	1			T68	7		T259	7		T292	10
auto[1]	values[1]	values[2]	341	1			T18	2		T49	10		T69	9
auto[1]	values[1]	values[3]	340	1			T36	10		T52	7		T109	10
auto[1]	values[1]	values[4]	367	1			T69	55		T52	19		T67	8
auto[1]	values[1]	values[5]	284	1			T50	6		T68	9		T108	79
auto[1]	values[1]	values[6]	396	1			T64	12		T38	9		T109	76
auto[1]	values[1]	values[7]	195	1			T108	12		T109	12		T225	9
auto[1]	values[2]	values[0]	238	1			T36	8		T38	8		T179	34
auto[1]	values[2]	values[1]	212	1			T60	20		T46	8		T255	4
auto[1]	values[2]	values[2]	382	1			T68	44		T109	31		T179	9
auto[1]	values[2]	values[3]	148	1			T234	16		T67	6		T225	11
auto[1]	values[2]	values[4]	239	1			T49	6		T69	9		T214	11
auto[1]	values[2]	values[5]	351	1			T108	15		T225	95		T251	10
auto[1]	values[2]	values[6]	247	1			T46	11		T69	75		T36	13
auto[1]	values[2]	values[7]	138	1			T269	5		T283	12		T293	11
auto[1]	values[3]	values[0]	184	1			T108	10		T217	6		T294	7
auto[1]	values[3]	values[1]	322	1			T46	4		T68	9		T109	10
auto[1]	values[3]	values[2]	156	1			T49	11		T36	10		T67	11
auto[1]	values[3]	values[3]	165	1			T69	8		T259	6		T295	22
auto[1]	values[3]	values[4]	122	1			T69	7		T71	14		T178	12
auto[1]	values[3]	values[5]	167	1			T44	33		T274	4		T296	7
auto[1]	values[3]	values[6]	181	1			T37	7		T109	9		T178	11
auto[1]	values[3]	values[7]	235	1			T69	6		T64	6		T225	11
auto[1]	values[4]	values[0]	183	1			T108	5		T109	19		T231	23
auto[1]	values[4]	values[1]	153	1			T71	8		T225	16		T44	8
auto[1]	values[4]	values[2]	168	1			T179	11		T283	7		T297	55
auto[1]	values[4]	values[3]	243	1			T108	12		T109	11		T225	62
auto[1]	values[4]	values[4]	238	1			T278	10		T217	17		T229	14
auto[1]	values[4]	values[5]	174	1			T46	7		T178	12		T231	5
auto[1]	values[4]	values[6]	257	1			T49	7		T64	7		T68	7
auto[1]	values[4]	values[7]	149	1			T243	16		T68	19		T263	11
auto[1]	values[5]	values[0]	311	1			T69	55		T220	90		T298	6
auto[1]	values[5]	values[1]	85	1			T64	11		T109	6		T274	26
auto[1]	values[5]	values[2]	329	1			T178	43		T179	41		T45	8
auto[1]	values[5]	values[3]	103	1			T178	23		T179	33		T299	4
auto[1]	values[5]	values[4]	358	1			T62	2		T64	6		T36	15
auto[1]	values[5]	values[5]	146	1			T108	12		T220	12		T283	9
auto[1]	values[5]	values[6]	203	1			T68	10		T180	70		T300	4
auto[1]	values[5]	values[7]	275	1			T50	16		T64	8		T108	34
auto[1]	values[6]	values[0]	206	1			T69	10		T37	9		T67	12
auto[1]	values[6]	values[1]	275	1			T66	5		T67	34		T178	5
auto[1]	values[6]	values[2]	175	1			T64	9		T52	13		T37	10
auto[1]	values[6]	values[3]	190	1			T220	10		T252	7		T283	43
auto[1]	values[6]	values[4]	241	1			T52	43		T37	9		T68	7
auto[1]	values[6]	values[5]	237	1			T214	13		T45	7		T217	11
auto[1]	values[6]	values[6]	302	1			T68	8		T108	15		T38	6
auto[1]	values[6]	values[7]	120	1			T301	5		T302	24		T298	20
auto[1]	values[7]	values[0]	351	1			T49	10		T303	5		T256	10
auto[1]	values[7]	values[1]	153	1			T46	17		T36	4		T223	9
auto[1]	values[7]	values[2]	121	1			T304	6		T178	9		T225	8
auto[1]	values[7]	values[3]	225	1			T64	10		T52	61		T37	8
auto[1]	values[7]	values[4]	146	1			T238	2		T44	10		T222	6
auto[1]	values[7]	values[5]	312	1			T68	30		T231	6		T305	20
auto[1]	values[7]	values[6]	540	1			T40	10		T69	100		T179	10
auto[1]	values[7]	values[7]	342	1			T36	17		T67	121		T179	12