Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

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Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	395	1			T58	2		T101	10		T46	4
auto[ReadAddrCrossIntoMailbox]	306	1			T46	2		T49	1		T69	4
auto[ReadAddrCrossOutOfMailbox]	344	1			T46	5		T49	1		T69	3
auto[ReadAddrCrossAllMailbox]	281	1			T46	3		T49	2		T69	2
auto[ReadAddrOutsideMailbox]	3699	1			T15	4		T24	2		T40	2

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2494

1

T15

2

T24

1

T40

1

auto[1]

2531

1

T15

2

T24

1

T40

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	811	1			T15	2		T53	2		T58	2
read_ops[0x0b]	834	1			T15	2		T101	4		T46	5
read_ops[0x3b]	790	1			T24	2		T61	2		T82	4
read_ops[0x6b]	816	1			T40	2		T61	4		T101	2
read_ops[0xbb]	889	1			T53	6		T82	2		T60	2
read_ops[0xeb]	885	1			T101	2		T83	2		T46	5

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	24	1			T58	1		T101	1		T69	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	27	1			T58	1		T101	1		T49	2
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	24	1			T259	1		T108	1		T306	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	19	1			T64	1		T37	1		T67	2
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	26	1			T179	1		T231	1		T307	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	28	1			T69	1		T37	2		T178	2
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	25	1			T108	1		T231	1		T307	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	22	1			T46	2		T37	2		T109	2
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	302	1			T15	1		T53	1		T61	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	314	1			T15	1		T53	1		T61	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	37	1			T101	2		T46	1		T37	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	32	1			T101	2		T69	2		T64	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	25	1			T64	1		T109	1		T179	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	24	1			T69	1		T67	1		T108	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	30	1			T69	1		T71	1		T52	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	33	1			T67	1		T108	1		T109	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	18	1			T49	1		T64	1		T260	2
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	22	1			T260	2		T71	1		T37	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	307	1			T15	1		T46	2		T49	3
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	306	1			T15	1		T46	2		T212	4
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	30	1			T64	1		T109	3		T178	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	41	1			T36	1		T71	1		T67	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	21	1			T108	1		T231	2		T220	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	27	1			T64	1		T52	1		T37	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	22	1			T248	1		T52	1		T179	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	33	1			T46	2		T248	1		T67	2
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	17	1			T248	1		T67	1		T45	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	32	1			T248	1		T52	1		T67	2
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	302	1			T24	1		T61	1		T82	2
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	265	1			T24	1		T61	1		T82	2
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	29	1			T101	1		T46	1		T120	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	34	1			T101	1		T46	2		T120	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	28	1			T46	1		T69	1		T109	4
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	23	1			T37	2		T109	2		T178	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	35	1			T46	2		T260	2		T108	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	39	1			T46	1		T64	1		T260	2
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	27	1			T36	1		T109	1		T214	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	28	1			T234	1		T180	1		T287	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	272	1			T40	1		T61	2		T49	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	301	1			T40	1		T61	2		T46	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	34	1			T36	1		T52	2		T108	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	36	1			T64	1		T109	1		T308	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	29	1			T69	1		T52	2		T67	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	28	1			T49	1		T108	2		T179	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	28	1			T52	1		T234	1		T68	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	21	1			T49	1		T67	1		T108	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	23	1			T46	1		T64	1		T68	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	22	1			T49	1		T64	1		T179	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	356	1			T53	3		T82	1		T60	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	312	1			T53	3		T82	1		T60	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	31	1			T101	1		T260	1		T109	2
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	40	1			T101	1		T260	1		T38	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	32	1			T69	1		T273	1		T36	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	26	1			T46	1		T273	1		T37	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	23	1			T36	1		T67	2		T109	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	26	1			T69	1		T37	1		T179	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	23	1			T69	1		T273	1		T36	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	22	1			T69	1		T64	1		T273	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	314	1			T83	1		T46	2		T49	6
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	348	1			T83	1		T46	2		T258	1