Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	5122	1			T40	10		T72	6		T76	2
values[1]	4063	1			T18	2		T101	20		T83	2
values[2]	3790	1			T58	2		T74	12		T69	83
values[3]	4894	1			T53	16		T82	14		T46	40
values[4]	4295	1			T15	12		T24	20		T65	2
values[5]	4165	1			T62	2		T46	20		T49	73
values[6]	4746	1			T11	6		T103	10		T46	20
values[7]	4200	1			T20	2		T63	2		T98	12

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	5048	1			T15	12		T72	6		T46	20
values[1]	4491	1			T46	20		T49	73		T212	8
values[2]	3899	1			T62	2		T58	2		T46	40
values[3]	4273	1			T24	20		T103	10		T63	2
values[4]	4250	1			T11	6		T18	2		T60	20
values[5]	4750	1			T73	10		T216	14		T255	4
values[6]	4188	1			T61	26		T101	20		T83	2
values[7]	4376	1			T20	2		T65	2		T40	10

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

34372

1

T11

6

T15

12

T18

2

auto[1]

903

1

T60

4

T46

7

T49

3

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	649	1			T72	6		T96	106		T36	40
auto[0]	values[0]	values[1]	401	1			T36	20		T67	32		T68	20
auto[0]	values[0]	values[2]	347	1			T64	18		T68	25		T309	8
auto[0]	values[0]	values[3]	978	1			T76	2		T69	108		T52	88
auto[0]	values[0]	values[4]	1132	1			T77	10		T66	64		T69	153
auto[0]	values[0]	values[5]	472	1			T216	14		T69	67		T67	123
auto[0]	values[0]	values[6]	458	1			T78	8		T234	20		T108	23
auto[0]	values[0]	values[7]	571	1			T40	10		T266	12		T179	20
auto[0]	values[1]	values[0]	611	1			T273	6		T264	4		T52	20
auto[0]	values[1]	values[1]	439	1			T46	19		T64	18		T108	27
auto[0]	values[1]	values[2]	460	1			T227	12		T225	76		T44	18
auto[0]	values[1]	values[3]	504	1			T69	20		T36	23		T282	2
auto[0]	values[1]	values[4]	398	1			T18	2		T179	32		T231	24
auto[0]	values[1]	values[5]	527	1			T73	10		T69	20		T281	2
auto[0]	values[1]	values[6]	598	1			T101	20		T83	2		T36	20
auto[0]	values[1]	values[7]	424	1			T52	64		T178	19		T231	27
auto[0]	values[2]	values[0]	499	1			T64	20		T208	2		T67	27
auto[0]	values[2]	values[1]	719	1			T224	14		T109	88		T178	53
auto[0]	values[2]	values[2]	362	1			T58	2		T74	12		T68	20
auto[0]	values[2]	values[3]	251	1			T67	20		T109	18		T178	20
auto[0]	values[2]	values[4]	351	1			T68	20		T108	20		T179	39
auto[0]	values[2]	values[5]	472	1			T268	2		T108	19		T310	2
auto[0]	values[2]	values[6]	383	1			T67	20		T311	20		T230	21
auto[0]	values[2]	values[7]	634	1			T69	81		T64	20		T109	38
auto[0]	values[3]	values[0]	665	1			T312	29		T225	86		T220	20
auto[0]	values[3]	values[1]	617	1			T212	8		T36	20		T267	2
auto[0]	values[3]	values[2]	559	1			T52	20		T108	32		T290	16
auto[0]	values[3]	values[3]	601	1			T82	14		T52	21		T225	25
auto[0]	values[3]	values[4]	490	1			T68	19		T271	12		T109	32
auto[0]	values[3]	values[5]	787	1			T37	20		T178	27		T312	20
auto[0]	values[3]	values[6]	489	1			T71	20		T68	18		T221	10
auto[0]	values[3]	values[7]	565	1			T53	16		T46	38		T49	69
auto[0]	values[4]	values[0]	711	1			T15	12		T36	21		T231	20
auto[0]	values[4]	values[1]	368	1			T36	25		T52	51		T307	8
auto[0]	values[4]	values[2]	452	1			T69	94		T52	68		T37	20
auto[0]	values[4]	values[3]	451	1			T24	20		T36	20		T313	4
auto[0]	values[4]	values[4]	296	1			T60	16		T178	20		T314	17
auto[0]	values[4]	values[5]	550	1			T255	4		T69	20		T250	10
auto[0]	values[4]	values[6]	760	1			T61	26		T52	20		T108	88
auto[0]	values[4]	values[7]	593	1			T65	2		T46	39		T36	41
auto[0]	values[5]	values[0]	325	1			T315	6		T316	30		T232	23
auto[0]	values[5]	values[1]	565	1			T49	72		T70	16		T37	39
auto[0]	values[5]	values[2]	602	1			T62	2		T46	17		T52	27
auto[0]	values[5]	values[3]	509	1			T50	20		T69	20		T234	20
auto[0]	values[5]	values[4]	639	1			T193	8		T69	66		T71	19
auto[0]	values[5]	values[5]	614	1			T67	25		T243	16		T108	20
auto[0]	values[5]	values[6]	370	1			T71	20		T67	20		T214	18
auto[0]	values[5]	values[7]	436	1			T120	14		T36	31		T317	20
auto[0]	values[6]	values[0]	600	1			T225	28		T222	20		T291	22
auto[0]	values[6]	values[1]	792	1			T69	128		T178	20		T231	69
auto[0]	values[6]	values[2]	501	1			T46	20		T49	50		T262	2
auto[0]	values[6]	values[3]	366	1			T103	10		T272	10		T259	40
auto[0]	values[6]	values[4]	438	1			T11	6		T49	29		T64	40
auto[0]	values[6]	values[5]	697	1			T64	16		T248	6		T38	18
auto[0]	values[6]	values[6]	604	1			T64	18		T304	6		T108	37
auto[0]	values[6]	values[7]	629	1			T235	10		T179	70		T214	25
auto[0]	values[7]	values[0]	861	1			T46	20		T69	110		T278	73
auto[0]	values[7]	values[1]	457	1			T108	25		T109	29		T225	20
auto[0]	values[7]	values[2]	518	1			T49	20		T238	2		T277	28
auto[0]	values[7]	values[3]	503	1			T63	2		T49	45		T318	8
auto[0]	values[7]	values[4]	400	1			T319	6		T246	22		T274	60
auto[0]	values[7]	values[5]	518	1			T258	8		T231	31		T217	78
auto[0]	values[7]	values[6]	422	1			T50	20		T260	12		T68	18
auto[0]	values[7]	values[7]	412	1			T20	2		T98	12		T295	22
auto[1]	values[0]	values[0]	10	1			T244	1		T214	1		T166	1
auto[1]	values[0]	values[1]	11	1			T36	1		T67	2		T178	1
auto[1]	values[0]	values[2]	11	1			T64	2		T68	4		T220	1
auto[1]	values[0]	values[3]	35	1			T69	2		T52	2		T45	5
auto[1]	values[0]	values[4]	20	1			T66	1		T69	2		T64	3
auto[1]	values[0]	values[5]	14	1			T67	3		T162	1		T230	3
auto[1]	values[0]	values[6]	4	1			T293	2		T320	1		T87	1
auto[1]	values[0]	values[7]	9	1			T256	1		T321	2		T322	6
auto[1]	values[1]	values[0]	17	1			T178	6		T293	2		T323	1
auto[1]	values[1]	values[1]	20	1			T46	1		T64	2		T109	1
auto[1]	values[1]	values[2]	9	1			T44	2		T283	1		T294	2
auto[1]	values[1]	values[3]	11	1			T108	1		T109	1		T324	2
auto[1]	values[1]	values[4]	11	1			T324	4		T320	2		T323	2
auto[1]	values[1]	values[5]	16	1			T45	1		T325	2		T326	2
auto[1]	values[1]	values[6]	10	1			T327	2		T166	5		T328	1
auto[1]	values[1]	values[7]	8	1			T178	1		T231	3		T214	2
auto[1]	values[2]	values[0]	15	1			T67	3		T214	2		T278	2
auto[1]	values[2]	values[1]	16	1			T178	2		T278	3		T220	1
auto[1]	values[2]	values[2]	14	1			T251	1		T162	6		T296	1
auto[1]	values[2]	values[3]	13	1			T109	2		T44	5		T329	3
auto[1]	values[2]	values[4]	4	1			T330	1		T331	2		T332	1
auto[1]	values[2]	values[5]	16	1			T108	1		T179	2		T278	2
auto[1]	values[2]	values[6]	12	1			T324	3		T333	1		T334	1
auto[1]	values[2]	values[7]	29	1			T69	2		T109	2		T305	8
auto[1]	values[3]	values[0]	20	1			T312	1		T217	1		T335	4
auto[1]	values[3]	values[1]	15	1			T109	2		T298	2		T328	4
auto[1]	values[3]	values[2]	8	1			T179	2		T293	1		T297	1
auto[1]	values[3]	values[3]	15	1			T52	2		T225	1		T336	4
auto[1]	values[3]	values[4]	19	1			T68	1		T109	5		T247	4
auto[1]	values[3]	values[5]	18	1			T214	2		T247	1		T242	2
auto[1]	values[3]	values[6]	11	1			T71	2		T68	2		T316	2
auto[1]	values[3]	values[7]	15	1			T46	2		T49	2		T274	2
auto[1]	values[4]	values[0]	20	1			T337	6		T298	4		T338	2
auto[1]	values[4]	values[1]	16	1			T52	1		T263	2		T322	7
auto[1]	values[4]	values[2]	8	1			T52	4		T229	1		T297	1
auto[1]	values[4]	values[3]	4	1			T283	1		T297	1		T339	1
auto[1]	values[4]	values[4]	18	1			T60	4		T178	1		T314	3
auto[1]	values[4]	values[5]	14	1			T108	2		T225	1		T340	2
auto[1]	values[4]	values[6]	29	1			T231	5		T247	2		T220	2
auto[1]	values[4]	values[7]	5	1			T46	1		T36	1		T37	2
auto[1]	values[5]	values[0]	6	1			T316	1		T341	1		T342	4
auto[1]	values[5]	values[1]	20	1			T49	1		T70	4		T37	1
auto[1]	values[5]	values[2]	24	1			T46	3		T231	1		T263	2
auto[1]	values[5]	values[3]	11	1			T296	1		T223	2		T343	2
auto[1]	values[5]	values[4]	10	1			T71	3		T245	1		T323	2
auto[1]	values[5]	values[5]	6	1			T179	1		T344	5		-	-
auto[1]	values[5]	values[6]	10	1			T214	2		T329	3		T263	1
auto[1]	values[5]	values[7]	18	1			T283	1		T335	2		T345	1
auto[1]	values[6]	values[0]	18	1			T291	4		T223	3		T346	3
auto[1]	values[6]	values[1]	20	1			T231	1		T278	2		T252	1
auto[1]	values[6]	values[2]	14	1			T68	1		T328	4		T347	3
auto[1]	values[6]	values[3]	13	1			T259	1		T109	1		T162	4
auto[1]	values[6]	values[4]	8	1			T334	2		T348	3		T349	1
auto[1]	values[6]	values[5]	21	1			T64	4		T38	2		T247	2
auto[1]	values[6]	values[6]	17	1			T64	2		T108	1		T251	1
auto[1]	values[6]	values[7]	8	1			T179	1		T293	1		T350	1
auto[1]	values[7]	values[0]	21	1			T278	3		T217	2		T251	4
auto[1]	values[7]	values[1]	15	1			T109	2		T299	3		T301	2
auto[1]	values[7]	values[2]	10	1			T217	2		T293	1		T230	1
auto[1]	values[7]	values[3]	8	1			T220	2		T351	1		T352	1
auto[1]	values[7]	values[4]	16	1			T274	1		T329	2		T335	2
auto[1]	values[7]	values[5]	8	1			T231	1		T217	1		T283	2
auto[1]	values[7]	values[6]	11	1			T68	2		T109	1		T179	2
auto[1]	values[7]	values[7]	20	1			T109	3		T252	2		T353	2