Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	842	1			T34	11		T37	14		T38	7
all_values[1]	842	1			T34	11		T37	14		T38	7
all_values[2]	842	1			T34	11		T37	14		T38	7
all_values[3]	842	1			T34	11		T37	14		T38	7
all_values[4]	842	1			T34	11		T37	14		T38	7
all_values[5]	842	1			T34	11		T37	14		T38	7
all_values[6]	842	1			T34	11		T37	14		T38	7
all_values[7]	842	1			T34	11		T37	14		T38	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3543

1

T34

46

T37

67

T38

31

auto[1]

3193

1

T34

42

T37

45

T38

25

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2693

1

T34

45

T37

57

T38

20

auto[1]

4043

1

T34

43

T37

55

T38

36

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3829

1

T34

55

T37

66

T38

31

auto[1]

2907

1

T34

33

T37

46

T38

25

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	144	1			T34	2		T37	2		T38	3
all_values[0]	auto[0]	auto[0]	auto[1]	84	1			T34	1		T39	2		T186	2
all_values[0]	auto[0]	auto[1]	auto[0]	152	1			T37	6		T38	1		T39	1
all_values[0]	auto[0]	auto[1]	auto[1]	82	1			T34	1		T39	1		T178	1
all_values[0]	auto[1]	auto[0]	auto[1]	206	1			T34	4		T37	6		T38	3
all_values[0]	auto[1]	auto[1]	auto[1]	174	1			T34	3		T39	1		T178	5
all_values[1]	auto[0]	auto[0]	auto[0]	165	1			T34	3		T37	7		T39	1
all_values[1]	auto[0]	auto[0]	auto[1]	71	1			T34	1		T37	1		T38	1
all_values[1]	auto[0]	auto[1]	auto[0]	152	1			T34	3		T37	3		T38	1
all_values[1]	auto[0]	auto[1]	auto[1]	77	1			T38	1		T39	3		T179	4
all_values[1]	auto[1]	auto[0]	auto[1]	195	1			T34	3		T37	3		T38	2
all_values[1]	auto[1]	auto[1]	auto[1]	182	1			T34	1		T38	2		T39	4
all_values[2]	auto[0]	auto[0]	auto[0]	172	1			T34	2		T37	1		T186	1
all_values[2]	auto[0]	auto[0]	auto[1]	71	1			T37	2		T38	1		T39	1
all_values[2]	auto[0]	auto[1]	auto[0]	133	1			T34	4		T37	3		T39	3
all_values[2]	auto[0]	auto[1]	auto[1]	92	1			T34	1		T37	1		T39	1
all_values[2]	auto[1]	auto[0]	auto[1]	181	1			T34	1		T37	3		T38	4
all_values[2]	auto[1]	auto[1]	auto[1]	193	1			T34	3		T37	4		T38	2
all_values[3]	auto[0]	auto[0]	auto[0]	157	1			T34	2		T37	4		T39	3
all_values[3]	auto[0]	auto[0]	auto[1]	74	1			T178	1		T44	2		T92	2
all_values[3]	auto[0]	auto[1]	auto[0]	136	1			T34	4		T37	3		T38	3
all_values[3]	auto[0]	auto[1]	auto[1]	95	1			T34	1		T37	1		T38	2
all_values[3]	auto[1]	auto[0]	auto[1]	202	1			T34	2		T37	4		T38	1
all_values[3]	auto[1]	auto[1]	auto[1]	178	1			T34	2		T37	2		T38	1
all_values[4]	auto[0]	auto[0]	auto[0]	167	1			T34	4		T37	1		T38	3
all_values[4]	auto[0]	auto[0]	auto[1]	91	1			T37	1		T39	2		T186	1
all_values[4]	auto[0]	auto[1]	auto[0]	157	1			T34	4		T37	1		T178	1
all_values[4]	auto[0]	auto[1]	auto[1]	87	1			T34	1		T37	1		T38	2
all_values[4]	auto[1]	auto[0]	auto[1]	198	1			T37	9		T38	2		T186	1
all_values[4]	auto[1]	auto[1]	auto[1]	142	1			T34	2		T37	1		T39	4
all_values[5]	auto[0]	auto[0]	auto[0]	252	1			T34	7		T37	4		T38	2
all_values[5]	auto[0]	auto[1]	auto[0]	234	1			T37	4		T38	2		T39	2
all_values[5]	auto[1]	auto[0]	auto[1]	183	1			T34	4		T37	4		T38	2
all_values[5]	auto[1]	auto[1]	auto[1]	173	1			T37	2		T38	1		T39	2
all_values[6]	auto[0]	auto[0]	auto[0]	203	1			T34	2		T37	6		T39	2
all_values[6]	auto[0]	auto[0]	auto[1]	75	1			T34	1		T39	3		T178	1
all_values[6]	auto[0]	auto[1]	auto[0]	149	1			T34	3		T37	4		T38	1
all_values[6]	auto[0]	auto[1]	auto[1]	64	1			T34	1		T38	3		T178	1
all_values[6]	auto[1]	auto[0]	auto[1]	193	1			T34	2		T37	1		T38	2
all_values[6]	auto[1]	auto[1]	auto[1]	158	1			T34	2		T37	3		T38	1
all_values[7]	auto[0]	auto[0]	auto[0]	179	1			T34	3		T37	4		T38	4
all_values[7]	auto[0]	auto[0]	auto[1]	84	1			T37	1		T39	2		T178	4
all_values[7]	auto[0]	auto[1]	auto[0]	141	1			T34	2		T37	4		T39	2
all_values[7]	auto[0]	auto[1]	auto[1]	89	1			T34	2		T37	1		T38	1
all_values[7]	auto[1]	auto[0]	auto[1]	196	1			T34	2		T37	3		T38	1
all_values[7]	auto[1]	auto[1]	auto[1]	153	1			T34	2		T37	1		T38	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal