Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1794

1

T4

2

T13

3

T17

16

auto[1]

1710

1

T4

4

T13

5

T17

16

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1940

1

T26

6

T42

16

T43

16

auto[1]

1564

1

T4

6

T13

8

T17

32

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2767

1

T4

6

T13

8

T17

32

auto[1]

737

1

T26

1

T42

5

T43

3

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	653	1			T4	2		T13	1		T17	6
valid[1]	722	1			T4	2		T13	3		T17	9
valid[2]	685	1			T4	1		T13	1		T17	4
valid[3]	727	1			T4	1		T13	1		T17	8
valid[4]	717	1			T13	2		T17	5		T26	1

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	117	1			T42	1		T43	1		T48	1
auto[0]	auto[0]	valid[0]	auto[1]	140	1			T4	1		T17	2		T29	2
auto[0]	auto[0]	valid[1]	auto[0]	118	1			T26	1		T43	1		T48	1
auto[0]	auto[0]	valid[1]	auto[1]	173	1			T13	1		T17	6		T28	1
auto[0]	auto[0]	valid[2]	auto[0]	113	1			T43	1		T48	1		T36	2
auto[0]	auto[0]	valid[2]	auto[1]	163	1			T4	1		T13	1		T17	4
auto[0]	auto[0]	valid[3]	auto[0]	135	1			T26	1		T42	2		T43	2
auto[0]	auto[0]	valid[3]	auto[1]	157	1			T17	3		T29	1		T31	1
auto[0]	auto[0]	valid[4]	auto[0]	108	1			T26	1		T42	2		T43	1
auto[0]	auto[0]	valid[4]	auto[1]	178	1			T13	1		T17	1		T29	2
auto[0]	auto[1]	valid[0]	auto[0]	103	1			T42	1		T43	3		T48	3
auto[0]	auto[1]	valid[0]	auto[1]	144	1			T4	1		T13	1		T17	4
auto[0]	auto[1]	valid[1]	auto[0]	137	1			T26	2		T48	1		T114	2
auto[0]	auto[1]	valid[1]	auto[1]	150	1			T4	2		T13	2		T17	3
auto[0]	auto[1]	valid[2]	auto[0]	120	1			T42	2		T43	1		T48	2
auto[0]	auto[1]	valid[2]	auto[1]	140	1			T26	1		T81	1		T375	1
auto[0]	auto[1]	valid[3]	auto[0]	120	1			T42	2		T43	2		T100	1
auto[0]	auto[1]	valid[3]	auto[1]	157	1			T4	1		T13	1		T17	5
auto[0]	auto[1]	valid[4]	auto[0]	132	1			T42	1		T43	1		T48	1
auto[0]	auto[1]	valid[4]	auto[1]	162	1			T13	1		T17	4		T29	2
auto[1]	auto[0]	valid[0]	auto[0]	83	1			T42	1		T43	1		T48	1
auto[1]	auto[0]	valid[1]	auto[0]	78	1			T43	1		T100	1		T114	1
auto[1]	auto[0]	valid[2]	auto[0]	75	1			T26	1		T48	1		T100	1
auto[1]	auto[0]	valid[3]	auto[0]	85	1			T42	1		T36	1		T366	1
auto[1]	auto[0]	valid[4]	auto[0]	71	1			T100	2		T36	1		T71	1
auto[1]	auto[1]	valid[0]	auto[0]	66	1			T42	1		T100	4		T36	1
auto[1]	auto[1]	valid[1]	auto[0]	66	1			T100	1		T114	2		T36	1
auto[1]	auto[1]	valid[2]	auto[0]	74	1			T48	2		T97	1		T259	1
auto[1]	auto[1]	valid[3]	auto[0]	73	1			T43	1		T48	1		T114	1
auto[1]	auto[1]	valid[4]	auto[0]	66	1			T42	2		T100	2		T114	2

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal