Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

47540

1

T5

4

T14

2

T26

119

auto[1]

16491

1

T4

6

T13

8

T17

484

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

46635

1

T4

6

T5

2

T13

8

auto[1]

17396

1

T5

2

T14

1

T26

42

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	33000	1			T4	6		T5	3		T13	8
others[1]	5433	1			T14	1		T17	35		T26	10
others[2]	5303	1			T17	44		T26	11		T29	16
others[3]	6155	1			T5	1		T17	55		T26	10
interest[1]	3519	1			T17	23		T26	4		T29	12
interest[4]	21591	1			T4	6		T5	3		T13	8
interest[64]	10621	1			T17	89		T26	23		T29	28

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	15459	1			T5	2		T26	42		T32	1
auto[0]	auto[0]	others[1]	2609	1			T14	1		T26	5		T42	28
auto[0]	auto[0]	others[2]	2474	1			T26	9		T42	20		T43	32
auto[0]	auto[0]	others[3]	2902	1			T26	5		T42	20		T43	32
auto[0]	auto[0]	interest[1]	1651	1			T26	2		T42	15		T43	25
auto[0]	auto[0]	interest[4]	10106	1			T5	2		T26	26		T32	1
auto[0]	auto[0]	interest[64]	5049	1			T26	14		T47	1		T42	41
auto[0]	auto[1]	others[0]	8611	1			T4	6		T13	8		T17	238
auto[0]	auto[1]	others[1]	1405	1			T17	35		T29	21		T81	9
auto[0]	auto[1]	others[2]	1365	1			T17	44		T29	16		T81	7
auto[0]	auto[1]	others[3]	1546	1			T17	55		T26	1		T29	8
auto[0]	auto[1]	interest[1]	884	1			T17	23		T29	12		T81	5
auto[0]	auto[1]	interest[4]	5702	1			T4	6		T13	8		T17	158
auto[0]	auto[1]	interest[64]	2680	1			T17	89		T26	4		T29	28
auto[1]	auto[0]	others[0]	8930	1			T5	1		T14	1		T26	24
auto[1]	auto[0]	others[1]	1419	1			T26	5		T42	7		T43	12
auto[1]	auto[0]	others[2]	1464	1			T26	2		T42	11		T43	14
auto[1]	auto[0]	others[3]	1707	1			T5	1		T26	4		T42	10
auto[1]	auto[0]	interest[1]	984	1			T26	2		T42	7		T43	8
auto[1]	auto[0]	interest[4]	5783	1			T5	1		T14	1		T26	18
auto[1]	auto[0]	interest[64]	2892	1			T26	5		T47	1		T42	21

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal