Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}
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Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 12 0 12 100.00
Crosses 32 0 32 100.00


Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 8 0 8 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_cg_cc 32 0 32 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 8 0 8 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 2646750 1 T1 1 T2 1 T3 1
all_values[1] 2646750 1 T1 1 T2 1 T3 1
all_values[2] 2646750 1 T1 1 T2 1 T3 1
all_values[3] 2646750 1 T1 1 T2 1 T3 1
all_values[4] 2646750 1 T1 1 T2 1 T3 1
all_values[5] 2646750 1 T1 1 T2 1 T3 1
all_values[6] 2646750 1 T1 1 T2 1 T3 1
all_values[7] 2646750 1 T1 1 T2 1 T3 1



Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 20588123 1 T1 8 T2 8 T3 8
auto[1] 585877 1 T20 30 T22 50 T89 45



Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 21146457 1 T1 8 T2 8 T3 8
auto[1] 27543 1 T20 30 T22 157 T47 209



Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 32 0 32 100.00


Automatically Generated Cross Bins for intr_cg_cc

Bins
cp_intrcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] 2524125 1 T1 1 T2 1 T3 1
all_values[0] auto[0] auto[1] 12439 1 T20 1 T22 57 T47 132
all_values[0] auto[1] auto[0] 109383 1 T20 3 T22 6 T89 2
all_values[0] auto[1] auto[1] 803 1 T20 3 T22 3 T89 4
all_values[1] auto[0] auto[0] 2612861 1 T1 1 T2 1 T3 1
all_values[1] auto[0] auto[1] 8593 1 T20 1 T22 35 T47 77
all_values[1] auto[1] auto[0] 25010 1 T20 1 T22 1 T89 3
all_values[1] auto[1] auto[1] 286 1 T22 5 T89 1 T32 8
all_values[2] auto[0] auto[0] 2533961 1 T1 1 T2 1 T3 1
all_values[2] auto[0] auto[1] 3024 1 T20 2 T22 37 T48 14
all_values[2] auto[1] auto[0] 109449 1 T20 1 T22 1 T89 2
all_values[2] auto[1] auto[1] 316 1 T20 1 T22 4 T89 2
all_values[3] auto[0] auto[0] 2536366 1 T1 1 T2 1 T3 1
all_values[3] auto[0] auto[1] 201 1 T20 1 T22 2 T89 3
all_values[3] auto[1] auto[0] 109988 1 T20 3 T22 1 T89 3
all_values[3] auto[1] auto[1] 195 1 T20 3 T22 1 T89 2
all_values[4] auto[0] auto[0] 2641270 1 T1 1 T2 1 T3 1
all_values[4] auto[0] auto[1] 231 1 T20 3 T22 3 T89 3
all_values[4] auto[1] auto[0] 5069 1 T20 1 T22 3 T89 3
all_values[4] auto[1] auto[1] 180 1 T20 4 T22 4 T34 1
all_values[5] auto[0] auto[0] 2534172 1 T1 1 T2 1 T3 1
all_values[5] auto[0] auto[1] 210 1 T22 2 T89 3 T32 9
all_values[5] auto[1] auto[0] 112175 1 T20 3 T22 8 T89 5
all_values[5] auto[1] auto[1] 193 1 T20 2 T89 3 T32 5
all_values[6] auto[0] auto[0] 2536763 1 T1 1 T2 1 T3 1
all_values[6] auto[0] auto[1] 216 1 T20 4 T22 1 T32 7
all_values[6] auto[1] auto[0] 109546 1 T20 1 T22 3 T89 3
all_values[6] auto[1] auto[1] 225 1 T22 2 T89 4 T32 3
all_values[7] auto[0] auto[0] 2643452 1 T1 1 T2 1 T3 1
all_values[7] auto[0] auto[1] 239 1 T20 2 T89 1 T32 4
all_values[7] auto[1] auto[0] 2867 1 T20 1 T22 7 T89 2
all_values[7] auto[1] auto[1] 192 1 T20 3 T22 1 T89 6

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