Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.74 98.65 96.80 99.01 89.36 98.51 95.57 99.26


Total tests in report: 1131
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
66.12 66.12 92.17 92.17 81.88 81.88 81.23 81.23 33.33 33.33 89.84 89.84 72.48 72.48 11.93 11.93 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_pass_cmd_filtering.2424048480
78.88 12.75 96.09 3.92 91.66 9.78 86.07 4.84 68.89 35.56 95.08 5.23 82.02 9.54 32.33 20.40 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_stress_all.2469420963
82.94 4.07 96.36 0.27 92.15 0.49 86.07 0.00 82.22 13.33 95.49 0.41 82.02 0.00 46.29 13.96 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_flash_and_tpm.1555504181
86.17 3.22 97.94 1.58 93.97 1.82 88.64 2.57 88.89 6.67 97.44 1.96 85.20 3.18 51.09 4.80 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_tpm_all.908834159
87.92 1.75 97.99 0.06 94.08 0.12 88.64 0.00 91.11 2.22 97.51 0.07 85.34 0.14 60.74 9.65 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_flash_mode_ignore_cmds.957494655
89.49 1.58 97.99 0.00 94.22 0.14 89.43 0.79 91.11 0.00 97.55 0.03 93.78 8.44 62.38 1.63 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.3003685755
90.60 1.11 98.02 0.03 94.25 0.03 89.43 0.00 93.33 2.22 97.56 0.02 93.78 0.00 67.82 5.45 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_stress_all.4207525507
91.47 0.87 98.49 0.47 95.45 1.20 92.29 2.87 93.33 0.00 98.28 0.72 94.33 0.55 68.12 0.30 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_read_buffer_direct.2630706598
92.30 0.83 98.54 0.06 95.54 0.09 92.29 0.00 93.33 0.00 98.44 0.15 94.33 0.00 73.61 5.50 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_flash_and_tpm_min_idle.1720410840
92.98 0.68 98.56 0.02 95.54 0.00 97.04 4.74 93.33 0.00 98.44 0.00 94.33 0.00 73.61 0.00 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_ram_cfg.852811863
93.53 0.55 98.56 0.00 95.54 0.00 97.04 0.00 93.33 0.00 98.44 0.00 94.33 0.00 77.48 3.86 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_flash_and_tpm_min_idle.825159560
94.07 0.54 98.56 0.00 95.56 0.01 97.04 0.00 93.33 0.00 98.44 0.00 94.33 0.00 81.24 3.76 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_flash_and_tpm.2494290214
94.42 0.35 98.56 0.00 95.56 0.00 97.04 0.00 93.33 0.00 98.44 0.00 94.47 0.14 83.56 2.33 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_stress_all.3494545212
94.74 0.32 98.57 0.01 95.59 0.04 98.81 1.78 93.33 0.00 98.46 0.02 94.61 0.14 83.81 0.25 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_sec_cm.3674994973
95.03 0.29 98.57 0.00 95.59 0.00 98.81 0.00 93.33 0.00 98.46 0.00 94.61 0.00 85.84 2.03 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_stress_all.2503419417
95.26 0.23 98.57 0.00 95.59 0.00 98.81 0.00 93.33 0.00 98.46 0.00 94.61 0.00 87.48 1.63 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_flash_and_tpm_min_idle.3542357044
95.48 0.22 98.57 0.00 95.59 0.00 98.81 0.00 93.33 0.00 98.46 0.00 94.61 0.00 89.01 1.53 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_flash_and_tpm.475330965
95.67 0.19 98.57 0.00 95.59 0.00 98.81 0.00 93.33 0.00 98.46 0.00 94.61 0.00 90.35 1.34 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_flash_mode_ignore_cmds.3550475851
95.83 0.16 98.58 0.01 95.70 0.10 98.81 0.00 93.33 0.00 98.47 0.02 94.61 0.00 91.34 0.99 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_tl_intg_err.954574625
95.98 0.14 98.58 0.00 95.70 0.00 98.81 0.00 93.33 0.00 98.47 0.00 94.61 0.00 92.33 0.99 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_flash_and_tpm.2024548996
96.11 0.13 98.58 0.00 96.36 0.67 98.81 0.00 93.33 0.00 98.47 0.00 94.61 0.00 92.57 0.25 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/8.spi_device_tl_errors.2143226445
96.23 0.12 98.58 0.00 96.39 0.03 98.81 0.00 93.33 0.00 98.47 0.00 95.44 0.83 92.57 0.00 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_hw_reset.3143276192
96.34 0.11 98.58 0.00 96.39 0.00 98.81 0.00 93.33 0.00 98.47 0.00 95.44 0.00 93.37 0.79 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_flash_all.4175566715
96.45 0.10 98.58 0.00 96.39 0.00 98.81 0.00 93.33 0.00 98.47 0.00 95.57 0.14 93.96 0.59 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_stress_all.1232878025
96.54 0.09 98.58 0.00 96.39 0.00 98.81 0.00 93.33 0.00 98.47 0.00 95.57 0.00 94.60 0.64 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_tpm_all.2739884739
96.61 0.07 98.58 0.00 96.39 0.00 98.81 0.00 93.33 0.00 98.47 0.00 95.57 0.00 95.10 0.50 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_stress_all.1039155406
96.68 0.07 98.61 0.03 96.45 0.06 98.81 0.00 93.33 0.00 98.47 0.00 95.57 0.00 95.50 0.40 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_intercept.77707460
96.74 0.06 98.61 0.00 96.45 0.00 98.81 0.00 93.33 0.00 98.47 0.00 95.57 0.00 95.94 0.45 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_stress_all.3205965870
96.80 0.06 98.61 0.00 96.45 0.00 98.81 0.00 93.33 0.00 98.47 0.00 95.57 0.00 96.34 0.40 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_flash_and_tpm_min_idle.3068280050
96.85 0.05 98.61 0.00 96.45 0.00 98.81 0.00 93.33 0.00 98.47 0.00 95.57 0.00 96.68 0.35 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_flash_all.2040464715
96.89 0.04 98.64 0.03 96.49 0.04 99.01 0.20 93.33 0.00 98.47 0.00 95.57 0.00 96.68 0.00 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_alert_test.3698775696
96.92 0.04 98.64 0.00 96.49 0.00 99.01 0.00 93.33 0.00 98.47 0.00 95.57 0.00 96.93 0.25 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_flash_mode.217555999
96.96 0.04 98.64 0.00 96.49 0.00 99.01 0.00 93.33 0.00 98.47 0.00 95.57 0.00 97.18 0.25 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_flash_and_tpm.3957185908
96.99 0.04 98.64 0.00 96.49 0.00 99.01 0.00 93.33 0.00 98.47 0.00 95.57 0.00 97.43 0.25 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_flash_mode_ignore_cmds.796680145
97.03 0.03 98.64 0.00 96.67 0.18 99.01 0.00 93.33 0.00 98.47 0.00 95.57 0.00 97.48 0.05 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_tl_errors.3477312337
97.05 0.03 98.64 0.00 96.67 0.00 99.01 0.00 93.33 0.00 98.47 0.00 95.57 0.00 97.67 0.20 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_stress_all.4145278550
97.08 0.03 98.64 0.00 96.67 0.00 99.01 0.00 93.33 0.00 98.47 0.00 95.57 0.00 97.87 0.20 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_flash_and_tpm_min_idle.2362058437
97.11 0.03 98.64 0.00 96.67 0.00 99.01 0.00 93.33 0.00 98.47 0.00 95.57 0.00 98.07 0.20 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_flash_and_tpm.3489238573
97.13 0.02 98.64 0.00 96.67 0.00 99.01 0.00 93.33 0.00 98.47 0.00 95.57 0.00 98.22 0.15 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_tpm_all.717684105
97.15 0.02 98.64 0.00 96.67 0.00 99.01 0.00 93.33 0.00 98.47 0.00 95.57 0.00 98.37 0.15 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_flash_mode.4193287346
97.17 0.02 98.64 0.00 96.67 0.00 99.01 0.00 93.33 0.00 98.47 0.00 95.57 0.00 98.51 0.15 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_stress_all.1146369865
97.19 0.02 98.64 0.00 96.68 0.01 99.01 0.00 93.33 0.00 98.47 0.00 95.57 0.00 98.61 0.10 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_flash_mode_ignore_cmds.2351399245
97.20 0.01 98.64 0.00 96.68 0.00 99.01 0.00 93.33 0.00 98.47 0.00 95.57 0.00 98.71 0.10 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/13.spi_device_tl_intg_err.2014881632
97.22 0.01 98.64 0.00 96.68 0.00 99.01 0.00 93.33 0.00 98.47 0.00 95.57 0.00 98.81 0.10 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/17.spi_device_tl_intg_err.517288398
97.23 0.01 98.64 0.00 96.68 0.00 99.01 0.00 93.33 0.00 98.47 0.00 95.57 0.00 98.91 0.10 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_flash_all.31519605
97.24 0.01 98.65 0.01 96.73 0.05 99.01 0.00 93.33 0.00 98.49 0.02 95.57 0.00 98.91 0.00 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_pass_cmd_filtering.3139448399
97.25 0.01 98.65 0.00 96.73 0.00 99.01 0.00 93.33 0.00 98.49 0.00 95.57 0.00 98.96 0.05 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_upload.3640423044
97.26 0.01 98.65 0.00 96.73 0.00 99.01 0.00 93.33 0.00 98.49 0.00 95.57 0.00 99.01 0.05 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_flash_all.1257751659
97.26 0.01 98.65 0.00 96.73 0.00 99.01 0.00 93.33 0.00 98.49 0.00 95.57 0.00 99.06 0.05 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_flash_and_tpm.3507433086
97.27 0.01 98.65 0.00 96.73 0.00 99.01 0.00 93.33 0.00 98.49 0.00 95.57 0.00 99.11 0.05 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_flash_mode.929455296
97.28 0.01 98.65 0.00 96.73 0.00 99.01 0.00 93.33 0.00 98.49 0.00 95.57 0.00 99.16 0.05 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_flash_all.3780684542
97.29 0.01 98.65 0.00 96.73 0.00 99.01 0.00 93.33 0.00 98.49 0.00 95.57 0.00 99.21 0.05 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_intercept.2165944996
97.29 0.01 98.65 0.00 96.73 0.00 99.01 0.00 93.33 0.00 98.49 0.00 95.57 0.00 99.26 0.05 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_flash_and_tpm.3996846391
97.30 0.01 98.65 0.00 96.76 0.03 99.01 0.00 93.33 0.00 98.51 0.02 95.57 0.00 99.26 0.00 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_intercept.2441269994
97.30 0.01 98.65 0.00 96.79 0.03 99.01 0.00 93.33 0.00 98.51 0.00 95.57 0.00 99.26 0.00 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/17.spi_device_tl_errors.1258636062
97.30 0.01 98.65 0.00 96.80 0.01 99.01 0.00 93.33 0.00 98.51 0.00 95.57 0.00 99.26 0.00 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_csb_read.726700694

Tests that do not contribute to grading

Name
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_aliasing.2436194261
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_bit_bash.1558814633
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_hw_reset.214319787
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.409463754
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_rw.3380395908
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_intr_test.3022494701
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_mem_partial_access.3461088605
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_mem_walk.1372708365
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.706968562
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_tl_errors.4066831306
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_aliasing.2846508693
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_bit_bash.3681468439
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_hw_reset.3844075460
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_rw.453296475
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_intr_test.3212415482
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_mem_partial_access.1000337276
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_mem_walk.2742629461
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.2350144987
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_tl_errors.2030430715
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_tl_intg_err.3843659310
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.1688394631
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_csr_rw.2376236800
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_intr_test.2063950756
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.2987795115
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_tl_errors.3181342427
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_tl_intg_err.273924211
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.941253256
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_csr_rw.332610584
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_intr_test.3730928649
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.113874499
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_tl_errors.2681117840
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_tl_intg_err.673567471
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.4126889439
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_csr_rw.4233173117
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_intr_test.2888541537
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.2314383149
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_tl_errors.2601736187
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_tl_intg_err.1465415852
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.321025508
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/13.spi_device_csr_rw.1307314906
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/13.spi_device_intr_test.3239045039
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.3216936080
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/13.spi_device_tl_errors.51434220
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.2783065234
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/14.spi_device_csr_rw.1758028951
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/14.spi_device_intr_test.3424338440
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.3578132880
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/14.spi_device_tl_errors.3348669579
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/14.spi_device_tl_intg_err.3056313486
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.1757271119
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/15.spi_device_csr_rw.2739238274
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/15.spi_device_intr_test.2485342241
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.2753469568
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/15.spi_device_tl_errors.4056745457
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/15.spi_device_tl_intg_err.1793876510
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.3872455046
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/16.spi_device_csr_rw.3904520838
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/16.spi_device_intr_test.2383330920
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.3776165093
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/16.spi_device_tl_errors.2304895633
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/16.spi_device_tl_intg_err.3369240864
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.68270933
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/17.spi_device_csr_rw.295939848
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/17.spi_device_intr_test.467241018
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.1525962189
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.2500959461
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/18.spi_device_csr_rw.2563657635
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/18.spi_device_intr_test.1591976646
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.103863162
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/18.spi_device_tl_errors.3074719030
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/18.spi_device_tl_intg_err.2629315585
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.254488540
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/19.spi_device_csr_rw.1134376156
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/19.spi_device_intr_test.1814848358
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.1986388293
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/19.spi_device_tl_errors.3840312590
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/19.spi_device_tl_intg_err.757049392
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_aliasing.2178054009
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_bit_bash.1911703079
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.1116952973
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_rw.3089328427
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_intr_test.3391535944
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_mem_partial_access.2523680281
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_mem_walk.4021006285
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.1602042893
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_tl_errors.4176883570
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_tl_intg_err.1980773243
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/20.spi_device_intr_test.931100263
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/21.spi_device_intr_test.1072907071
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/22.spi_device_intr_test.2696284878
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/23.spi_device_intr_test.864859462
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/24.spi_device_intr_test.4202489059
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/25.spi_device_intr_test.3491942717
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/26.spi_device_intr_test.188178523
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/27.spi_device_intr_test.1456211881
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/28.spi_device_intr_test.2705041587
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/29.spi_device_intr_test.4040699273
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_aliasing.2573941020
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_bit_bash.4222595862
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_hw_reset.1880040840
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.3816222803
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_rw.41652434
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_intr_test.1621491300
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_mem_partial_access.4207755693
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_mem_walk.2746976591
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.861100137
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_tl_intg_err.1618044306
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/30.spi_device_intr_test.2838017309
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/31.spi_device_intr_test.2466898186
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/32.spi_device_intr_test.668423681
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/33.spi_device_intr_test.1077021388
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/34.spi_device_intr_test.2184421440
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/35.spi_device_intr_test.1708958965
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/36.spi_device_intr_test.2159964061
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/37.spi_device_intr_test.3191981194
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/38.spi_device_intr_test.515769104
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/39.spi_device_intr_test.1976293726
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_aliasing.865728551
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_bit_bash.828087492
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_hw_reset.2813932259
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.3411072705
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_rw.1622328327
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_intr_test.1442982932
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_mem_partial_access.1898238968
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_mem_walk.2159347025
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.4264080680
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_tl_errors.602445181
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_tl_intg_err.3835503274
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/40.spi_device_intr_test.3836107002
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/41.spi_device_intr_test.2036972769
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/42.spi_device_intr_test.3477655917
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/43.spi_device_intr_test.1963433347
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/44.spi_device_intr_test.1187660520
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/45.spi_device_intr_test.671359363
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/46.spi_device_intr_test.2891845876
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/47.spi_device_intr_test.2227632680
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/48.spi_device_intr_test.1172600957
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/49.spi_device_intr_test.3916012630
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.487254284
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/5.spi_device_csr_rw.2314888308
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/5.spi_device_intr_test.2734911758
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.1288458199
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/5.spi_device_tl_errors.2202308280
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/5.spi_device_tl_intg_err.2163914412
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.2080464762
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/6.spi_device_csr_rw.2598655243
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/6.spi_device_intr_test.1159936758
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.906165606
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/6.spi_device_tl_errors.127539389
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/6.spi_device_tl_intg_err.2858432708
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.1960717028
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/7.spi_device_csr_rw.3006419800
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/7.spi_device_intr_test.1987177535
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.1156545035
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/7.spi_device_tl_errors.1072078664
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/7.spi_device_tl_intg_err.2718203579
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.3908805610
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/8.spi_device_csr_rw.1372541285
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/8.spi_device_intr_test.2343627660
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.1541051182
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/8.spi_device_tl_intg_err.2879485422
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.2472032462
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/9.spi_device_csr_rw.3785337920
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/9.spi_device_intr_test.3793683810
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.661367373
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/9.spi_device_tl_errors.1840252711
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/9.spi_device_tl_intg_err.929822618
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_cfg_cmd.2961118043
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_flash_all.1338032484
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_flash_mode.2110784685
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_mailbox.745774811
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_pass_addr_payload_swap.978871977
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_tpm_read_hw_reg.3171751402
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_tpm_rw.4158538648
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_tpm_sts_read.1474033762
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_upload.217727029
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_alert_test.4255012017
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_cfg_cmd.3078260192
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_csb_read.1446206815
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_flash_all.3417066384
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_flash_and_tpm.2413344490
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_flash_and_tpm_min_idle.377857314
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_flash_mode_ignore_cmds.2975995976
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_intercept.988783510
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_mailbox.3740972238
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_pass_addr_payload_swap.1865906278
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_read_buffer_direct.2531228617
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_sec_cm.4019912874
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_stress_all.375010850
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_tpm_all.2324622821
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_tpm_read_hw_reg.1975291193
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_tpm_rw.3210115454
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_tpm_sts_read.3025074057
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_upload.3089397268
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_alert_test.4026315045
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_cfg_cmd.4109182376
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_csb_read.47431110
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_flash_all.1045794275
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_flash_and_tpm.81448576
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_flash_and_tpm_min_idle.190672070
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_flash_mode.1315924407
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_flash_mode_ignore_cmds.1434963375
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_intercept.445178097
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_mailbox.1689010498
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_pass_addr_payload_swap.1051919614
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_pass_cmd_filtering.2050366648
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_read_buffer_direct.3711962474
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_stress_all.995140469
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_tpm_all.4233997133
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_tpm_read_hw_reg.1704768543
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_tpm_rw.1390158640
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_tpm_sts_read.4283935580
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_alert_test.2414820831
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_cfg_cmd.2385465067
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_csb_read.4006529671
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_flash_and_tpm_min_idle.2272329222
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_flash_mode_ignore_cmds.2841291033
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_intercept.1881275252
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_mailbox.1242119817
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_pass_addr_payload_swap.1862443212
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_pass_cmd_filtering.3527350857
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_read_buffer_direct.425199846
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_stress_all.1272151322
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_tpm_all.708238539
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_tpm_read_hw_reg.3088699242
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_tpm_rw.4837955
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_tpm_sts_read.1519574847
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_upload.2235391538
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_alert_test.143289492
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_cfg_cmd.3816039765
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_csb_read.1807667441
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_flash_all.3793876282
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_flash_and_tpm.4055739301
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_flash_and_tpm_min_idle.3933382140
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_flash_mode.2782231633
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_flash_mode_ignore_cmds.106974597
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_mailbox.3762475575
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_pass_addr_payload_swap.2886311477
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_pass_cmd_filtering.2825069862
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_read_buffer_direct.3866190298
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_stress_all.1974296232
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_tpm_all.918642419
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_tpm_read_hw_reg.151948192
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_tpm_rw.239409899
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_tpm_sts_read.2377169261
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_upload.3916624344
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_alert_test.372009827
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_cfg_cmd.1131833787
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_csb_read.3211135384
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_flash_all.3996098160
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_flash_and_tpm_min_idle.2790096538
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_flash_mode.1335900201
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_flash_mode_ignore_cmds.294835398
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_intercept.1390184377
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_mailbox.3924133406
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_pass_addr_payload_swap.2218964054
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_pass_cmd_filtering.260465108
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_read_buffer_direct.2121547180
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_stress_all.21573028
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_tpm_read_hw_reg.3647689575
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_tpm_rw.2651233095
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_tpm_sts_read.421780947
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_upload.573456621
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_alert_test.1563275220
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_cfg_cmd.2702251865
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_csb_read.2862201161
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_flash_all.4275677612
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_flash_and_tpm.3404533730
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_flash_and_tpm_min_idle.4192143831
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_flash_mode.2980314559
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_flash_mode_ignore_cmds.1350125905
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_intercept.2383903544
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_mailbox.2700120413
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_pass_addr_payload_swap.2258464180
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_pass_cmd_filtering.388127588
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_read_buffer_direct.315076723
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_tpm_all.2814467516
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_tpm_read_hw_reg.2263850515
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_tpm_rw.2906794106
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_tpm_sts_read.835831365
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_upload.2165891568
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_alert_test.1218482029
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_cfg_cmd.1875709004
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_csb_read.2570358010
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_flash_all.584420477
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_flash_and_tpm.886288193
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_flash_and_tpm_min_idle.1102339199
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_flash_mode.1826561143
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_flash_mode_ignore_cmds.66027877
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_intercept.3470636813
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_mailbox.4106947769
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_pass_addr_payload_swap.2770136060
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_pass_cmd_filtering.531325368
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_read_buffer_direct.2449016304
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_stress_all.1285630125
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_tpm_all.55263594
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_tpm_read_hw_reg.3205698597
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_tpm_rw.606064205
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_tpm_sts_read.516520637
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_upload.2541484096
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_alert_test.2688312059
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_cfg_cmd.2470192830
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_csb_read.3395100187
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_flash_all.1581956568
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_flash_and_tpm.2646875381
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_flash_and_tpm_min_idle.2270362094
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_flash_mode.2397181610
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_intercept.2290113753
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_mailbox.936431782
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_pass_addr_payload_swap.803469217
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_pass_cmd_filtering.2597919703
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_read_buffer_direct.2297955869
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_tpm_all.1616502097
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_tpm_read_hw_reg.94955540
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_tpm_rw.3347194761
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_tpm_sts_read.3996012095
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_upload.3251201324
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_alert_test.3200363956
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_cfg_cmd.3178190516
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_csb_read.2519397528
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_flash_all.3653158005
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_flash_and_tpm.3787272231
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_flash_and_tpm_min_idle.4020234598
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_flash_mode.2547734816
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_flash_mode_ignore_cmds.3801596972
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_intercept.352598345
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_mailbox.4287140527
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_pass_addr_payload_swap.2655837694
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_pass_cmd_filtering.3737721727
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_read_buffer_direct.1855235229
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_stress_all.2541328491
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_tpm_all.1647650365
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_tpm_read_hw_reg.2695070152
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_tpm_rw.3941326712
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_tpm_sts_read.1635874828
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_upload.252131814
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_alert_test.1959964837
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_cfg_cmd.3107614223
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_csb_read.368021943
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_flash_all.1513149007
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_flash_and_tpm.2859188394
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_flash_and_tpm_min_idle.1971332829
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_flash_mode.3048712319
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_flash_mode_ignore_cmds.3188609616
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_intercept.1328369424
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_mailbox.102329247
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_pass_addr_payload_swap.1235579640
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_pass_cmd_filtering.3850294677
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_read_buffer_direct.2078671864
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_stress_all.1300724423
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_tpm_all.2345103587
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_tpm_read_hw_reg.4193104843
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_tpm_rw.921470303
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_tpm_sts_read.2355967740
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_upload.3344833950
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_alert_test.2234576323
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_cfg_cmd.1826606378
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_csb_read.523718687
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_flash_and_tpm_min_idle.1464439194
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_flash_mode.3056326375
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_flash_mode_ignore_cmds.4201745318
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_intercept.1930251410
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_mailbox.3278585709
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_pass_addr_payload_swap.3264655029
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_pass_cmd_filtering.801260416
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_read_buffer_direct.1773201581
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_stress_all.754175009
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_tpm_all.3545501267
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_tpm_read_hw_reg.496030329
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_tpm_rw.2336923621
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_tpm_sts_read.1134343841
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_upload.3666914526
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_alert_test.2223713199
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_cfg_cmd.419984584
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_csb_read.2395607274
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_flash_all.2490341189
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_flash_mode.4271533183
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_flash_mode_ignore_cmds.1240336489
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_intercept.924356668
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_mailbox.1054684659
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_pass_addr_payload_swap.4209184932
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_pass_cmd_filtering.3175821846
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_read_buffer_direct.3482856355
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_sec_cm.3340880636
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_tpm_read_hw_reg.2729346515
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_tpm_rw.150461230
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_tpm_sts_read.2203245
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_upload.3412333116
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_alert_test.1910990706
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_cfg_cmd.1013926874
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_csb_read.2828391095
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_flash_all.3315437238
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_flash_and_tpm.2552668023
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_flash_and_tpm_min_idle.3876750745
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_flash_mode.454327999
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_flash_mode_ignore_cmds.285276677
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_intercept.4227688381
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_mailbox.136519726
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_pass_addr_payload_swap.945171331
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_pass_cmd_filtering.4004961571
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_read_buffer_direct.3773877088
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_stress_all.956307715
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_tpm_all.4087088379
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_tpm_read_hw_reg.1632648714
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_tpm_rw.3722441494
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_tpm_sts_read.556692528
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_upload.593865406
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_alert_test.342811830
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_cfg_cmd.3010294147
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_csb_read.2379494583
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_flash_all.3280889315
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_flash_and_tpm.3189374669
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_flash_and_tpm_min_idle.2777381377
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_flash_mode.3999691835
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_flash_mode_ignore_cmds.2447163250
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_intercept.1711586982
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_mailbox.488512401
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_pass_addr_payload_swap.4270315012
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_pass_cmd_filtering.1168789126
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_read_buffer_direct.1645540915
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_tpm_all.3366651710
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_tpm_read_hw_reg.3392891900
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_tpm_rw.1635134553
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_tpm_sts_read.3993827426
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_upload.260889754
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_alert_test.4025628209
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_cfg_cmd.2211111759
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_csb_read.1018179169
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_flash_all.2806453080
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_flash_and_tpm.3591185512
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_flash_mode.1319514140
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_flash_mode_ignore_cmds.1824878117
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_intercept.2622384258
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_mailbox.398346841
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_pass_addr_payload_swap.3124637965
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_pass_cmd_filtering.1975320444
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_read_buffer_direct.226682098
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_stress_all.2212620835
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_tpm_all.1434947644
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_tpm_read_hw_reg.4103504023
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_tpm_rw.3006803244
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_tpm_sts_read.3649868001
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_upload.127759810
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_alert_test.1528359956
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_cfg_cmd.3235153243
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_csb_read.2545758483
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_flash_all.2237269537
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_flash_and_tpm.2770564793
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_flash_and_tpm_min_idle.1622296393
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_flash_mode.1143504303
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_flash_mode_ignore_cmds.332388979
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_intercept.2577235216
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_mailbox.1058970617
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_pass_addr_payload_swap.2453160415
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_pass_cmd_filtering.2159436777
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_read_buffer_direct.3495179492
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_stress_all.782791771
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_tpm_all.3770081580
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_tpm_read_hw_reg.3517825557
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_tpm_rw.854024238
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_tpm_sts_read.1369262022
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_upload.3014197717
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_alert_test.1530372960
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_cfg_cmd.756872039
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_csb_read.2347991628
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_flash_and_tpm.3191360003
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_flash_and_tpm_min_idle.2443637543
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_flash_mode.343085573
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_flash_mode_ignore_cmds.2056629045
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_intercept.2304475162
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_mailbox.1394252988
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_pass_addr_payload_swap.3878417511
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_pass_cmd_filtering.1624944667
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_read_buffer_direct.3488796993
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_stress_all.3391287273
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_tpm_all.3952077862
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_tpm_read_hw_reg.1741763635
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_tpm_rw.2049942643
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_tpm_sts_read.810209470
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_upload.898557027
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_alert_test.3323730465
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_cfg_cmd.821011085
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_csb_read.1202129788
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_flash_all.538728935
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_flash_and_tpm.3605183613
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_flash_and_tpm_min_idle.993849582
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_flash_mode.24013720
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_flash_mode_ignore_cmds.107394866
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_intercept.343017553
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_mailbox.3074790013
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_pass_addr_payload_swap.1162378588
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_pass_cmd_filtering.1776247193
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_read_buffer_direct.179322214
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_stress_all.1595761172
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_tpm_all.1817222839
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_tpm_read_hw_reg.1294057984
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_tpm_rw.66523160
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_tpm_sts_read.2598423176
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_upload.2808490029
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_alert_test.984704723
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_cfg_cmd.1638029530
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_csb_read.3237552174
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_flash_all.3129822105
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_flash_and_tpm.2606296730
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_flash_and_tpm_min_idle.497351727
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_flash_mode.1378932486
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_flash_mode_ignore_cmds.542547818
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_intercept.2315487504
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_mailbox.1077866586
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_pass_addr_payload_swap.1092116173
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_pass_cmd_filtering.337098978
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_read_buffer_direct.2829660147
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_stress_all.2186506944
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_tpm_all.175679498
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_tpm_read_hw_reg.1891222415
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_tpm_rw.3180271496
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_tpm_sts_read.4127142132
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_upload.2164959374
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_alert_test.563721363
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_cfg_cmd.861789743
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_csb_read.3155551236
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_flash_all.1496729402
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_flash_and_tpm.3968609833
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_flash_and_tpm_min_idle.4156979555
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_flash_mode.3408217549
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_flash_mode_ignore_cmds.614495213
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_mailbox.1728262555
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_pass_addr_payload_swap.1639122908
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_pass_cmd_filtering.3999475733
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_read_buffer_direct.3316818634
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_stress_all.359171444
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_tpm_all.1904614254
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_tpm_read_hw_reg.1144727982
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_tpm_rw.3800611300
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_tpm_sts_read.3815903734
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_upload.1238087185
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_alert_test.685008343
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_cfg_cmd.2367035199
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_csb_read.345241204
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_flash_and_tpm.2036085045
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_flash_and_tpm_min_idle.3243394300
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_flash_mode.3059269801
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_flash_mode_ignore_cmds.484923177
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_intercept.3493818545
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_mailbox.391809510
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_pass_addr_payload_swap.1141522650
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_pass_cmd_filtering.4095649420
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_read_buffer_direct.4153927290
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_stress_all.4083732402
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_tpm_all.161729610
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_tpm_read_hw_reg.3245272720
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_tpm_rw.2422951712
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_tpm_sts_read.2597221668
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_upload.2266186023
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_alert_test.3761730987
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_cfg_cmd.2340130571
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_csb_read.353850982
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_flash_all.3018496500
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_flash_and_tpm.1586511097
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_flash_and_tpm_min_idle.1110173230
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_flash_mode.160675785
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_flash_mode_ignore_cmds.2034831670
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_intercept.3071077654
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_mailbox.3264175626
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_pass_addr_payload_swap.1113101044
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_pass_cmd_filtering.3186540875
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_read_buffer_direct.2410004437
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_stress_all.3186141948
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_tpm_all.906275138
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_tpm_read_hw_reg.2167471560
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_tpm_rw.666890156
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_tpm_sts_read.2880917991
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_upload.276014292
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_alert_test.3954485765
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_cfg_cmd.2677988478
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_csb_read.178514390
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_flash_all.3338647770
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_flash_and_tpm_min_idle.1929875415
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_flash_mode.16056764
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_intercept.216383289
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_mailbox.3053394791
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_pass_addr_payload_swap.2495053285
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_pass_cmd_filtering.3818240952
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_read_buffer_direct.3433459221
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_sec_cm.2199950093
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_stress_all.321769076
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_tpm_all.1706108252
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_tpm_read_hw_reg.1666540062
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_tpm_rw.1036947333
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_tpm_sts_read.2932997633
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_upload.1355797548
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_alert_test.1489564815
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_cfg_cmd.670589925
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_csb_read.2562277315
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_flash_all.3500731568
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_flash_and_tpm.1870378129
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_flash_and_tpm_min_idle.670601249
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_flash_mode.1544808547
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_flash_mode_ignore_cmds.1199360092
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_intercept.3738798057
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_mailbox.2896057791
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_pass_addr_payload_swap.1031275311
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_pass_cmd_filtering.3687904138
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_read_buffer_direct.804441966
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_stress_all.4207214492
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_tpm_all.3094012300
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_tpm_read_hw_reg.1648465672
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_tpm_rw.1397125972
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_tpm_sts_read.1897382681
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_upload.3637081874
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_alert_test.1612101791
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_cfg_cmd.1899308275
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_csb_read.4230146457
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_flash_all.1625954035
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_flash_and_tpm.1994855066
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_flash_and_tpm_min_idle.4120849213
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_flash_mode.2392337043
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_flash_mode_ignore_cmds.238541572
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_intercept.611859597
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_mailbox.2049242668
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_pass_addr_payload_swap.1317480856
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_pass_cmd_filtering.3955014107
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_read_buffer_direct.2988896228
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_stress_all.1777392722
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_tpm_all.626020632
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_tpm_read_hw_reg.358358598
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_tpm_rw.4019033213
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_tpm_sts_read.3161526553
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_upload.21508102
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_alert_test.2270664470
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_cfg_cmd.3614755825
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_csb_read.2769429117
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_flash_all.3445495192
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_flash_and_tpm.1021823894
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_flash_and_tpm_min_idle.2290740417
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_flash_mode_ignore_cmds.110596341
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_intercept.1386621741
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_mailbox.1297551144
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_pass_addr_payload_swap.4258498512
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_pass_cmd_filtering.3440674449
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_read_buffer_direct.1082395682
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_tpm_all.3736767469
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_tpm_read_hw_reg.9444770
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_tpm_rw.2679350959
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_tpm_sts_read.1109048180
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_upload.394613116
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_alert_test.581876323
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_cfg_cmd.403474643
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_csb_read.1374800890
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_flash_all.4279062261
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_flash_and_tpm.1581598987
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_flash_and_tpm_min_idle.3860513562
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_flash_mode.3229014475
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_flash_mode_ignore_cmds.1573260908
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_intercept.2263934257
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_mailbox.3089088758
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_pass_addr_payload_swap.2078989170
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_pass_cmd_filtering.248186354
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_read_buffer_direct.25121905
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_stress_all.1139083366
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_tpm_all.1400926168
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_tpm_read_hw_reg.1148683312
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_tpm_rw.52266090
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_tpm_sts_read.3415248306
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_upload.484153245
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_alert_test.4252127813
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_cfg_cmd.3145940736
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_csb_read.3158426230
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_flash_all.3494120921
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_flash_and_tpm_min_idle.668539451
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_flash_mode.4115186079
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_flash_mode_ignore_cmds.700682896
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_intercept.3722396159
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_mailbox.840432758
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_pass_addr_payload_swap.1972273984
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_pass_cmd_filtering.4065588656
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_read_buffer_direct.338781197
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_stress_all.1265477544
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_tpm_all.1819051146
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_tpm_read_hw_reg.3679700112
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_tpm_rw.1309787142
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_tpm_sts_read.2959318025
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_upload.1153451646
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_alert_test.2588128603
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_cfg_cmd.1968941017
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_csb_read.4036902493
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_flash_all.2228119826
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_flash_and_tpm.2128221390
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_flash_mode.459408109
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_flash_mode_ignore_cmds.1460729875
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_intercept.3433319067
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_mailbox.2158471818
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_pass_addr_payload_swap.2345357721
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_pass_cmd_filtering.1412304555
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_read_buffer_direct.3794632787
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_stress_all.2685384921
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_tpm_all.600251988
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_tpm_read_hw_reg.3816776762
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_tpm_rw.836364557
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_tpm_sts_read.3520306146
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_upload.2812532665
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_alert_test.3976432521
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_cfg_cmd.2636266871
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_csb_read.2119575698
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_flash_all.105712299
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_flash_and_tpm.2941580507
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_flash_and_tpm_min_idle.2821321289
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_flash_mode.2172126709
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_flash_mode_ignore_cmds.2503071374
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_intercept.3897750311
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_mailbox.876914655
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_pass_addr_payload_swap.2985333434
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_pass_cmd_filtering.2565760829
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_read_buffer_direct.2119568371
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_stress_all.3165596970
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_tpm_all.818880942
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_tpm_read_hw_reg.1293786740
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_tpm_rw.4196151357
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_tpm_sts_read.3433081241
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_upload.1460043519
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_alert_test.2653397532
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_cfg_cmd.836368310
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_csb_read.2726530893
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_flash_all.1980064004
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_flash_and_tpm.3768019752
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_flash_and_tpm_min_idle.1918675412
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_flash_mode.3156659129
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_flash_mode_ignore_cmds.3119944840
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_intercept.2943956131
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_mailbox.80225063
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_pass_addr_payload_swap.470319973
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_pass_cmd_filtering.1573882601
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_read_buffer_direct.1114569314
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_stress_all.1233416292
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_tpm_all.1244589209
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_tpm_read_hw_reg.833628456
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_tpm_rw.933968834
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_tpm_sts_read.3381553495
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_upload.2677097680
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_alert_test.2067033842
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_cfg_cmd.2660555394
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_csb_read.2815461124
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_flash_all.3056082256
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_flash_and_tpm.4251134683
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_flash_and_tpm_min_idle.1445267782
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_flash_mode.2545751471
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_flash_mode_ignore_cmds.693046341
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_intercept.803848478
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_mailbox.934956270
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_pass_addr_payload_swap.3257575299
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_pass_cmd_filtering.2659028069
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_read_buffer_direct.2112694707
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_tpm_all.1634708209
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_tpm_read_hw_reg.3760019686
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_tpm_rw.1191698863
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_tpm_sts_read.2443082926
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_upload.3901478666
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_alert_test.3369652177
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_cfg_cmd.3316641239
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_csb_read.3154467412
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_flash_all.2879230596
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_flash_and_tpm.3289967605
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_flash_and_tpm_min_idle.3198497827
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_flash_mode.535038443
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_flash_mode_ignore_cmds.3123083525
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_intercept.3286747068
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_mailbox.2788534828
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_pass_addr_payload_swap.806359007
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_pass_cmd_filtering.3167648690
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_read_buffer_direct.1184224257
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_stress_all.3309264488
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_tpm_all.569337994
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_tpm_read_hw_reg.3452848743
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_tpm_rw.492927027
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_tpm_sts_read.3660838217
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_upload.2453285719
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_alert_test.668643119
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_cfg_cmd.3122959249
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_csb_read.3081741476
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_flash_all.3101565224
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_flash_and_tpm.4214676383
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_flash_mode.3898976367
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_intercept.1896665931
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_mailbox.1985335567
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_pass_addr_payload_swap.3735417540
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_pass_cmd_filtering.4039483634
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_read_buffer_direct.550326096
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_sec_cm.2697202101
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_stress_all.2181042236
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_tpm_all.2509369734
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_tpm_read_hw_reg.2288226150
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_tpm_rw.3661594444
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_tpm_sts_read.3153637309
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_upload.1258492914
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_alert_test.527703353
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_cfg_cmd.611802674
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_csb_read.2188613194
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_flash_all.266552405
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_flash_and_tpm.490707415
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_flash_and_tpm_min_idle.1308062494
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_flash_mode.2248327999
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_flash_mode_ignore_cmds.2142368576
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_intercept.558071624
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_mailbox.2950867055
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_pass_addr_payload_swap.2364196964
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_pass_cmd_filtering.2241678805
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_read_buffer_direct.2467674877
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_stress_all.3523861448
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_tpm_all.2439753751
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_tpm_read_hw_reg.1369095211
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_tpm_rw.3782509720
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_tpm_sts_read.18728720
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_upload.1571743420
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_alert_test.2550657867
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_cfg_cmd.2995379087
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_csb_read.1481652338
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_flash_all.3113965485
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_flash_and_tpm.234438127
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_flash_and_tpm_min_idle.2609172228
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_flash_mode.1276334018
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_flash_mode_ignore_cmds.2560842937
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_intercept.922571138
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_mailbox.3300242540
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_pass_addr_payload_swap.2031293573
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_pass_cmd_filtering.609125740
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_read_buffer_direct.4142034865
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_stress_all.3070137852
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_tpm_all.3935259792
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_tpm_read_hw_reg.3148760015
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_tpm_rw.2812313378
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_tpm_sts_read.3746534137
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_upload.575339218
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_alert_test.2550403516
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_cfg_cmd.1591017878
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_csb_read.1153575481
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_flash_all.944359715
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_flash_and_tpm.2469618021
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_flash_and_tpm_min_idle.3474273464
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_flash_mode.2922196234
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_flash_mode_ignore_cmds.3178131370
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_intercept.127179016
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_mailbox.2761446720
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_pass_addr_payload_swap.2361076560
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_pass_cmd_filtering.1997045870
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_read_buffer_direct.2223885923
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_stress_all.3741615859
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_tpm_all.1310350205
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_tpm_read_hw_reg.601236774
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_tpm_rw.403586784
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_tpm_sts_read.438945962
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_upload.4220308444
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_alert_test.1168593384
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_cfg_cmd.1445065974
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_csb_read.1126107264
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_flash_all.2765617914
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_flash_and_tpm.4069202028
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_flash_and_tpm_min_idle.3494404227
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_flash_mode.4162412852
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_flash_mode_ignore_cmds.1302080478
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_intercept.3145399717
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_mailbox.2516723147
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_pass_addr_payload_swap.2325580547
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_pass_cmd_filtering.948670958
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_read_buffer_direct.1192806903
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_stress_all.3750994996
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_tpm_all.2849163181
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_tpm_read_hw_reg.3157586075
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_tpm_rw.2475360899
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_tpm_sts_read.1478472022
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_upload.2905989623
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_alert_test.2520630442
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_cfg_cmd.1858470264
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_csb_read.4242286949
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_flash_and_tpm.1489321583
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_flash_and_tpm_min_idle.4292148891
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_flash_mode.3902216607
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_flash_mode_ignore_cmds.4021666905
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_intercept.1167562599
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_mailbox.93729336
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_pass_addr_payload_swap.1935763362
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_pass_cmd_filtering.2214777938
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_read_buffer_direct.1512193833
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_stress_all.2109180805
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_tpm_all.479423653
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_tpm_read_hw_reg.1368667837
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_tpm_rw.428123872
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_tpm_sts_read.1714020998
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_upload.77175378
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_alert_test.3991030924
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_cfg_cmd.264697053
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_csb_read.3240595621
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_flash_all.4106023601
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_flash_and_tpm.2809596077
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_flash_and_tpm_min_idle.3001456297
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_flash_mode.1103715869
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_flash_mode_ignore_cmds.2974878211
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_intercept.301309706
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_mailbox.2813595731
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_pass_addr_payload_swap.3986958119
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_pass_cmd_filtering.1289375854
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_read_buffer_direct.2066990291
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_stress_all.3677105644
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_tpm_all.3191205512
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_tpm_read_hw_reg.470439570
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_tpm_rw.3299796409
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_tpm_sts_read.3790382176
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_upload.3570583994
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_alert_test.3555998835
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_cfg_cmd.2882961942
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_csb_read.4095665627
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_flash_all.2748654049
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_flash_and_tpm.3125830484
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_flash_and_tpm_min_idle.29514426
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_flash_mode.319264756
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_flash_mode_ignore_cmds.249121334
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_intercept.1025184135
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_mailbox.3899273492
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_pass_addr_payload_swap.3278798309
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_pass_cmd_filtering.2330140950
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_read_buffer_direct.3351575269
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_stress_all.3949741764
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_tpm_all.650531358
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_tpm_read_hw_reg.2972601523
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_tpm_rw.3634913089
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_tpm_sts_read.2978512909
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_upload.1676382009
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_alert_test.4098150120
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_cfg_cmd.3194014776
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_csb_read.3697227314
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_flash_all.3689279695
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_flash_and_tpm.3521891511
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_flash_and_tpm_min_idle.3330232551
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_flash_mode.1673930633
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_flash_mode_ignore_cmds.2509537603
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_intercept.1201876130
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_mailbox.1429222714
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_pass_addr_payload_swap.2933854961
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_pass_cmd_filtering.184416702
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_read_buffer_direct.1550915540
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_stress_all.1700897495
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_tpm_all.193238663
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_tpm_read_hw_reg.4103151223
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_tpm_rw.4220488546
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_tpm_sts_read.1918220131
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_upload.1635298657
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_alert_test.2250295008
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_cfg_cmd.3092757784
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_csb_read.1674763162
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_flash_all.2082732660
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_flash_and_tpm.1575641534
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_flash_and_tpm_min_idle.3618104706
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_flash_mode.2168919419
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_flash_mode_ignore_cmds.958340920
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_intercept.3221263060
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_mailbox.1944771036
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_pass_addr_payload_swap.725344209
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_pass_cmd_filtering.2429345906
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_read_buffer_direct.2548659124
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_stress_all.722564545
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_tpm_all.3178606317
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_tpm_read_hw_reg.2207922486
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_tpm_rw.952911308
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_tpm_sts_read.1345124578
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_upload.4147304534
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_alert_test.794339760
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_cfg_cmd.1717724395
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_csb_read.3931043339
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_flash_all.830700312
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_flash_and_tpm.4106300266
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_flash_and_tpm_min_idle.375261566
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_flash_mode.3793798550
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_flash_mode_ignore_cmds.2161210541
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_intercept.1940188635
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_mailbox.1411857478
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_pass_addr_payload_swap.3088642870
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_pass_cmd_filtering.3772006374
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_read_buffer_direct.4193148204
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_stress_all.280731261
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_tpm_all.1260756060
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_tpm_read_hw_reg.3169369566
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_tpm_rw.3491493855
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_tpm_sts_read.3855064302
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_upload.1634977801
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_alert_test.2673409929
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_cfg_cmd.4138800779
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_csb_read.836900452
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_flash_all.1198471655
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_flash_and_tpm_min_idle.1488421533
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_flash_mode.3010468998
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_flash_mode_ignore_cmds.1346950676
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_intercept.2912151059
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_mailbox.4145076136
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_pass_addr_payload_swap.2183659092
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_pass_cmd_filtering.1787511671
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_read_buffer_direct.353164173
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_stress_all.3984408316
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_tpm_all.1184621158
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_tpm_read_hw_reg.3945309129
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_tpm_rw.2616572162
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_tpm_sts_read.2632139348
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_upload.2684217919
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_alert_test.1037456293
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_cfg_cmd.3195787578
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_csb_read.2265685068
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_flash_all.2551365105
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_flash_and_tpm.1670818593
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_flash_and_tpm_min_idle.629631804
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_flash_mode.2683461201
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_flash_mode_ignore_cmds.2007598858
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_intercept.4086346802
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_mailbox.1814456770
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_pass_addr_payload_swap.1563210309
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_pass_cmd_filtering.2332262488
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_read_buffer_direct.2071592163
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_tpm_all.1358636390
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_tpm_read_hw_reg.2720709914
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_tpm_rw.2682741092
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_tpm_sts_read.2059254279
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_upload.4068652442
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_alert_test.1768050052
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_cfg_cmd.2641657238
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_csb_read.827542487
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_flash_all.339940772
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_flash_and_tpm.1623212775
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_flash_and_tpm_min_idle.751155144
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_flash_mode.571726056
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_flash_mode_ignore_cmds.4152993410
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_intercept.3371905665
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_mailbox.3901098892
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_pass_addr_payload_swap.1602876564
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_pass_cmd_filtering.3762195740
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_read_buffer_direct.2153631862
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_stress_all.3596808917
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_tpm_all.4044045100
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_tpm_read_hw_reg.1376550405
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_tpm_rw.945771609
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_tpm_sts_read.539420112
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_upload.586440411
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_alert_test.3217166262
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_cfg_cmd.2020038357
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_csb_read.1200053160
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_flash_all.170498968
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_flash_and_tpm.1923377815
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_flash_and_tpm_min_idle.2266016727
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_flash_mode.61703290
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_flash_mode_ignore_cmds.2932119012
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_intercept.3195377521
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_mailbox.2394020346
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_pass_addr_payload_swap.3919886148
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_pass_cmd_filtering.2500698445
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_read_buffer_direct.565051537
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_tpm_all.2537187544
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_tpm_read_hw_reg.79245360
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_tpm_rw.2325983212
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_tpm_sts_read.275330890
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_upload.14769273
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_alert_test.1096131513
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_cfg_cmd.2182513498
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_csb_read.246971523
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_flash_all.1205239363
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_flash_and_tpm.1114674411
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_flash_and_tpm_min_idle.3168157201
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_flash_mode.84262877
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_flash_mode_ignore_cmds.1832664755
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_intercept.596352583
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_mailbox.3094325739
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_pass_addr_payload_swap.3644934110
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_pass_cmd_filtering.3413973522
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_read_buffer_direct.458864448
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_stress_all.559200018
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_tpm_all.3673600257
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_tpm_read_hw_reg.722463895
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_tpm_rw.1482964702
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_tpm_sts_read.4082357658
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_upload.3386236710



Total test records in report: 1131
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_tpm_sts_read.3153637309 Oct 12 08:41:57 AM UTC 24 Oct 12 08:41:59 AM UTC 24 67662569 ps
T2 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_csb_read.726700694 Oct 12 08:38:15 AM UTC 24 Oct 12 08:38:17 AM UTC 24 69166264 ps
T3 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_ram_cfg.852811863 Oct 12 08:38:18 AM UTC 24 Oct 12 08:38:20 AM UTC 24 15885737 ps
T4 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_tpm_read_hw_reg.3171751402 Oct 12 08:38:18 AM UTC 24 Oct 12 08:38:21 AM UTC 24 197047531 ps
T5 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_tpm_sts_read.1474033762 Oct 12 08:38:22 AM UTC 24 Oct 12 08:38:24 AM UTC 24 116372322 ps
T6 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_tpm_rw.4158538648 Oct 12 08:38:25 AM UTC 24 Oct 12 08:38:29 AM UTC 24 90070067 ps
T7 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_pass_cmd_filtering.2424048480 Oct 12 08:38:26 AM UTC 24 Oct 12 08:38:32 AM UTC 24 140381481 ps
T8 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_intercept.77707460 Oct 12 08:38:32 AM UTC 24 Oct 12 08:38:37 AM UTC 24 496139717 ps
T9 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_cfg_cmd.2961118043 Oct 12 08:38:41 AM UTC 24 Oct 12 08:38:45 AM UTC 24 149290575 ps
T10 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_tpm_all.908834159 Oct 12 08:38:21 AM UTC 24 Oct 12 08:38:46 AM UTC 24 3330467781 ps
T11 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_pass_addr_payload_swap.978871977 Oct 12 08:38:29 AM UTC 24 Oct 12 08:38:48 AM UTC 24 5131220662 ps
T12 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_mailbox.745774811 Oct 12 08:38:39 AM UTC 24 Oct 12 08:38:55 AM UTC 24 1280692201 ps
T13 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_read_buffer_direct.2630706598 Oct 12 08:38:47 AM UTC 24 Oct 12 08:38:55 AM UTC 24 162655865 ps
T14 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_upload.217727029 Oct 12 08:38:39 AM UTC 24 Oct 12 08:38:58 AM UTC 24 4454606233 ps
T15 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_sec_cm.3674994973 Oct 12 08:38:58 AM UTC 24 Oct 12 08:39:01 AM UTC 24 43075635 ps
T16 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_flash_mode.2110784685 Oct 12 08:38:46 AM UTC 24 Oct 12 08:39:02 AM UTC 24 1805553080 ps
T23 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_alert_test.3698775696 Oct 12 08:39:02 AM UTC 24 Oct 12 08:39:04 AM UTC 24 13816172 ps
T17 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_csb_read.1446206815 Oct 12 08:39:03 AM UTC 24 Oct 12 08:39:05 AM UTC 24 36915935 ps
T24 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_tpm_read_hw_reg.1975291193 Oct 12 08:39:06 AM UTC 24 Oct 12 08:39:14 AM UTC 24 2330376535 ps
T25 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_tpm_all.2324622821 Oct 12 08:39:08 AM UTC 24 Oct 12 08:39:16 AM UTC 24 346152213 ps
T26 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_tpm_sts_read.3025074057 Oct 12 08:39:15 AM UTC 24 Oct 12 08:39:17 AM UTC 24 42099121 ps
T27 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_tpm_rw.3210115454 Oct 12 08:39:17 AM UTC 24 Oct 12 08:39:23 AM UTC 24 1092363845 ps
T18 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_pass_cmd_filtering.3139448399 Oct 12 08:39:18 AM UTC 24 Oct 12 08:39:28 AM UTC 24 1851322354 ps
T19 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_pass_addr_payload_swap.1865906278 Oct 12 08:39:24 AM UTC 24 Oct 12 08:39:34 AM UTC 24 1334008361 ps
T51 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_intercept.988783510 Oct 12 08:39:30 AM UTC 24 Oct 12 08:39:37 AM UTC 24 713707937 ps
T113 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_mailbox.3740972238 Oct 12 08:39:35 AM UTC 24 Oct 12 08:39:41 AM UTC 24 775582100 ps
T54 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_cfg_cmd.3078260192 Oct 12 08:39:42 AM UTC 24 Oct 12 08:39:46 AM UTC 24 123222749 ps
T52 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_upload.3089397268 Oct 12 08:39:38 AM UTC 24 Oct 12 08:39:49 AM UTC 24 5628024382 ps
T90 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_flash_all.3417066384 Oct 12 08:40:00 AM UTC 24 Oct 12 08:40:03 AM UTC 24 24945457 ps
T35 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_read_buffer_direct.2531228617 Oct 12 08:39:50 AM UTC 24 Oct 12 08:40:04 AM UTC 24 2846846885 ps
T20 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_stress_all.375010850 Oct 12 08:40:12 AM UTC 24 Oct 12 08:40:14 AM UTC 24 220643189 ps
T21 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_sec_cm.4019912874 Oct 12 08:40:14 AM UTC 24 Oct 12 08:40:17 AM UTC 24 290000255 ps
T84 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_alert_test.4255012017 Oct 12 08:40:15 AM UTC 24 Oct 12 08:40:17 AM UTC 24 55255074 ps
T91 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_csb_read.2395607274 Oct 12 08:40:17 AM UTC 24 Oct 12 08:40:19 AM UTC 24 57754569 ps
T92 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_csb_read.3081741476 Oct 12 08:41:54 AM UTC 24 Oct 12 08:41:56 AM UTC 24 179698593 ps
T93 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_tpm_read_hw_reg.2729346515 Oct 12 08:40:18 AM UTC 24 Oct 12 08:40:20 AM UTC 24 10725512 ps
T28 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_tpm_sts_read.2203245 Oct 12 08:40:21 AM UTC 24 Oct 12 08:40:24 AM UTC 24 69327473 ps
T44 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_flash_mode.217555999 Oct 12 08:39:45 AM UTC 24 Oct 12 08:40:24 AM UTC 24 3305535154 ps
T41 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_tpm_rw.150461230 Oct 12 08:40:21 AM UTC 24 Oct 12 08:40:25 AM UTC 24 144865506 ps
T67 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_pass_cmd_filtering.3175821846 Oct 12 08:40:25 AM UTC 24 Oct 12 08:40:32 AM UTC 24 1545125311 ps
T45 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_intercept.924356668 Oct 12 08:40:27 AM UTC 24 Oct 12 08:40:34 AM UTC 24 4496566552 ps
T55 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_upload.3412333116 Oct 12 08:40:35 AM UTC 24 Oct 12 08:40:46 AM UTC 24 4777571848 ps
T39 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_flash_mode_ignore_cmds.957494655 Oct 12 08:38:46 AM UTC 24 Oct 12 08:40:47 AM UTC 24 25223338676 ps
T63 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_cfg_cmd.419984584 Oct 12 08:40:46 AM UTC 24 Oct 12 08:40:51 AM UTC 24 2379364325 ps
T22 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_stress_all.2469420963 Oct 12 08:38:57 AM UTC 24 Oct 12 08:40:51 AM UTC 24 23037667439 ps
T40 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_tpm_all.2739884739 Oct 12 08:40:20 AM UTC 24 Oct 12 08:40:59 AM UTC 24 10391323775 ps
T46 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_read_buffer_direct.3482856355 Oct 12 08:40:52 AM UTC 24 Oct 12 08:41:00 AM UTC 24 3914840794 ps
T64 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_pass_addr_payload_swap.4209184932 Oct 12 08:40:26 AM UTC 24 Oct 12 08:41:05 AM UTC 24 7894840840 ps
T42 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_flash_mode_ignore_cmds.2975995976 Oct 12 08:39:47 AM UTC 24 Oct 12 08:41:10 AM UTC 24 17738395651 ps
T29 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_sec_cm.3340880636 Oct 12 08:41:11 AM UTC 24 Oct 12 08:41:14 AM UTC 24 203552053 ps
T50 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_flash_mode.4271533183 Oct 12 08:40:48 AM UTC 24 Oct 12 08:41:15 AM UTC 24 1252223961 ps
T85 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_alert_test.2223713199 Oct 12 08:41:15 AM UTC 24 Oct 12 08:41:18 AM UTC 24 37848090 ps
T174 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_csb_read.178514390 Oct 12 08:41:15 AM UTC 24 Oct 12 08:41:18 AM UTC 24 79944459 ps
T65 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_tpm_sts_read.2932997633 Oct 12 08:41:22 AM UTC 24 Oct 12 08:41:24 AM UTC 24 72409359 ps
T394 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_tpm_rw.1036947333 Oct 12 08:41:25 AM UTC 24 Oct 12 08:41:27 AM UTC 24 27792375 ps
T66 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_tpm_read_hw_reg.1666540062 Oct 12 08:41:20 AM UTC 24 Oct 12 08:41:27 AM UTC 24 1719446504 ps
T43 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_tpm_all.1706108252 Oct 12 08:41:20 AM UTC 24 Oct 12 08:41:27 AM UTC 24 835676479 ps
T261 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_upload.1355797548 Oct 12 08:41:34 AM UTC 24 Oct 12 08:41:38 AM UTC 24 132703945 ps
T200 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_mailbox.1054684659 Oct 12 08:40:33 AM UTC 24 Oct 12 08:41:39 AM UTC 24 14283971328 ps
T201 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_pass_addr_payload_swap.2495053285 Oct 12 08:41:28 AM UTC 24 Oct 12 08:41:39 AM UTC 24 1847527057 ps
T284 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_pass_cmd_filtering.3818240952 Oct 12 08:41:28 AM UTC 24 Oct 12 08:41:41 AM UTC 24 272424712 ps
T181 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_flash_mode.16056764 Oct 12 08:41:40 AM UTC 24 Oct 12 08:41:47 AM UTC 24 689473150 ps
T103 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_cfg_cmd.2677988478 Oct 12 08:41:39 AM UTC 24 Oct 12 08:41:48 AM UTC 24 319807226 ps
T395 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_mailbox.3053394791 Oct 12 08:41:30 AM UTC 24 Oct 12 08:41:49 AM UTC 24 4929833459 ps
T30 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_sec_cm.2199950093 Oct 12 08:41:50 AM UTC 24 Oct 12 08:41:53 AM UTC 24 139413778 ps
T155 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_read_buffer_direct.3433459221 Oct 12 08:41:42 AM UTC 24 Oct 12 08:41:53 AM UTC 24 4979521165 ps
T396 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_alert_test.3954485765 Oct 12 08:41:53 AM UTC 24 Oct 12 08:41:55 AM UTC 24 13924560 ps
T47 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_flash_and_tpm.1555504181 Oct 12 08:38:55 AM UTC 24 Oct 12 08:41:59 AM UTC 24 27715614748 ps
T397 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_tpm_rw.3661594444 Oct 12 08:42:00 AM UTC 24 Oct 12 08:42:02 AM UTC 24 18773398 ps
T185 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_intercept.216383289 Oct 12 08:41:28 AM UTC 24 Oct 12 08:42:04 AM UTC 24 9860769091 ps
T398 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_tpm_read_hw_reg.2288226150 Oct 12 08:41:56 AM UTC 24 Oct 12 08:42:04 AM UTC 24 4779034078 ps
T177 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_pass_cmd_filtering.4039483634 Oct 12 08:42:00 AM UTC 24 Oct 12 08:42:07 AM UTC 24 350394433 ps
T272 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_mailbox.1985335567 Oct 12 08:42:06 AM UTC 24 Oct 12 08:42:12 AM UTC 24 398047843 ps
T107 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_pass_addr_payload_swap.3735417540 Oct 12 08:42:03 AM UTC 24 Oct 12 08:42:12 AM UTC 24 569176231 ps
T231 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_intercept.1896665931 Oct 12 08:42:05 AM UTC 24 Oct 12 08:42:13 AM UTC 24 504686847 ps
T48 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_flash_and_tpm_min_idle.825159560 Oct 12 08:38:55 AM UTC 24 Oct 12 08:42:15 AM UTC 24 46037862931 ps
T197 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_cfg_cmd.3122959249 Oct 12 08:42:13 AM UTC 24 Oct 12 08:42:17 AM UTC 24 144065722 ps
T101 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_tpm_all.2509369734 Oct 12 08:41:57 AM UTC 24 Oct 12 08:42:18 AM UTC 24 6959022728 ps
T399 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_flash_and_tpm.4214676383 Oct 12 08:42:19 AM UTC 24 Oct 12 08:42:21 AM UTC 24 27314396 ps
T400 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_flash_mode.3898976367 Oct 12 08:42:13 AM UTC 24 Oct 12 08:42:27 AM UTC 24 8537704274 ps
T224 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_upload.1258492914 Oct 12 08:42:09 AM UTC 24 Oct 12 08:42:28 AM UTC 24 1930932320 ps
T156 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_read_buffer_direct.550326096 Oct 12 08:42:16 AM UTC 24 Oct 12 08:42:28 AM UTC 24 1476881440 ps
T49 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_flash_all.1338032484 Oct 12 08:38:49 AM UTC 24 Oct 12 08:42:29 AM UTC 24 50701522748 ps
T89 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_stress_all.2181042236 Oct 12 08:42:27 AM UTC 24 Oct 12 08:42:30 AM UTC 24 42002528 ps
T401 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_alert_test.668643119 Oct 12 08:42:29 AM UTC 24 Oct 12 08:42:31 AM UTC 24 29865716 ps
T31 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_sec_cm.2697202101 Oct 12 08:42:29 AM UTC 24 Oct 12 08:42:31 AM UTC 24 406183645 ps
T402 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_csb_read.836900452 Oct 12 08:42:30 AM UTC 24 Oct 12 08:42:32 AM UTC 24 16347323 ps
T403 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_tpm_sts_read.2632139348 Oct 12 08:42:33 AM UTC 24 Oct 12 08:42:36 AM UTC 24 137817757 ps
T380 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_tpm_rw.2616572162 Oct 12 08:42:34 AM UTC 24 Oct 12 08:42:38 AM UTC 24 34097449 ps
T404 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_tpm_read_hw_reg.3945309129 Oct 12 08:42:32 AM UTC 24 Oct 12 08:42:39 AM UTC 24 3286327670 ps
T211 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_pass_cmd_filtering.1787511671 Oct 12 08:42:36 AM UTC 24 Oct 12 08:42:45 AM UTC 24 1878763397 ps
T234 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_pass_addr_payload_swap.2183659092 Oct 12 08:42:36 AM UTC 24 Oct 12 08:42:49 AM UTC 24 5207239715 ps
T265 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_intercept.2912151059 Oct 12 08:42:39 AM UTC 24 Oct 12 08:42:50 AM UTC 24 1080367749 ps
T232 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_upload.2684217919 Oct 12 08:42:47 AM UTC 24 Oct 12 08:42:55 AM UTC 24 651358126 ps
T293 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_cfg_cmd.4138800779 Oct 12 08:42:50 AM UTC 24 Oct 12 08:42:58 AM UTC 24 414425242 ps
T53 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_flash_mode_ignore_cmds.796680145 Oct 12 08:42:14 AM UTC 24 Oct 12 08:43:02 AM UTC 24 6022341428 ps
T405 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_flash_mode.3010468998 Oct 12 08:42:50 AM UTC 24 Oct 12 08:43:02 AM UTC 24 2814351450 ps
T184 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_flash_and_tpm_min_idle.1929875415 Oct 12 08:41:47 AM UTC 24 Oct 12 08:43:03 AM UTC 24 7587526453 ps
T157 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_read_buffer_direct.353164173 Oct 12 08:42:55 AM UTC 24 Oct 12 08:43:03 AM UTC 24 442701220 ps
T406 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_alert_test.2673409929 Oct 12 08:43:05 AM UTC 24 Oct 12 08:43:07 AM UTC 24 14703493 ps
T407 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_csb_read.2265685068 Oct 12 08:43:09 AM UTC 24 Oct 12 08:43:12 AM UTC 24 79500190 ps
T378 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_tpm_all.1184621158 Oct 12 08:42:32 AM UTC 24 Oct 12 08:43:13 AM UTC 24 24546212726 ps
T408 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_tpm_sts_read.2059254279 Oct 12 08:43:18 AM UTC 24 Oct 12 08:43:20 AM UTC 24 20266364 ps
T391 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_tpm_rw.2682741092 Oct 12 08:43:22 AM UTC 24 Oct 12 08:43:24 AM UTC 24 17265671 ps
T183 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_flash_mode_ignore_cmds.1346950676 Oct 12 08:42:50 AM UTC 24 Oct 12 08:43:27 AM UTC 24 11647112925 ps
T180 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_pass_cmd_filtering.2332262488 Oct 12 08:43:22 AM UTC 24 Oct 12 08:43:28 AM UTC 24 548192903 ps
T32 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_stress_all.321769076 Oct 12 08:41:49 AM UTC 24 Oct 12 08:43:36 AM UTC 24 39630509409 ps
T409 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_intercept.4086346802 Oct 12 08:43:29 AM UTC 24 Oct 12 08:43:36 AM UTC 24 659921814 ps
T410 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_upload.4068652442 Oct 12 08:43:32 AM UTC 24 Oct 12 08:43:37 AM UTC 24 135317856 ps
T411 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_tpm_read_hw_reg.2720709914 Oct 12 08:43:15 AM UTC 24 Oct 12 08:43:38 AM UTC 24 12489209110 ps
T249 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_flash_mode.2683461201 Oct 12 08:43:37 AM UTC 24 Oct 12 08:43:44 AM UTC 24 111997197 ps
T94 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_flash_mode_ignore_cmds.1240336489 Oct 12 08:40:52 AM UTC 24 Oct 12 08:43:45 AM UTC 24 21699911230 ps
T204 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_mailbox.1814456770 Oct 12 08:43:29 AM UTC 24 Oct 12 08:43:51 AM UTC 24 1128255269 ps
T108 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_flash_mode_ignore_cmds.2007598858 Oct 12 08:43:38 AM UTC 24 Oct 12 08:43:52 AM UTC 24 2352034617 ps
T95 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_flash_all.3338647770 Oct 12 08:41:43 AM UTC 24 Oct 12 08:43:54 AM UTC 24 6368970498 ps
T412 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_alert_test.1037456293 Oct 12 08:43:53 AM UTC 24 Oct 12 08:43:55 AM UTC 24 11232308 ps
T413 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_csb_read.827542487 Oct 12 08:43:54 AM UTC 24 Oct 12 08:43:56 AM UTC 24 49344690 ps
T59 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_pass_addr_payload_swap.1563210309 Oct 12 08:43:26 AM UTC 24 Oct 12 08:43:58 AM UTC 24 4663273307 ps
T158 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_read_buffer_direct.2071592163 Oct 12 08:43:38 AM UTC 24 Oct 12 08:44:00 AM UTC 24 10982321629 ps
T295 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_cfg_cmd.3195787578 Oct 12 08:43:34 AM UTC 24 Oct 12 08:44:01 AM UTC 24 16634642011 ps
T414 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_tpm_sts_read.539420112 Oct 12 08:43:59 AM UTC 24 Oct 12 08:44:01 AM UTC 24 90823138 ps
T415 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_tpm_read_hw_reg.1376550405 Oct 12 08:43:57 AM UTC 24 Oct 12 08:44:02 AM UTC 24 1189775363 ps
T209 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_flash_all.2490341189 Oct 12 08:40:59 AM UTC 24 Oct 12 08:44:02 AM UTC 24 30171899149 ps
T387 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_tpm_rw.945771609 Oct 12 08:44:01 AM UTC 24 Oct 12 08:44:04 AM UTC 24 169644336 ps
T250 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_intercept.3371905665 Oct 12 08:44:03 AM UTC 24 Oct 12 08:44:09 AM UTC 24 101379377 ps
T102 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_flash_and_tpm.3489238573 Oct 12 08:43:03 AM UTC 24 Oct 12 08:44:10 AM UTC 24 4827654204 ps
T383 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_tpm_all.4044045100 Oct 12 08:43:58 AM UTC 24 Oct 12 08:44:11 AM UTC 24 4027453540 ps
T58 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_pass_cmd_filtering.3762195740 Oct 12 08:44:02 AM UTC 24 Oct 12 08:44:12 AM UTC 24 1129807787 ps
T227 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_upload.586440411 Oct 12 08:44:05 AM UTC 24 Oct 12 08:44:13 AM UTC 24 1410036790 ps
T198 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_cfg_cmd.2641657238 Oct 12 08:44:10 AM UTC 24 Oct 12 08:44:16 AM UTC 24 103120263 ps
T60 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_pass_addr_payload_swap.1602876564 Oct 12 08:44:02 AM UTC 24 Oct 12 08:44:23 AM UTC 24 6883434411 ps
T159 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_flash_mode.571726056 Oct 12 08:44:11 AM UTC 24 Oct 12 08:44:26 AM UTC 24 3583624188 ps
T416 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_alert_test.1768050052 Oct 12 08:44:25 AM UTC 24 Oct 12 08:44:27 AM UTC 24 146907147 ps
T100 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_tpm_all.1358636390 Oct 12 08:43:16 AM UTC 24 Oct 12 08:44:28 AM UTC 24 48707815312 ps
T160 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_read_buffer_direct.2153631862 Oct 12 08:44:13 AM UTC 24 Oct 12 08:44:28 AM UTC 24 1006404147 ps
T417 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_csb_read.1200053160 Oct 12 08:44:26 AM UTC 24 Oct 12 08:44:28 AM UTC 24 18234721 ps
T223 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_upload.14769273 Oct 12 08:44:35 AM UTC 24 Oct 12 08:45:04 AM UTC 24 15897833182 ps
T56 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_flash_all.1198471655 Oct 12 08:43:00 AM UTC 24 Oct 12 08:44:31 AM UTC 24 29039242698 ps
T418 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_tpm_sts_read.275330890 Oct 12 08:44:29 AM UTC 24 Oct 12 08:44:32 AM UTC 24 350545513 ps
T370 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_flash_and_tpm.1623212775 Oct 12 08:44:17 AM UTC 24 Oct 12 08:44:33 AM UTC 24 1762457053 ps
T379 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_tpm_rw.2325983212 Oct 12 08:44:32 AM UTC 24 Oct 12 08:44:34 AM UTC 24 232749466 ps
T419 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_tpm_read_hw_reg.79245360 Oct 12 08:44:29 AM UTC 24 Oct 12 08:44:34 AM UTC 24 289258748 ps
T175 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_flash_and_tpm_min_idle.377857314 Oct 12 08:40:05 AM UTC 24 Oct 12 08:44:37 AM UTC 24 48188106108 ps
T61 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_pass_addr_payload_swap.3919886148 Oct 12 08:44:33 AM UTC 24 Oct 12 08:44:39 AM UTC 24 354057213 ps
T199 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_cfg_cmd.2020038357 Oct 12 08:44:36 AM UTC 24 Oct 12 08:44:49 AM UTC 24 361575996 ps
T228 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_intercept.3195377521 Oct 12 08:44:34 AM UTC 24 Oct 12 08:44:51 AM UTC 24 2939372280 ps
T298 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_mailbox.2394020346 Oct 12 08:44:35 AM UTC 24 Oct 12 08:44:52 AM UTC 24 1331062338 ps
T299 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_pass_cmd_filtering.2500698445 Oct 12 08:44:32 AM UTC 24 Oct 12 08:44:52 AM UTC 24 31103547555 ps
T420 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_read_buffer_direct.565051537 Oct 12 08:44:49 AM UTC 24 Oct 12 08:44:56 AM UTC 24 85635266 ps
T421 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_alert_test.3217166262 Oct 12 08:44:57 AM UTC 24 Oct 12 08:44:59 AM UTC 24 14248791 ps
T305 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_mailbox.4145076136 Oct 12 08:42:40 AM UTC 24 Oct 12 08:44:59 AM UTC 24 42777459979 ps
T300 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_mailbox.3901098892 Oct 12 08:44:03 AM UTC 24 Oct 12 08:45:01 AM UTC 24 18096425207 ps
T182 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_flash_all.339940772 Oct 12 08:44:15 AM UTC 24 Oct 12 08:45:02 AM UTC 24 16619328505 ps
T393 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_tpm_rw.1482964702 Oct 12 08:45:03 AM UTC 24 Oct 12 08:45:07 AM UTC 24 980070973 ps
T422 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_csb_read.246971523 Oct 12 08:45:00 AM UTC 24 Oct 12 08:45:02 AM UTC 24 36963389 ps
T423 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_tpm_sts_read.4082357658 Oct 12 08:45:03 AM UTC 24 Oct 12 08:45:06 AM UTC 24 77861077 ps
T176 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_flash_and_tpm_min_idle.1488421533 Oct 12 08:43:03 AM UTC 24 Oct 12 08:45:05 AM UTC 24 117983032870 ps
T369 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_tpm_all.2537187544 Oct 12 08:44:29 AM UTC 24 Oct 12 08:45:13 AM UTC 24 7445720058 ps
T294 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_pass_cmd_filtering.3413973522 Oct 12 08:45:04 AM UTC 24 Oct 12 08:45:13 AM UTC 24 11504503187 ps
T62 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_pass_addr_payload_swap.3644934110 Oct 12 08:45:06 AM UTC 24 Oct 12 08:45:14 AM UTC 24 4493111867 ps
T324 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_intercept.596352583 Oct 12 08:45:07 AM UTC 24 Oct 12 08:45:16 AM UTC 24 2216890879 ps
T359 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_flash_mode.61703290 Oct 12 08:44:38 AM UTC 24 Oct 12 08:45:19 AM UTC 24 1876818480 ps
T277 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_cfg_cmd.2182513498 Oct 12 08:45:14 AM UTC 24 Oct 12 08:45:20 AM UTC 24 134240611 ps
T301 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_upload.3386236710 Oct 12 08:45:14 AM UTC 24 Oct 12 08:45:20 AM UTC 24 183505442 ps
T424 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_read_buffer_direct.458864448 Oct 12 08:45:19 AM UTC 24 Oct 12 08:45:25 AM UTC 24 121966081 ps
T425 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_tpm_read_hw_reg.722463895 Oct 12 08:45:02 AM UTC 24 Oct 12 08:45:26 AM UTC 24 5278855734 ps
T360 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_flash_mode.84262877 Oct 12 08:45:15 AM UTC 24 Oct 12 08:45:27 AM UTC 24 179045624 ps
T68 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_flash_and_tpm.2413344490 Oct 12 08:40:03 AM UTC 24 Oct 12 08:45:28 AM UTC 24 119105571082 ps
T76 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_mailbox.3094325739 Oct 12 08:45:08 AM UTC 24 Oct 12 08:45:29 AM UTC 24 16768873010 ps
T77 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_tpm_all.3673600257 Oct 12 08:45:02 AM UTC 24 Oct 12 08:45:31 AM UTC 24 3534156222 ps
T78 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_alert_test.1096131513 Oct 12 08:45:29 AM UTC 24 Oct 12 08:45:31 AM UTC 24 22513933 ps
T79 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_csb_read.47431110 Oct 12 08:45:29 AM UTC 24 Oct 12 08:45:31 AM UTC 24 19851421 ps
T80 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_tpm_sts_read.4283935580 Oct 12 08:45:32 AM UTC 24 Oct 12 08:45:35 AM UTC 24 272128570 ps
T81 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_tpm_rw.1390158640 Oct 12 08:45:33 AM UTC 24 Oct 12 08:45:35 AM UTC 24 44262869 ps
T57 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_flash_mode_ignore_cmds.3550475851 Oct 12 08:41:41 AM UTC 24 Oct 12 08:45:37 AM UTC 24 176147975091 ps
T82 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_tpm_read_hw_reg.1704768543 Oct 12 08:45:32 AM UTC 24 Oct 12 08:45:38 AM UTC 24 721051724 ps
T83 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_pass_cmd_filtering.2050366648 Oct 12 08:45:35 AM UTC 24 Oct 12 08:45:43 AM UTC 24 555112216 ps
T33 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_stress_all.4207525507 Oct 12 08:43:51 AM UTC 24 Oct 12 08:45:46 AM UTC 24 16832114554 ps
T208 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_flash_all.3101565224 Oct 12 08:42:18 AM UTC 24 Oct 12 08:45:49 AM UTC 24 24845816800 ps
T206 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_intercept.445178097 Oct 12 08:45:39 AM UTC 24 Oct 12 08:45:49 AM UTC 24 536112883 ps
T304 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_cfg_cmd.4109182376 Oct 12 08:45:44 AM UTC 24 Oct 12 08:45:52 AM UTC 24 683478155 ps
T308 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_flash_and_tpm.1923377815 Oct 12 08:44:53 AM UTC 24 Oct 12 08:45:52 AM UTC 24 6354739333 ps
T239 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_pass_addr_payload_swap.1051919614 Oct 12 08:45:36 AM UTC 24 Oct 12 08:45:56 AM UTC 24 1388332772 ps
T426 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_flash_mode.1315924407 Oct 12 08:45:47 AM UTC 24 Oct 12 08:46:02 AM UTC 24 1850997842 ps
T427 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_alert_test.4026315045 Oct 12 08:46:03 AM UTC 24 Oct 12 08:46:05 AM UTC 24 117530349 ps
T428 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_csb_read.4006529671 Oct 12 08:46:06 AM UTC 24 Oct 12 08:46:08 AM UTC 24 92250098 ps
T245 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_flash_all.1045794275 Oct 12 08:45:53 AM UTC 24 Oct 12 08:46:08 AM UTC 24 6809673274 ps
T429 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_read_buffer_direct.3711962474 Oct 12 08:45:50 AM UTC 24 Oct 12 08:46:09 AM UTC 24 1297357630 ps
T384 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_flash_and_tpm_min_idle.3168157201 Oct 12 08:45:27 AM UTC 24 Oct 12 08:46:09 AM UTC 24 10463858158 ps
T430 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_tpm_all.708238539 Oct 12 08:46:09 AM UTC 24 Oct 12 08:46:12 AM UTC 24 1903250401 ps
T431 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_tpm_sts_read.1519574847 Oct 12 08:46:10 AM UTC 24 Oct 12 08:46:13 AM UTC 24 62770571 ps
T390 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_tpm_rw.4837955 Oct 12 08:46:10 AM UTC 24 Oct 12 08:46:13 AM UTC 24 135324967 ps
T280 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_mailbox.1689010498 Oct 12 08:45:39 AM UTC 24 Oct 12 08:46:13 AM UTC 24 10644604260 ps
T259 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_intercept.1881275252 Oct 12 08:46:13 AM UTC 24 Oct 12 08:46:22 AM UTC 24 556908226 ps
T372 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_flash_and_tpm_min_idle.190672070 Oct 12 08:45:54 AM UTC 24 Oct 12 08:46:23 AM UTC 24 9530761783 ps
T321 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_pass_addr_payload_swap.1862443212 Oct 12 08:46:13 AM UTC 24 Oct 12 08:46:24 AM UTC 24 1091178943 ps
T432 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_tpm_read_hw_reg.3088699242 Oct 12 08:46:09 AM UTC 24 Oct 12 08:46:24 AM UTC 24 9518687245 ps
T262 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_upload.2235391538 Oct 12 08:46:15 AM UTC 24 Oct 12 08:46:26 AM UTC 24 2200029568 ps
T433 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_cfg_cmd.2385465067 Oct 12 08:46:20 AM UTC 24 Oct 12 08:46:26 AM UTC 24 376643087 ps
T34 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_stress_all.3596808917 Oct 12 08:44:24 AM UTC 24 Oct 12 08:46:27 AM UTC 24 49792823822 ps
T291 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_pass_cmd_filtering.3527350857 Oct 12 08:46:12 AM UTC 24 Oct 12 08:46:28 AM UTC 24 2509851336 ps
T368 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_tpm_all.4233997133 Oct 12 08:45:32 AM UTC 24 Oct 12 08:46:30 AM UTC 24 18926330205 ps
T297 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_mailbox.1242119817 Oct 12 08:46:15 AM UTC 24 Oct 12 08:46:32 AM UTC 24 985672469 ps
T434 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_alert_test.2414820831 Oct 12 08:46:30 AM UTC 24 Oct 12 08:46:32 AM UTC 24 14851768 ps
T435 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_csb_read.1807667441 Oct 12 08:46:31 AM UTC 24 Oct 12 08:46:33 AM UTC 24 20100266 ps
T436 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_tpm_all.918642419 Oct 12 08:46:34 AM UTC 24 Oct 12 08:46:36 AM UTC 24 36925978 ps
T437 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_tpm_sts_read.2377169261 Oct 12 08:46:34 AM UTC 24 Oct 12 08:46:36 AM UTC 24 118485906 ps
T438 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_read_buffer_direct.425199846 Oct 12 08:46:24 AM UTC 24 Oct 12 08:46:37 AM UTC 24 873822269 ps
T365 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_flash_mode.929455296 Oct 12 08:46:23 AM UTC 24 Oct 12 08:46:37 AM UTC 24 924606557 ps
T179 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_flash_and_tpm.1670818593 Oct 12 08:43:45 AM UTC 24 Oct 12 08:46:38 AM UTC 24 20700973717 ps
T439 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_tpm_rw.239409899 Oct 12 08:46:36 AM UTC 24 Oct 12 08:46:38 AM UTC 24 14236605 ps
T195 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_flash_mode_ignore_cmds.1832664755 Oct 12 08:45:17 AM UTC 24 Oct 12 08:46:39 AM UTC 24 11263357778 ps
T306 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_pass_cmd_filtering.2825069862 Oct 12 08:46:37 AM UTC 24 Oct 12 08:46:42 AM UTC 24 1278218816 ps
T178 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_flash_mode_ignore_cmds.2932119012 Oct 12 08:44:40 AM UTC 24 Oct 12 08:46:42 AM UTC 24 7110788861 ps
T318 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_pass_addr_payload_swap.2886311477 Oct 12 08:46:37 AM UTC 24 Oct 12 08:46:43 AM UTC 24 450419089 ps
T217 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_flash_mode_ignore_cmds.4152993410 Oct 12 08:44:11 AM UTC 24 Oct 12 08:46:43 AM UTC 24 16239013430 ps
T440 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_tpm_read_hw_reg.151948192 Oct 12 08:46:33 AM UTC 24 Oct 12 08:46:43 AM UTC 24 2467514885 ps
T104 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_intercept.2441269994 Oct 12 08:46:37 AM UTC 24 Oct 12 08:46:44 AM UTC 24 1051526033 ps
T218 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_flash_and_tpm_min_idle.751155144 Oct 12 08:44:19 AM UTC 24 Oct 12 08:46:46 AM UTC 24 16480980119 ps
T441 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_alert_test.143289492 Oct 12 08:46:45 AM UTC 24 Oct 12 08:46:47 AM UTC 24 40445435 ps
T276 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_upload.3640423044 Oct 12 08:45:40 AM UTC 24 Oct 12 08:46:49 AM UTC 24 20700025311 ps
T442 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_csb_read.3211135384 Oct 12 08:46:47 AM UTC 24 Oct 12 08:46:49 AM UTC 24 67423474 ps
T443 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_flash_all.170498968 Oct 12 08:44:53 AM UTC 24 Oct 12 08:47:05 AM UTC 24 69219697493 ps
T444 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_read_buffer_direct.3866190298 Oct 12 08:46:43 AM UTC 24 Oct 12 08:46:50 AM UTC 24 658620063 ps
T244 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_mailbox.3762475575 Oct 12 08:46:39 AM UTC 24 Oct 12 08:46:50 AM UTC 24 1502986093 ps
T445 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_cfg_cmd.3816039765 Oct 12 08:46:40 AM UTC 24 Oct 12 08:46:51 AM UTC 24 1766012784 ps
T446 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_tpm_rw.2651233095 Oct 12 08:46:51 AM UTC 24 Oct 12 08:46:53 AM UTC 24 56466233 ps
T447 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_tpm_sts_read.421780947 Oct 12 08:46:51 AM UTC 24 Oct 12 08:46:53 AM UTC 24 131978581 ps
T448 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_tpm_read_hw_reg.3647689575 Oct 12 08:46:50 AM UTC 24 Oct 12 08:46:56 AM UTC 24 1320386909 ps
T309 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_pass_cmd_filtering.260465108 Oct 12 08:46:51 AM UTC 24 Oct 12 08:46:59 AM UTC 24 2182623498 ps
T313 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_pass_addr_payload_swap.2218964054 Oct 12 08:46:52 AM UTC 24 Oct 12 08:47:00 AM UTC 24 154988713 ps
T449 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_cfg_cmd.1131833787 Oct 12 08:47:00 AM UTC 24 Oct 12 08:47:04 AM UTC 24 95371206 ps
T325 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_upload.573456621 Oct 12 08:46:56 AM UTC 24 Oct 12 08:47:06 AM UTC 24 3625745760 ps
T450 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_flash_mode.2782231633 Oct 12 08:46:40 AM UTC 24 Oct 12 08:47:09 AM UTC 24 10560999086 ps
T451 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_intercept.1390184377 Oct 12 08:46:54 AM UTC 24 Oct 12 08:47:10 AM UTC 24 1106807032 ps
T452 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_flash_mode.1335900201 Oct 12 08:47:01 AM UTC 24 Oct 12 08:47:14 AM UTC 24 261749990 ps
T207 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_flash_all.2551365105 Oct 12 08:43:39 AM UTC 24 Oct 12 08:47:15 AM UTC 24 100569320818 ps
T453 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_alert_test.372009827 Oct 12 08:47:15 AM UTC 24 Oct 12 08:47:17 AM UTC 24 95998506 ps
T454 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_csb_read.2862201161 Oct 12 08:47:18 AM UTC 24 Oct 12 08:47:21 AM UTC 24 58783055 ps
T455 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_read_buffer_direct.2121547180 Oct 12 08:47:06 AM UTC 24 Oct 12 08:47:22 AM UTC 24 1361147493 ps
T456 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_tpm_sts_read.835831365 Oct 12 08:47:30 AM UTC 24 Oct 12 08:47:32 AM UTC 24 176291340 ps
T240 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_flash_mode_ignore_cmds.106974597 Oct 12 08:46:41 AM UTC 24 Oct 12 08:47:36 AM UTC 24 12121801023 ps
T373 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_tpm_all.717684105 Oct 12 08:46:50 AM UTC 24 Oct 12 08:47:37 AM UTC 24 2967961344 ps
T457 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_tpm_rw.2906794106 Oct 12 08:47:33 AM UTC 24 Oct 12 08:47:41 AM UTC 24 499201462 ps
T302 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_upload.3916624344 Oct 12 08:46:39 AM UTC 24 Oct 12 08:47:41 AM UTC 24 39167381158 ps
T458 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_tpm_read_hw_reg.2263850515 Oct 12 08:47:23 AM UTC 24 Oct 12 08:47:43 AM UTC 24 5032340177 ps
T319 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_pass_addr_payload_swap.2258464180 Oct 12 08:47:38 AM UTC 24 Oct 12 08:47:44 AM UTC 24 477184440 ps
T166 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_stress_all.1974296232 Oct 12 08:46:44 AM UTC 24 Oct 12 08:47:44 AM UTC 24 14872481077 ps
T225 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_pass_cmd_filtering.388127588 Oct 12 08:47:36 AM UTC 24 Oct 12 08:47:45 AM UTC 24 402806863 ps
T283 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_intercept.2383903544 Oct 12 08:47:42 AM UTC 24 Oct 12 08:47:47 AM UTC 24 270323504 ps
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