Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	34098	1			T8	2		T9	8		T11	2
auto[SpiFlashAddrCfg]	7723	1			T11	2		T12	4		T16	1
auto[SpiFlashAddr3b]	9253	1			T7	6		T16	2		T18	6
auto[SpiFlashAddr4b]	7639	1			T7	2		T8	2		T14	2

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33026

1

T7

8

T8

4

T9

8

auto[1]

25687

1

T11

4

T19

14

T39

81

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30735

1

T7

6

T8

2

T9

8

auto[1]

27978

1

T7

2

T8

2

T12

4

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	38854	1			T7	6		T8	2		T9	8
values[1]	1137	1			T39	4		T22	1		T64	4
values[2]	1443	1			T18	2		T45	4		T39	6
values[3]	1505	1			T7	2		T19	2		T55	2
values[4]	1489	1			T11	2		T44	2		T39	4
values[5]	1462	1			T16	2		T51	2		T44	1
values[6]	1489	1			T16	1		T55	2		T39	15
values[7]	1550	1			T14	2		T18	2		T39	13
values[8]	9784	1			T8	2		T11	2		T12	4

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29844

1

T7

8

T8

4

T9

8

auto[1]

28869

1

T16

3

T44

5

T50

8

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

55362

1

T7

4

T8

4

T9

8

write

3351

1

T7

4

T52

2

T39

24

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

19397

1

T7

2

T9

8

T11

2

valids[0x1]

39316

1

T7

6

T8

4

T11

2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1651	1			T8	2		T19	6		T51	4
internal_process_ops[0x5a]	1524	1			T18	2		T39	7		T22	4
internal_process_ops[0x05]	19920	1			T14	2		T19	2		T52	5
internal_process_ops[0x35]	1605	1			T14	2		T18	2		T39	5
internal_process_ops[0x15]	1654	1			T45	2		T39	8		T22	1
internal_process_ops[0x03]	1078	1			T51	2		T44	1		T45	4
internal_process_ops[0x0b]	1102	1			T7	2		T8	2		T12	4
internal_process_ops[0x3b]	1001	1			T44	1		T39	5		T22	4
internal_process_ops[0x6b]	1137	1			T16	2		T39	10		T22	3
internal_process_ops[0xbb]	1048	1			T19	2		T45	2		T39	6
internal_process_ops[0xeb]	1113	1			T7	2		T16	1		T51	2

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

57145

1

T7

8

T8

4

T9

8

auto[1]

1568

1

T39

18

T42

2

T47

3

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

56283

1

T7

8

T8

4

T9

8

auto[1]

2430

1

T52

2

T55

2

T39

11

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

9197

1

T8

2

T9

8

T14

6

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

6419

1

T11

2

T19

8

T39

11

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

2069

1

T12

4

T45

2

T55

2

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1818

1

T11

2

T19

2

T39

21

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2597

1

T7

2

T18

6

T45

4

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2182

1

T39

24

T22

8

T64

8

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

2099

1

T7

2

T8

2

T14

2

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1815

1

T19

4

T39

12

T22

3

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

104

1

T52

2

T42

1

T177

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

85

1

T39

6

T57

1

T178

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

97

1

T39

2

T53

1

T175

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

87

1

T39

3

T53

1

T60

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

126

1

T22

1

T42

1

T53

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

92

1

T39

1

T57

4

T179

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

101

1

T56

2

T57

1

T33

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

94

1

T39

2

T56

1

T61

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

129

1

T7

4

T39

1

T180

6

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

92

1

T176

1

T57

4

T178

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

117

1

T39

1

T53

4

T176

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

115

1

T39

3

T56

1

T33

4

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

104

1

T39

2

T42

2

T53

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

97

1

T39

1

T42

2

T53

4

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

117

1

T42

1

T53

2

T175

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

91

1

T39

2

T53

1

T59

2

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

10562

1

T47

40

T48

155

T49

211

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

7097

1

T47

14

T48

241

T49

218

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1520

1

T16

1

T44

2

T50

5

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1495

1

T47

11

T48

9

T49

17

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

1868

1

T16

2

T44

1

T50

3

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1735

1

T47

5

T48

28

T49

19

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1440

1

T44

2

T181

1

T47

8

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1449

1

T47

9

T48

20

T49

14

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

113

1

T49

3

T108

1

T95

4

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

105

1

T47

1

T48

2

T49

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

134

1

T47

3

T48

2

T94

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

98

1

T48

1

T94

1

T95

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

114

1

T102

1

T182

3

T68

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

118

1

T49

2

T183

1

T95

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

95

1

T48

4

T49

4

T95

5

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

81

1

T49

1

T183

2

T94

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

88

1

T47

2

T48

2

T32

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

106

1

T48

5

T184

1

T94

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

112

1

T48

3

T49

3

T94

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

112

1

T48

3

T94

4

T95

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

95

1

T48

1

T49

2

T94

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

106

1

T47

2

T48

1

T49

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

137

1

T48

5

T95

2

T102

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

89

1

T48

3

T49

2

T184

2

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	3828	1			T9	8		T14	2		T54	4
auto[0]	values[0]	valids[0x1]	14754	1			T7	6		T8	2		T14	4
auto[0]	values[1]	valids[0x1]	546	1			T39	4		T22	1		T64	4
auto[0]	values[2]	valids[0x0]	515	1			T39	1		T42	6		T107	2
auto[0]	values[2]	valids[0x1]	316	1			T18	2		T45	4		T39	5
auto[0]	values[3]	valids[0x0]	560	1			T7	2		T19	2		T55	2
auto[0]	values[3]	valids[0x1]	364	1			T39	3		T42	2		T185	2
auto[0]	values[4]	valids[0x0]	537	1			T39	2		T22	1		T42	2
auto[0]	values[4]	valids[0x1]	307	1			T11	2		T39	2		T42	1
auto[0]	values[5]	valids[0x0]	538	1			T51	2		T39	4		T22	2
auto[0]	values[5]	valids[0x1]	306	1			T39	1		T22	1		T42	2
auto[0]	values[6]	valids[0x0]	503	1			T39	12		T22	1		T42	2
auto[0]	values[6]	valids[0x1]	317	1			T55	2		T39	3		T22	1
auto[0]	values[7]	valids[0x0]	585	1			T18	2		T39	11		T22	6
auto[0]	values[7]	valids[0x1]	317	1			T14	2		T39	2		T42	3
auto[0]	values[8]	valids[0x0]	3438	1			T11	2		T19	2		T52	2
auto[0]	values[8]	valids[0x1]	2113	1			T8	2		T12	4		T19	2
auto[1]	values[0]	valids[0x0]	4077	1			T47	24		T48	37		T49	57
auto[1]	values[0]	valids[0x1]	16195	1			T47	48		T48	395		T49	407
auto[1]	values[1]	valids[0x1]	591	1			T47	1		T48	12		T49	6
auto[1]	values[2]	valids[0x0]	379	1			T47	3		T48	3		T49	4
auto[1]	values[2]	valids[0x1]	233	1			T48	2		T49	11		T95	2
auto[1]	values[3]	valids[0x0]	330	1			T47	3		T48	9		T49	6
auto[1]	values[3]	valids[0x1]	251	1			T47	2		T48	4		T49	4
auto[1]	values[4]	valids[0x0]	372	1			T48	1		T49	6		T184	1
auto[1]	values[4]	valids[0x1]	273	1			T44	2		T48	3		T49	7
auto[1]	values[5]	valids[0x0]	357	1			T16	2		T44	1		T181	1
auto[1]	values[5]	valids[0x1]	261	1			T48	1		T32	3		T94	9
auto[1]	values[6]	valids[0x0]	434	1			T16	1		T48	9		T49	3
auto[1]	values[6]	valids[0x1]	235	1			T48	10		T49	3		T183	2
auto[1]	values[7]	valids[0x0]	365	1			T47	8		T48	2		T94	4
auto[1]	values[7]	valids[0x1]	283	1			T48	2		T49	3		T32	1
auto[1]	values[8]	valids[0x0]	2579	1			T44	1		T50	3		T47	14
auto[1]	values[8]	valids[0x1]	1654	1			T44	1		T50	5		T47	11