Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3362295

1

T7

1

T8

33

T9

8

auto[1]

31267

1

T52

5

T55

45

T39

53

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

860284

1

T7

1

T8

33

T9

8

auto[1]

2533278

1

T14

516

T52

5

T45

8

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	589395	1			T7	1		T8	4		T9	1
auto[524288:1048575]	417582	1			T9	3		T51	1		T113	1
auto[1048576:1572863]	394820	1			T16	2		T51	55		T44	3857
auto[1572864:2097151]	391486	1			T12	410		T39	2851		T63	1
auto[2097152:2621439]	412161	1			T12	1036		T51	162		T45	77
auto[2621440:3145727]	391114	1			T9	4		T12	1		T16	1
auto[3145728:3670015]	425272	1			T8	29		T16	2283		T113	1
auto[3670016:4194303]	371732	1			T12	1		T51	18		T44	2250

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2568687

1

T7

1

T8

7

T9

8

auto[1]

824875

1

T8

26

T12

1873

T16

2414

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2902231

1

T7

1

T8

33

T9

7

auto[1]

491331

1

T9

1

T54

3

T39

11199

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	181821	1			T7	1		T8	4		T11	1
auto[0]	auto[0]	auto[0:524287]	auto[1]	332766	1			T14	516		T52	2		T55	2
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	91741	1			T9	3		T51	1		T113	1
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	261183	1			T39	256		T22	2995		T42	644
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	125756	1			T16	2		T51	55		T44	3857
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	217920	1			T200	4		T47	1		T185	249
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	101184	1			T12	410		T39	44		T63	1
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	228638	1			T39	1		T42	3102		T47	6
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	87677	1			T12	1036		T51	162		T45	77
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	266870	1			T22	2673		T42	2552		T200	1
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	82213	1			T9	4		T12	1		T16	1
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	224243	1			T42	384		T47	786		T48	601
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	99014	1			T8	29		T16	2283		T113	1
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	257770	1			T200	2049		T47	951		T48	262
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	71166	1			T12	1		T51	18		T44	2250
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	246480	1			T45	8		T200	257		T47	1
auto[0]	auto[1]	auto[0:524287]	auto[0]	1622	1			T9	1		T39	36		T63	17
auto[0]	auto[1]	auto[0:524287]	auto[1]	69323	1			T39	2709		T48	132		T49	1
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	1024	1			T54	3		T39	53		T42	48
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	60401	1			T39	256		T42	128		T49	886
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	2708	1			T39	4		T63	14		T103	369
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	43355	1			T48	1		T49	274		T95	256
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	2704	1			T39	16		T42	7		T53	26
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	54911	1			T39	2773		T53	2680		T95	6407
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	1313	1			T39	26		T63	266		T22	4
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	53177	1			T39	2785		T22	13		T49	3
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	2847	1			T39	11		T48	3		T53	22
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	78861	1			T48	518		T53	258		T94	256
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	2603	1			T39	37		T103	1		T49	1
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	62307	1			T39	2475		T49	256		T102	2944
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	659	1			T39	3		T42	13		T103	2
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	48038	1			T48	258		T53	5953		T95	2503
auto[1]	auto[0]	auto[0:524287]	auto[0]	455	1			T52	2		T55	2		T39	3
auto[1]	auto[0]	auto[0:524287]	auto[1]	2690	1			T52	3		T55	43		T48	66
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	432	1			T39	12		T22	1		T42	10
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	2194	1			T22	2		T42	126		T47	1
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	466	1			T42	10		T48	1		T49	2
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	4064	1			T48	35		T49	21		T95	41
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	444	1			T39	17		T42	3		T47	5
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	2897	1			T47	2		T48	51		T49	131
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	440	1			T39	3		T42	11		T47	1
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	1815	1			T47	1		T32	1		T95	76
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	465	1			T42	26		T48	2		T53	3
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	1916	1			T48	36		T95	35		T102	63
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	367	1			T39	3		T47	3		T48	3
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	2635	1			T47	2		T48	13		T49	14
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	440	1			T47	1		T48	3		T49	5
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	4069	1			T48	10		T49	61		T53	416
auto[1]	auto[1]	auto[0:524287]	auto[0]	91	1			T39	3		T49	1		T94	12
auto[1]	auto[1]	auto[0:524287]	auto[1]	627	1			T49	5		T94	45		T95	46
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	123	1			T39	12		T42	7		T49	1
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	484	1			T49	4		T195	106		T217	114
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	57	1			T48	1		T68	1		T208	2
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	494	1			T48	30		T68	1		T208	7
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	94	1			T53	16		T34	1		T36	1
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	614	1			T53	256		T34	6		T36	2
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	97	1			T22	1		T49	3		T95	2
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	772	1			T22	1		T49	54		T95	51
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	81	1			T68	1		T34	1		T218	2
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	488	1			T34	40		T218	20		T36	3
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	90	1			T102	1		T57	8		T245	1
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	486	1			T102	16		T245	8		T257	8
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	90	1			T48	2		T53	10		T182	2
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	790	1			T48	18		T53	117		T182	23

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	2062504	1			T7	1		T8	7		T9	7
auto[0]	auto[0]	auto[1]	813938	1			T8	26		T12	1873		T16	2414
auto[0]	auto[1]	auto[0]	475639	1			T9	1		T39	11184		T63	11
auto[0]	auto[1]	auto[1]	10214	1			T54	3		T63	286		T103	681
auto[1]	auto[0]	auto[0]	25190	1			T52	4		T55	44		T39	30
auto[1]	auto[0]	auto[1]	599	1			T52	1		T55	1		T39	8
auto[1]	auto[1]	auto[0]	5354	1			T39	12		T22	2		T42	6
auto[1]	auto[1]	auto[1]	124	1			T39	3		T42	1		T48	1