Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2646750	1			T1	1		T2	1		T3	1
all_pins[1]	2646750	1			T1	1		T2	1		T3	1
all_pins[2]	2646750	1			T1	1		T2	1		T3	1
all_pins[3]	2646750	1			T1	1		T2	1		T3	1
all_pins[4]	2646750	1			T1	1		T2	1		T3	1
all_pins[5]	2646750	1			T1	1		T2	1		T3	1
all_pins[6]	2646750	1			T1	1		T2	1		T3	1
all_pins[7]	2646750	1			T1	1		T2	1		T3	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	21061254	1			T1	8		T2	8		T3	8
values[0x1]	112746	1			T20	16		T22	20		T89	22
transitions[0x0=>0x1]	111274	1			T20	11		T22	15		T89	13
transitions[0x1=>0x0]	111282	1			T20	11		T22	15		T89	13

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2645897	1			T1	1		T2	1		T3	1
all_pins[0]	values[0x1]	853	1			T20	3		T22	3		T89	4
all_pins[0]	transitions[0x0=>0x1]	698	1			T20	3		T22	2		T89	3
all_pins[0]	transitions[0x1=>0x0]	146	1			T22	4		T32	8		T34	4
all_pins[1]	values[0x0]	2646449	1			T1	1		T2	1		T3	1
all_pins[1]	values[0x1]	301	1			T22	5		T89	1		T32	8
all_pins[1]	transitions[0x0=>0x1]	150	1			T22	2		T32	5		T34	2
all_pins[1]	transitions[0x1=>0x0]	176	1			T20	1		T22	1		T89	1
all_pins[2]	values[0x0]	2646423	1			T1	1		T2	1		T3	1
all_pins[2]	values[0x1]	327	1			T20	1		T22	4		T89	2
all_pins[2]	transitions[0x0=>0x1]	276	1			T20	1		T22	4		T89	2
all_pins[2]	transitions[0x1=>0x0]	144	1			T20	3		T22	1		T89	2
all_pins[3]	values[0x0]	2646555	1			T1	1		T2	1		T3	1
all_pins[3]	values[0x1]	195	1			T20	3		T22	1		T89	2
all_pins[3]	transitions[0x0=>0x1]	129	1			T89	2		T32	5		T166	4
all_pins[3]	transitions[0x1=>0x0]	114	1			T20	1		T22	3		T34	1
all_pins[4]	values[0x0]	2646570	1			T1	1		T2	1		T3	1
all_pins[4]	values[0x1]	180	1			T20	4		T22	4		T34	1
all_pins[4]	transitions[0x0=>0x1]	141	1			T20	3		T22	4		T34	1
all_pins[4]	transitions[0x1=>0x0]	1218	1			T20	1		T89	3		T32	5
all_pins[5]	values[0x0]	2645493	1			T1	1		T2	1		T3	1
all_pins[5]	values[0x1]	1257	1			T20	2		T89	3		T32	5
all_pins[5]	transitions[0x0=>0x1]	373	1			T20	2		T89	2		T32	4
all_pins[5]	transitions[0x1=>0x0]	108557	1			T22	2		T89	3		T32	2
all_pins[6]	values[0x0]	2537309	1			T1	1		T2	1		T3	1
all_pins[6]	values[0x1]	109441	1			T22	2		T89	4		T32	3
all_pins[6]	transitions[0x0=>0x1]	109375	1			T22	2		T32	2		T34	3
all_pins[6]	transitions[0x1=>0x0]	126	1			T20	3		T22	1		T89	2
all_pins[7]	values[0x0]	2646558	1			T1	1		T2	1		T3	1
all_pins[7]	values[0x1]	192	1			T20	3		T22	1		T89	6
all_pins[7]	transitions[0x0=>0x1]	132	1			T20	2		T22	1		T89	4
all_pins[7]	transitions[0x1=>0x0]	801	1			T20	2		T22	3		T89	2