Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16791

1

T7

8

T8

4

T9

8

auto[1]

13053

1

T11

4

T19

14

T39

81

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3966	1			T54	4		T39	20		T231	6
values[1]	3522	1			T45	16		T39	40		T42	20
values[2]	3653	1			T11	4		T52	9		T39	80
values[3]	3504	1			T39	20		T177	12		T272	2
values[4]	4188	1			T8	4		T51	8		T67	4
values[5]	3635	1			T9	8		T42	40		T261	2
values[6]	3776	1			T39	20		T201	16		T185	14
values[7]	3600	1			T7	8		T12	4		T14	8

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3719	1			T12	4		T52	9		T39	20
values[1]	3821	1			T7	8		T39	20		T272	2
values[2]	3218	1			T9	8		T42	20		T177	12
values[3]	2861	1			T8	4		T14	8		T39	60
values[4]	4566	1			T19	14		T51	8		T55	51
values[5]	3489	1			T11	4		T18	8		T54	4
values[6]	3840	1			T67	4		T45	16		T39	40
values[7]	4330	1			T39	40		T22	20		T64	8

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	239	1			T178	7		T217	6		T256	20
auto[0]	values[0]	values[1]	282	1			T57	23		T214	20		T273	93
auto[0]	values[0]	values[2]	158	1			T178	23		T274	4		T229	27
auto[0]	values[0]	values[3]	226	1			T228	20		T217	8		T275	4
auto[0]	values[0]	values[4]	245	1			T56	12		T276	49		T166	10
auto[0]	values[0]	values[5]	330	1			T54	4		T204	18		T277	12
auto[0]	values[0]	values[6]	310	1			T231	6		T57	14		T226	10
auto[0]	values[0]	values[7]	289	1			T39	11		T56	24		T217	13
auto[0]	values[1]	values[0]	227	1			T263	16		T278	8		T279	10
auto[0]	values[1]	values[1]	265	1			T39	10		T33	10		T280	14
auto[0]	values[1]	values[2]	332	1			T42	18		T175	13		T263	13
auto[0]	values[1]	values[3]	118	1			T39	9		T72	13		T281	17
auto[0]	values[1]	values[4]	408	1			T58	4		T57	10		T282	6
auto[0]	values[1]	values[5]	185	1			T33	12		T283	4		T36	13
auto[0]	values[1]	values[6]	260	1			T45	16		T284	12		T217	11
auto[0]	values[1]	values[7]	311	1			T227	12		T285	9		T213	9
auto[0]	values[2]	values[0]	339	1			T52	9		T39	18		T22	14
auto[0]	values[2]	values[1]	268	1			T53	14		T216	18		T202	12
auto[0]	values[2]	values[2]	131	1			T36	14		T237	7		T72	13
auto[0]	values[2]	values[3]	131	1			T39	13		T175	14		T33	7
auto[0]	values[2]	values[4]	248	1			T53	9		T226	12		T137	14
auto[0]	values[2]	values[5]	280	1			T175	17		T166	13		T286	8
auto[0]	values[2]	values[6]	293	1			T39	16		T57	13		T287	6
auto[0]	values[2]	values[7]	234	1			T39	16		T288	24		T289	8
auto[0]	values[3]	values[0]	209	1			T57	15		T262	8		T226	14
auto[0]	values[3]	values[1]	223	1			T272	2		T33	14		T290	12
auto[0]	values[3]	values[2]	218	1			T177	12		T197	2		T226	10
auto[0]	values[3]	values[3]	240	1			T39	14		T178	16		T226	9
auto[0]	values[3]	values[4]	460	1			T33	49		T166	15		T70	23
auto[0]	values[3]	values[5]	199	1			T291	6		T36	12		T226	10
auto[0]	values[3]	values[6]	204	1			T224	24		T217	5		T213	9
auto[0]	values[3]	values[7]	349	1			T206	4		T217	10		T207	83
auto[0]	values[4]	values[0]	282	1			T292	10		T70	15		T238	69
auto[0]	values[4]	values[1]	366	1			T293	8		T269	12		T229	17
auto[0]	values[4]	values[2]	328	1			T198	18		T294	4		T57	19
auto[0]	values[4]	values[3]	184	1			T8	4		T42	14		T53	14
auto[0]	values[4]	values[4]	431	1			T51	8		T39	7		T200	8
auto[0]	values[4]	values[5]	241	1			T39	15		T176	11		T229	13
auto[0]	values[4]	values[6]	305	1			T67	4		T295	4		T244	10
auto[0]	values[4]	values[7]	278	1			T22	12		T42	12		T296	14
auto[0]	values[5]	values[0]	347	1			T42	8		T261	2		T178	12
auto[0]	values[5]	values[1]	169	1			T199	8		T259	4		T263	13
auto[0]	values[5]	values[2]	301	1			T9	8		T53	10		T70	13
auto[0]	values[5]	values[3]	262	1			T103	14		T263	17		T213	9
auto[0]	values[5]	values[4]	320	1			T42	10		T211	22		T53	7
auto[0]	values[5]	values[5]	173	1			T223	51		T57	13		T297	4
auto[0]	values[5]	values[6]	248	1			T298	8		T179	11		T36	6
auto[0]	values[5]	values[7]	207	1			T217	29		T207	9		T36	8
auto[0]	values[6]	values[0]	96	1			T56	8		T213	8		T137	15
auto[0]	values[6]	values[1]	354	1			T53	8		T299	22		T217	17
auto[0]	values[6]	values[2]	263	1			T175	11		T300	8		T57	16
auto[0]	values[6]	values[3]	297	1			T76	2		T243	16		T229	10
auto[0]	values[6]	values[4]	262	1			T176	13		T301	14		T302	39
auto[0]	values[6]	values[5]	229	1			T53	14		T36	11		T303	2
auto[0]	values[6]	values[6]	254	1			T39	10		T304	12		T104	4
auto[0]	values[6]	values[7]	366	1			T185	14		T180	14		T305	2
auto[0]	values[7]	values[0]	267	1			T12	4		T63	8		T57	10
auto[0]	values[7]	values[1]	199	1			T7	8		T306	4		T230	13
auto[0]	values[7]	values[2]	310	1			T33	11		T263	11		T213	9
auto[0]	values[7]	values[3]	220	1			T14	8		T265	14		T250	6
auto[0]	values[7]	values[4]	292	1			T55	51		T229	19		T307	12
auto[0]	values[7]	values[5]	176	1			T18	8		T232	4		T308	15
auto[0]	values[7]	values[6]	297	1			T22	18		T42	15		T57	14
auto[0]	values[7]	values[7]	256	1			T42	23		T56	12		T309	16
auto[1]	values[0]	values[0]	164	1			T178	13		T217	14		T70	44
auto[1]	values[0]	values[1]	106	1			T57	17		T273	9		T310	8
auto[1]	values[0]	values[2]	81	1			T178	17		T229	5		T311	20
auto[1]	values[0]	values[3]	162	1			T217	12		T312	13		T72	12
auto[1]	values[0]	values[4]	340	1			T56	55		T166	73		T273	10
auto[1]	values[0]	values[5]	259	1			T33	5		T307	18		T137	99
auto[1]	values[0]	values[6]	372	1			T57	6		T226	85		T263	10
auto[1]	values[0]	values[7]	403	1			T39	9		T56	26		T217	7
auto[1]	values[1]	values[0]	188	1			T263	8		T279	10		T273	13
auto[1]	values[1]	values[1]	331	1			T39	10		T33	33		T240	7
auto[1]	values[1]	values[2]	178	1			T42	2		T175	7		T313	12
auto[1]	values[1]	values[3]	107	1			T39	11		T72	7		T281	3
auto[1]	values[1]	values[4]	97	1			T57	10		T137	7		T238	8
auto[1]	values[1]	values[5]	163	1			T33	12		T36	22		T289	5
auto[1]	values[1]	values[6]	125	1			T217	9		T263	7		T213	4
auto[1]	values[1]	values[7]	227	1			T285	24		T213	11		T205	11
auto[1]	values[2]	values[0]	203	1			T39	2		T22	9		T226	14
auto[1]	values[2]	values[1]	233	1			T53	6		T62	14		T202	8
auto[1]	values[2]	values[2]	103	1			T36	6		T237	13		T72	7
auto[1]	values[2]	values[3]	204	1			T39	7		T175	6		T33	13
auto[1]	values[2]	values[4]	237	1			T53	11		T226	15		T137	63
auto[1]	values[2]	values[5]	332	1			T11	4		T175	3		T166	15
auto[1]	values[2]	values[6]	141	1			T39	4		T57	7		T268	15
auto[1]	values[2]	values[7]	276	1			T39	4		T288	13		T314	8
auto[1]	values[3]	values[0]	144	1			T57	5		T226	10		T315	10
auto[1]	values[3]	values[1]	117	1			T60	20		T33	6		T273	10
auto[1]	values[3]	values[2]	149	1			T226	10		T70	10		T229	6
auto[1]	values[3]	values[3]	170	1			T39	6		T239	24		T178	4
auto[1]	values[3]	values[4]	328	1			T33	14		T166	5		T70	8
auto[1]	values[3]	values[5]	154	1			T36	13		T226	14		T70	10
auto[1]	values[3]	values[6]	128	1			T217	15		T213	11		T316	8
auto[1]	values[3]	values[7]	212	1			T217	10		T207	46		T268	9
auto[1]	values[4]	values[0]	194	1			T70	5		T238	12		T317	6
auto[1]	values[4]	values[1]	311	1			T234	20		T59	16		T318	2
auto[1]	values[4]	values[2]	242	1			T57	21		T226	9		T237	9
auto[1]	values[4]	values[3]	145	1			T42	6		T53	6		T217	7
auto[1]	values[4]	values[4]	219	1			T39	13		T175	7		T33	3
auto[1]	values[4]	values[5]	269	1			T39	5		T176	16		T229	21
auto[1]	values[4]	values[6]	165	1			T229	13		T72	11		T251	39
auto[1]	values[4]	values[7]	228	1			T22	8		T64	8		T42	8
auto[1]	values[5]	values[0]	390	1			T42	12		T178	8		T207	50
auto[1]	values[5]	values[1]	192	1			T319	2		T263	7		T237	15
auto[1]	values[5]	values[2]	98	1			T53	10		T70	7		T203	3
auto[1]	values[5]	values[3]	137	1			T263	20		T213	11		T233	4
auto[1]	values[5]	values[4]	337	1			T42	10		T53	13		T226	22
auto[1]	values[5]	values[5]	114	1			T57	7		T178	15		T207	5
auto[1]	values[5]	values[6]	185	1			T179	9		T36	26		T288	9
auto[1]	values[5]	values[7]	155	1			T217	11		T207	27		T36	12
auto[1]	values[6]	values[0]	241	1			T56	105		T61	6		T213	12
auto[1]	values[6]	values[1]	309	1			T53	12		T217	3		T207	5
auto[1]	values[6]	values[2]	128	1			T175	27		T57	4		T217	4
auto[1]	values[6]	values[3]	114	1			T107	14		T229	12		T202	6
auto[1]	values[6]	values[4]	132	1			T176	8		T226	5		T229	11
auto[1]	values[6]	values[5]	135	1			T53	6		T36	12		T237	8
auto[1]	values[6]	values[6]	292	1			T39	10		T166	38		T320	18
auto[1]	values[6]	values[7]	304	1			T201	16		T217	13		T70	20
auto[1]	values[7]	values[0]	189	1			T57	10		T226	9		T138	9
auto[1]	values[7]	values[1]	96	1			T230	17		T233	7		T311	22
auto[1]	values[7]	values[2]	198	1			T33	9		T263	9		T213	11
auto[1]	values[7]	values[3]	144	1			T178	13		T263	8		T268	13
auto[1]	values[7]	values[4]	210	1			T19	14		T229	1		T307	8
auto[1]	values[7]	values[5]	250	1			T308	7		T36	14		T230	19
auto[1]	values[7]	values[6]	261	1			T22	4		T42	5		T57	6
auto[1]	values[7]	values[7]	235	1			T42	17		T56	8		T321	20