Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	445	1			T8	2		T39	7		T22	6
auto[ReadAddrCrossIntoMailbox]	278	1			T12	2		T39	6		T42	1
auto[ReadAddrCrossOutOfMailbox]	284	1			T39	3		T22	1		T42	1
auto[ReadAddrCrossAllMailbox]	248	1			T39	3		T22	2		T42	1
auto[ReadAddrOutsideMailbox]	3581	1			T7	4		T12	2		T18	2

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2340

1

T7

2

T8

1

T12

2

auto[1]

2496

1

T7

2

T8

1

T12

2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	809	1			T51	2		T45	4		T39	12
read_ops[0x0b]	838	1			T7	2		T8	2		T12	4
read_ops[0x3b]	760	1			T39	5		T22	4		T42	2
read_ops[0x6b]	831	1			T39	10		T22	3		T42	5
read_ops[0xbb]	762	1			T19	2		T45	2		T39	6
read_ops[0xeb]	836	1			T7	2		T51	2		T45	4

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	41	1			T22	1		T42	1		T56	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	41	1			T39	1		T57	1		T33	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	21	1			T39	2		T42	1		T178	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	19	1			T217	1		T207	1		T263	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	19	1			T244	1		T292	1		T137	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	25	1			T175	1		T33	1		T244	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	14	1			T240	1		T263	1		T322	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	24	1			T57	2		T178	1		T240	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	271	1			T51	1		T45	2		T39	4
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	334	1			T51	1		T45	2		T39	5
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	40	1			T8	1		T22	1		T42	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	39	1			T8	1		T185	2		T33	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	21	1			T12	1		T36	1		T230	2
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	21	1			T12	1		T39	1		T57	2
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	28	1			T39	1		T175	1		T33	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	31	1			T56	2		T57	1		T217	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	22	1			T39	1		T323	1		T233	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	21	1			T56	1		T57	1		T323	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	324	1			T7	1		T12	1		T18	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	291	1			T7	1		T12	1		T18	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	42	1			T39	1		T265	1		T175	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	28	1			T22	4		T265	1		T56	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	19	1			T33	1		T70	1		T285	2
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	32	1			T33	1		T217	1		T240	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	21	1			T39	1		T56	1		T175	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	23	1			T42	1		T33	1		T244	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	14	1			T226	1		T285	1		T137	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	21	1			T226	1		T70	1		T307	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	286	1			T39	2		T177	1		T107	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	274	1			T39	1		T42	1		T177	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	40	1			T39	1		T178	2		T104	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	41	1			T39	1		T42	1		T33	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	26	1			T175	1		T244	2		T226	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	35	1			T39	3		T53	1		T244	2
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	19	1			T70	3		T273	1		T72	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	25	1			T57	1		T217	1		T207	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	21	1			T22	1		T244	1		T36	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	23	1			T244	1		T205	1		T322	2
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	308	1			T39	1		T42	3		T261	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	293	1			T39	4		T22	2		T42	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	39	1			T185	2		T175	1		T228	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	36	1			T39	1		T185	2		T228	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	21	1			T57	1		T226	1		T323	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	18	1			T178	1		T226	1		T323	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	18	1			T57	1		T178	1		T322	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	18	1			T39	1		T179	1		T70	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	18	1			T175	1		T243	1		T202	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	25	1			T22	1		T42	1		T166	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	266	1			T19	1		T45	1		T39	4
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	303	1			T19	1		T45	1		T22	2
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	27	1			T176	1		T324	1		T57	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	31	1			T39	2		T324	1		T70	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	17	1			T175	1		T229	1		T307	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	28	1			T36	1		T237	1		T213	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	24	1			T22	1		T57	1		T226	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	33	1			T178	2		T166	1		T292	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	25	1			T39	1		T57	1		T217	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	20	1			T39	1		T178	1		T226	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	288	1			T7	1		T51	1		T45	2
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	343	1			T7	1		T51	1		T45	2