Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4042	1			T39	80		T63	8		T231	6
values[1]	3915	1			T7	8		T8	4		T9	8
values[2]	3526	1			T11	4		T12	4		T18	8
values[3]	3815	1			T14	8		T54	4		T45	16
values[4]	3289	1			T42	60		T284	12		T185	14
values[5]	3753	1			T22	23		T53	20		T227	12
values[6]	3697	1			T52	9		T67	4		T39	20
values[7]	3807	1			T51	8		T39	20		T64	8

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4254	1			T18	8		T45	16		T39	40
values[1]	3213	1			T7	8		T39	20		T63	8
values[2]	3918	1			T39	20		T22	20		T42	20
values[3]	3723	1			T9	8		T12	4		T54	4
values[4]	3343	1			T14	8		T19	14		T67	4
values[5]	4108	1			T55	51		T39	20		T42	20
values[6]	3594	1			T8	4		T11	4		T39	60
values[7]	3691	1			T51	8		T52	9		T22	45

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29091

1

T7

8

T8

4

T9

8

auto[1]

753

1

T39

18

T42

2

T53

6

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	668	1			T231	6		T175	40		T308	21
auto[0]	values[0]	values[1]	588	1			T39	19		T63	8		T293	8
auto[0]	values[0]	values[2]	685	1			T39	20		T180	14		T58	4
auto[0]	values[0]	values[3]	498	1			T56	29		T283	4		T320	18
auto[0]	values[0]	values[4]	299	1			T217	20		T314	8		T237	19
auto[0]	values[0]	values[5]	344	1			T204	18		T229	31		T279	108
auto[0]	values[0]	values[6]	431	1			T39	35		T232	4		T175	21
auto[0]	values[0]	values[7]	419	1			T53	20		T305	2		T217	18
auto[0]	values[1]	values[0]	868	1			T42	20		T107	14		T57	14
auto[0]	values[1]	values[1]	355	1			T7	8		T60	18		T206	4
auto[0]	values[1]	values[2]	315	1			T207	44		T213	40		T273	60
auto[0]	values[1]	values[3]	363	1			T9	8		T39	18		T325	16
auto[0]	values[1]	values[4]	379	1			T261	2		T57	20		T214	20
auto[0]	values[1]	values[5]	474	1			T215	16		T285	57		T213	19
auto[0]	values[1]	values[6]	455	1			T8	4		T56	20		T239	24
auto[0]	values[1]	values[7]	614	1			T223	51		T62	10		T229	34
auto[0]	values[2]	values[0]	356	1			T18	8		T237	18		T230	55
auto[0]	values[2]	values[1]	166	1			T299	22		T237	37		T326	20
auto[0]	values[2]	values[2]	659	1			T228	20		T297	4		T179	20
auto[0]	values[2]	values[3]	559	1			T12	4		T39	18		T198	18
auto[0]	values[2]	values[4]	270	1			T19	14		T39	20		T42	20
auto[0]	values[2]	values[5]	511	1			T55	51		T39	15		T57	20
auto[0]	values[2]	values[6]	443	1			T11	4		T199	8		T229	27
auto[0]	values[2]	values[7]	495	1			T53	20		T259	4		T104	4
auto[0]	values[3]	values[0]	597	1			T45	16		T39	17		T57	19
auto[0]	values[3]	values[1]	379	1			T56	20		T176	20		T288	26
auto[0]	values[3]	values[2]	449	1			T53	19		T324	4		T57	20
auto[0]	values[3]	values[3]	569	1			T54	4		T53	19		T175	20
auto[0]	values[3]	values[4]	505	1			T14	8		T42	20		T59	14
auto[0]	values[3]	values[5]	471	1			T201	16		T280	14		T276	49
auto[0]	values[3]	values[6]	391	1			T42	19		T234	20		T33	20
auto[0]	values[3]	values[7]	362	1			T56	67		T315	10		T237	74
auto[0]	values[4]	values[0]	306	1			T272	2		T53	19		T57	19
auto[0]	values[4]	values[1]	365	1			T284	12		T185	14		T226	20
auto[0]	values[4]	values[2]	580	1			T42	20		T224	24		T226	57
auto[0]	values[4]	values[3]	247	1			T57	18		T274	4		T327	8
auto[0]	values[4]	values[4]	455	1			T42	20		T250	6		T229	21
auto[0]	values[4]	values[5]	674	1			T57	18		T178	18		T36	31
auto[0]	values[4]	values[6]	235	1			T291	6		T226	24		T216	18
auto[0]	values[4]	values[7]	331	1			T42	19		T70	21		T328	6
auto[0]	values[5]	values[0]	375	1			T178	20		T105	16		T237	63
auto[0]	values[5]	values[1]	456	1			T301	14		T179	19		T226	18
auto[0]	values[5]	values[2]	372	1			T36	19		T233	44		T273	66
auto[0]	values[5]	values[3]	441	1			T203	20		T205	78		T137	32
auto[0]	values[5]	values[4]	461	1			T227	12		T72	71		T210	20
auto[0]	values[5]	values[5]	571	1			T57	19		T33	63		T217	20
auto[0]	values[5]	values[6]	481	1			T53	17		T294	4		T240	19
auto[0]	values[5]	values[7]	500	1			T22	23		T33	83		T217	20
auto[0]	values[6]	values[0]	533	1			T103	14		T56	112		T318	2
auto[0]	values[6]	values[1]	406	1			T200	8		T298	8		T217	18
auto[0]	values[6]	values[2]	418	1			T22	20		T295	4		T33	20
auto[0]	values[6]	values[3]	337	1			T36	43		T285	26		T213	20
auto[0]	values[6]	values[4]	400	1			T67	4		T36	42		T329	2
auto[0]	values[6]	values[5]	479	1			T226	52		T269	12		T237	68
auto[0]	values[6]	values[6]	577	1			T39	20		T207	83		T263	27
auto[0]	values[6]	values[7]	446	1			T52	9		T22	22		T211	22
auto[0]	values[7]	values[0]	439	1			T39	20		T203	19		T330	20
auto[0]	values[7]	values[1]	410	1			T300	8		T57	20		T178	20
auto[0]	values[7]	values[2]	362	1			T33	60		T217	19		T285	31
auto[0]	values[7]	values[3]	610	1			T177	12		T57	20		T178	20
auto[0]	values[7]	values[4]	497	1			T197	2		T53	20		T309	16
auto[0]	values[7]	values[5]	465	1			T42	20		T61	4		T226	21
auto[0]	values[7]	values[6]	492	1			T64	8		T277	12		T166	68
auto[0]	values[7]	values[7]	433	1			T51	8		T265	14		T304	12
auto[1]	values[0]	values[0]	12	1			T308	1		T273	1		T173	1
auto[1]	values[0]	values[1]	21	1			T39	1		T57	1		T178	2
auto[1]	values[0]	values[2]	13	1			T217	1		T230	1		T38	4
auto[1]	values[0]	values[3]	20	1			T56	1		T213	2		T331	2
auto[1]	values[0]	values[4]	5	1			T237	1		T72	2		T332	2
auto[1]	values[0]	values[5]	13	1			T229	1		T279	3		T238	3
auto[1]	values[0]	values[6]	13	1			T39	5		T333	1		T334	2
auto[1]	values[0]	values[7]	13	1			T217	2		T226	1		T237	1
auto[1]	values[1]	values[0]	19	1			T57	6		T217	1		T166	1
auto[1]	values[1]	values[1]	17	1			T60	2		T321	2		T72	2
auto[1]	values[1]	values[2]	8	1			T207	1		T335	2		T336	3
auto[1]	values[1]	values[3]	10	1			T39	2		T230	1		T247	2
auto[1]	values[1]	values[4]	11	1			T229	1		T307	3		T205	2
auto[1]	values[1]	values[5]	7	1			T213	1		T71	2		T279	3
auto[1]	values[1]	values[6]	8	1			T70	1		T268	3		T326	2
auto[1]	values[1]	values[7]	12	1			T62	4		T337	1		T38	2
auto[1]	values[2]	values[0]	11	1			T237	2		T212	2		T338	1
auto[1]	values[2]	values[1]	7	1			T237	2		T252	5		-	-
auto[1]	values[2]	values[2]	10	1			T179	1		T237	1		T268	1
auto[1]	values[2]	values[3]	13	1			T39	2		T175	1		T217	1
auto[1]	values[2]	values[4]	2	1			T178	1		T339	1		-	-
auto[1]	values[2]	values[5]	15	1			T39	5		T166	3		T233	1
auto[1]	values[2]	values[6]	6	1			T229	1		T72	2		T212	1
auto[1]	values[2]	values[7]	3	1			T340	3		-	-		-	-
auto[1]	values[3]	values[0]	13	1			T39	3		T57	1		T226	1
auto[1]	values[3]	values[1]	6	1			T176	1		T72	1		T171	1
auto[1]	values[3]	values[2]	8	1			T53	1		T137	2		T341	2
auto[1]	values[3]	values[3]	20	1			T53	1		T226	4		T229	2
auto[1]	values[3]	values[4]	14	1			T59	2		T207	4		T322	2
auto[1]	values[3]	values[5]	2	1			T342	1		T343	1		-	-
auto[1]	values[3]	values[6]	14	1			T42	1		T70	3		T202	1
auto[1]	values[3]	values[7]	15	1			T307	2		T344	2		T345	2
auto[1]	values[4]	values[0]	13	1			T53	1		T57	1		T33	2
auto[1]	values[4]	values[1]	5	1			T71	1		T342	2		T346	2
auto[1]	values[4]	values[2]	10	1			T238	2		T322	1		T347	1
auto[1]	values[4]	values[3]	6	1			T57	2		T348	2		T326	2
auto[1]	values[4]	values[4]	9	1			T229	1		T341	1		T222	1
auto[1]	values[4]	values[5]	30	1			T57	2		T178	2		T36	4
auto[1]	values[4]	values[6]	8	1			T247	5		T349	1		T343	1
auto[1]	values[4]	values[7]	15	1			T42	1		T70	1		T328	6
auto[1]	values[5]	values[0]	14	1			T238	1		T171	1		T350	1
auto[1]	values[5]	values[1]	10	1			T179	1		T226	2		T338	1
auto[1]	values[5]	values[2]	10	1			T36	1		T310	1		T72	3
auto[1]	values[5]	values[3]	11	1			T205	1		T351	1		T171	1
auto[1]	values[5]	values[4]	10	1			T311	1		T335	1		T343	1
auto[1]	values[5]	values[5]	7	1			T57	1		T70	1		T171	1
auto[1]	values[5]	values[6]	23	1			T53	3		T240	1		T36	4
auto[1]	values[5]	values[7]	11	1			T33	3		T166	1		T230	2
auto[1]	values[6]	values[0]	17	1			T56	1		T36	5		T279	3
auto[1]	values[6]	values[1]	14	1			T217	2		T70	2		T230	1
auto[1]	values[6]	values[2]	4	1			T70	1		T337	1		T352	1
auto[1]	values[6]	values[3]	7	1			T233	1		T281	1		T353	4
auto[1]	values[6]	values[4]	23	1			T36	1		T311	1		T221	7
auto[1]	values[6]	values[5]	15	1			T226	1		T354	1		T355	1
auto[1]	values[6]	values[6]	10	1			T207	1		T138	2		T311	2
auto[1]	values[6]	values[7]	11	1			T342	1		T356	2		T352	1
auto[1]	values[7]	values[0]	13	1			T203	1		T357	2		T335	2
auto[1]	values[7]	values[1]	8	1			T70	1		T72	2		T348	3
auto[1]	values[7]	values[2]	15	1			T33	3		T217	1		T285	2
auto[1]	values[7]	values[3]	12	1			T289	1		T263	2		T238	2
auto[1]	values[7]	values[4]	3	1			T226	1		T358	2		-	-
auto[1]	values[7]	values[5]	30	1			T61	2		T226	2		T233	1
auto[1]	values[7]	values[6]	7	1			T349	1		T336	2		T354	1
auto[1]	values[7]	values[7]	11	1			T217	3		T238	2		T310	1