Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	874	1			T20	7		T22	10		T89	11
all_values[1]	874	1			T20	7		T22	10		T89	11
all_values[2]	874	1			T20	7		T22	10		T89	11
all_values[3]	874	1			T20	7		T22	10		T89	11
all_values[4]	874	1			T20	7		T22	10		T89	11
all_values[5]	874	1			T20	7		T22	10		T89	11
all_values[6]	874	1			T20	7		T22	10		T89	11
all_values[7]	874	1			T20	7		T22	10		T89	11

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3791

1

T20

31

T22

31

T89

51

auto[1]

3201

1

T20

25

T22

49

T89

37

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2731

1

T20

21

T22

36

T89

31

auto[1]

4261

1

T20

35

T22

44

T89

57

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3926

1

T20

32

T22

47

T89

47

auto[1]

3066

1

T20

24

T22

33

T89

41

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	181	1			T20	1		T89	3		T32	4
all_values[0]	auto[0]	auto[0]	auto[1]	91	1			T22	1		T89	3		T32	3
all_values[0]	auto[0]	auto[1]	auto[0]	138	1			T20	2		T22	5		T32	5
all_values[0]	auto[0]	auto[1]	auto[1]	90	1			T20	1		T89	1		T32	1
all_values[0]	auto[1]	auto[0]	auto[1]	189	1			T20	1		T32	5		T34	3
all_values[0]	auto[1]	auto[1]	auto[1]	185	1			T20	2		T22	4		T89	4
all_values[1]	auto[0]	auto[0]	auto[0]	168	1			T20	5		T22	1		T89	3
all_values[1]	auto[0]	auto[0]	auto[1]	72	1			T22	1		T32	2		T34	1
all_values[1]	auto[0]	auto[1]	auto[0]	163	1			T22	1		T89	1		T32	3
all_values[1]	auto[0]	auto[1]	auto[1]	97	1			T20	1		T22	2		T32	4
all_values[1]	auto[1]	auto[0]	auto[1]	202	1			T20	1		T22	2		T89	5
all_values[1]	auto[1]	auto[1]	auto[1]	172	1			T22	3		T89	2		T32	5
all_values[2]	auto[0]	auto[0]	auto[0]	166	1			T20	2		T89	1		T32	4
all_values[2]	auto[0]	auto[0]	auto[1]	93	1			T20	1		T22	3		T89	3
all_values[2]	auto[0]	auto[1]	auto[0]	144	1			T22	2		T32	1		T166	7
all_values[2]	auto[0]	auto[1]	auto[1]	82	1			T22	1		T89	1		T32	1
all_values[2]	auto[1]	auto[0]	auto[1]	214	1			T20	2		T22	2		T89	4
all_values[2]	auto[1]	auto[1]	auto[1]	175	1			T20	2		T22	2		T89	2
all_values[3]	auto[0]	auto[0]	auto[0]	182	1			T20	1		T22	3		T89	3
all_values[3]	auto[0]	auto[0]	auto[1]	82	1			T22	1		T89	1		T32	3
all_values[3]	auto[0]	auto[1]	auto[0]	154	1			T20	1		T22	1		T89	2
all_values[3]	auto[0]	auto[1]	auto[1]	87	1			T20	2		T22	1		T89	1
all_values[3]	auto[1]	auto[0]	auto[1]	214	1			T20	1		T22	3		T89	3
all_values[3]	auto[1]	auto[1]	auto[1]	155	1			T20	2		T22	1		T89	1
all_values[4]	auto[0]	auto[0]	auto[0]	194	1			T22	1		T89	3		T32	9
all_values[4]	auto[0]	auto[0]	auto[1]	93	1			T20	1		T89	2		T34	1
all_values[4]	auto[0]	auto[1]	auto[0]	143	1			T22	1		T89	2		T32	8
all_values[4]	auto[0]	auto[1]	auto[1]	61	1			T20	1		T22	1		T166	1
all_values[4]	auto[1]	auto[0]	auto[1]	215	1			T20	2		T22	3		T89	3
all_values[4]	auto[1]	auto[1]	auto[1]	168	1			T20	3		T22	4		T89	1
all_values[5]	auto[0]	auto[0]	auto[0]	262	1			T20	4		T22	1		T89	3
all_values[5]	auto[0]	auto[1]	auto[0]	209	1			T20	1		T22	7		T89	2
all_values[5]	auto[1]	auto[0]	auto[1]	215	1			T22	1		T89	4		T32	9
all_values[5]	auto[1]	auto[1]	auto[1]	188	1			T20	2		T22	1		T89	2
all_values[6]	auto[0]	auto[0]	auto[0]	175	1			T20	1		T22	3		T89	3
all_values[6]	auto[0]	auto[0]	auto[1]	84	1			T20	1		T32	3		T166	2
all_values[6]	auto[0]	auto[1]	auto[0]	132	1			T20	1		T22	3		T89	3
all_values[6]	auto[0]	auto[1]	auto[1]	96	1			T89	1		T32	2		T34	3
all_values[6]	auto[1]	auto[0]	auto[1]	207	1			T20	4		T22	1		T89	1
all_values[6]	auto[1]	auto[1]	auto[1]	180	1			T22	3		T89	3		T32	2
all_values[7]	auto[0]	auto[0]	auto[0]	180	1			T20	1		T22	2		T89	1
all_values[7]	auto[0]	auto[0]	auto[1]	91	1			T20	1		T89	1		T32	2
all_values[7]	auto[0]	auto[1]	auto[0]	140	1			T20	1		T22	5		T89	1
all_values[7]	auto[0]	auto[1]	auto[1]	76	1			T20	2		T89	2		T32	3
all_values[7]	auto[1]	auto[0]	auto[1]	221	1			T20	1		T22	2		T89	1
all_values[7]	auto[1]	auto[1]	auto[1]	166	1			T20	1		T22	1		T89	5

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal