Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1713

1

T1

1

T4

1

T5

3

auto[1]

1746

1

T1

2

T4

2

T5

3

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1963

1

T10

12

T25

2

T22

6

auto[1]

1496

1

T1

3

T4

3

T5

6

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2711

1

T1

3

T4

3

T5

6

auto[1]

748

1

T10

5

T25

1

T22

4

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	711	1			T4	3		T5	1		T10	2
valid[1]	655	1			T5	2		T10	6		T24	3
valid[2]	708	1			T1	2		T10	1		T24	3
valid[3]	705	1			T1	1		T5	2		T10	3
valid[4]	680	1			T5	1		T10	3		T24	3

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	127	1			T22	1		T378	1		T383	1
auto[0]	auto[0]	valid[0]	auto[1]	138	1			T4	1		T24	6		T40	1
auto[0]	auto[0]	valid[1]	auto[0]	116	1			T10	1		T47	3		T184	1
auto[0]	auto[0]	valid[1]	auto[1]	136	1			T5	1		T10	1		T24	2
auto[0]	auto[0]	valid[2]	auto[0]	129	1			T25	1		T184	1		T378	1
auto[0]	auto[0]	valid[2]	auto[1]	141	1			T1	1		T24	2		T40	2
auto[0]	auto[0]	valid[3]	auto[0]	118	1			T10	1		T43	1		T47	1
auto[0]	auto[0]	valid[3]	auto[1]	152	1			T5	1		T10	1		T24	3
auto[0]	auto[0]	valid[4]	auto[0]	133	1			T10	1		T47	3		T378	1
auto[0]	auto[0]	valid[4]	auto[1]	140	1			T5	1		T24	2		T40	1
auto[0]	auto[1]	valid[0]	auto[0]	125	1			T22	1		T47	1		T184	1
auto[0]	auto[1]	valid[0]	auto[1]	164	1			T4	2		T5	1		T26	1
auto[0]	auto[1]	valid[1]	auto[0]	102	1			T10	1		T40	1		T47	1
auto[0]	auto[1]	valid[1]	auto[1]	167	1			T5	1		T10	1		T24	1
auto[0]	auto[1]	valid[2]	auto[0]	131	1			T10	1		T40	1		T184	1
auto[0]	auto[1]	valid[2]	auto[1]	152	1			T1	1		T24	1		T40	1
auto[0]	auto[1]	valid[3]	auto[0]	132	1			T10	1		T378	2		T32	1
auto[0]	auto[1]	valid[3]	auto[1]	150	1			T1	1		T5	1		T28	1
auto[0]	auto[1]	valid[4]	auto[0]	102	1			T10	1		T47	3		T378	1
auto[0]	auto[1]	valid[4]	auto[1]	156	1			T24	1		T26	1		T40	1
auto[1]	auto[0]	valid[0]	auto[0]	80	1			T22	2		T47	1		T184	1
auto[1]	auto[0]	valid[1]	auto[0]	70	1			T10	2		T43	1		T47	2
auto[1]	auto[0]	valid[2]	auto[0]	75	1			T40	1		T184	1		T378	1
auto[1]	auto[0]	valid[3]	auto[0]	81	1			T22	1		T47	1		T378	1
auto[1]	auto[0]	valid[4]	auto[0]	77	1			T10	1		T47	1		T100	2
auto[1]	auto[1]	valid[0]	auto[0]	77	1			T10	2		T48	1		T184	2
auto[1]	auto[1]	valid[1]	auto[0]	64	1			T101	1		T184	1		T175	1
auto[1]	auto[1]	valid[2]	auto[0]	80	1			T40	1		T48	2		T101	1
auto[1]	auto[1]	valid[3]	auto[0]	72	1			T25	1		T22	1		T47	1
auto[1]	auto[1]	valid[4]	auto[0]	72	1			T378	1		T383	1		T100	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal