Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

48507

1

T6

6

T10

201

T25

50

auto[1]

15712

1

T1

3

T4

49

T5

6

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

46663

1

T1

3

T4

49

T5

6

auto[1]

17556

1

T6

2

T10

78

T25

15

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	32715	1			T1	3		T4	28		T5	6
others[1]	5539	1			T4	4		T6	1		T10	21
others[2]	5414	1			T4	5		T6	1		T10	20
others[3]	6285	1			T4	5		T10	14		T24	12
interest[1]	3499	1			T4	3		T6	1		T10	8
interest[4]	21388	1			T1	3		T4	22		T5	6
interest[64]	10767	1			T4	4		T6	1		T10	42

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	15655	1			T6	2		T10	70		T25	13
auto[0]	auto[0]	others[1]	2669	1			T6	1		T10	12		T41	1
auto[0]	auto[0]	others[2]	2644	1			T6	1		T10	5		T25	3
auto[0]	auto[0]	others[3]	3044	1			T10	6		T25	8		T22	7
auto[0]	auto[0]	interest[1]	1699	1			T10	3		T25	1		T22	5
auto[0]	auto[0]	interest[4]	10128	1			T6	1		T10	48		T25	8
auto[0]	auto[0]	interest[64]	5240	1			T10	27		T25	10		T27	1
auto[0]	auto[1]	others[0]	8213	1			T1	3		T4	28		T5	6
auto[0]	auto[1]	others[1]	1343	1			T4	4		T10	4		T24	16
auto[0]	auto[1]	others[2]	1306	1			T4	5		T10	4		T24	14
auto[0]	auto[1]	others[3]	1464	1			T4	5		T10	2		T24	12
auto[0]	auto[1]	interest[1]	831	1			T4	3		T10	1		T24	5
auto[0]	auto[1]	interest[4]	5459	1			T1	3		T4	22		T5	6
auto[0]	auto[1]	interest[64]	2555	1			T4	4		T10	4		T24	36
auto[1]	auto[0]	others[0]	8847	1			T10	41		T25	11		T27	1
auto[1]	auto[0]	others[1]	1527	1			T10	5		T22	2		T40	5
auto[1]	auto[0]	others[2]	1464	1			T10	11		T27	1		T41	1
auto[1]	auto[0]	others[3]	1777	1			T10	6		T25	1		T22	3
auto[1]	auto[0]	interest[1]	969	1			T6	1		T10	4		T27	1
auto[1]	auto[0]	interest[4]	5801	1			T10	28		T25	9		T41	3
auto[1]	auto[0]	interest[64]	2972	1			T6	1		T10	11		T25	3

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal