Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3694831

1

T1

45

T2

1

T3

6

full_word

4399746

1

T3

20

T4

873

T5

201

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	8094167	1			T1	45		T2	1		T3	26
auto[TlIntgErrCmd]	140	1			T105	5		T107	1		T106	9
auto[TlIntgErrData]	144	1			T105	6		T107	3		T106	5
auto[TlIntgErrBoth]	126	1			T105	9		T107	6		T106	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4404240

1

T1

45

T2

1

T3

1

auto[1]

3690337

1

T3

25

T4

875

T5

249

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3330707	1			T1	45		T2	1		T3	1
auto[TlIntgErrNone]	partial	auto[1]	363751	1			T3	5		T4	3		T5	48
auto[TlIntgErrNone]	full_word	auto[0]	1073354	1			T4	1		T6	26		T7	199
auto[TlIntgErrNone]	full_word	auto[1]	3326355	1			T3	20		T4	872		T5	201
auto[TlIntgErrCmd]	partial	auto[0]	46	1			T105	2		T107	1		T106	3
auto[TlIntgErrCmd]	partial	auto[1]	76	1			T105	3		T106	3		T188	2
auto[TlIntgErrCmd]	full_word	auto[0]	8	1			T106	1		T184	1		T189	1
auto[TlIntgErrCmd]	full_word	auto[1]	10	1			T106	2		T166	1		T184	1
auto[TlIntgErrData]	partial	auto[0]	71	1			T105	2		T107	3		T106	1
auto[TlIntgErrData]	partial	auto[1]	65	1			T105	3		T106	3		T188	2
auto[TlIntgErrData]	full_word	auto[0]	3	1			T105	1		T183	1		T190	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T106	1		T184	1		T191	2
auto[TlIntgErrBoth]	partial	auto[0]	47	1			T105	2		T107	4		T106	2
auto[TlIntgErrBoth]	partial	auto[1]	68	1			T105	7		T107	2		T106	2
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T106	2		T192	1		T186	1
auto[TlIntgErrBoth]	full_word	auto[1]	7	1			T192	1		T191	2		T189	1