Unified Coverage Report :: Module :: spi_device_csr_assert_fpv

Module : spi_device_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_spi_device_csr_assert_0/spi_device_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.spi_device_csr_assert	100.00						100.00

---

Module Instance : tb.dut.spi_device_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.10	95.20	93.48	97.84		93.55	95.45	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : spi_device_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	58	58	100.00	58	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	58	58	100.00	58	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	455154969	3586	0	0
addr_swap_data_rd_A	455154969	1285	0	0
addr_swap_mask_rd_A	455154969	1348	0	0
cfg_rd_A	455154969	1666	0	0
cmd_filter_0_rd_A	455154969	7332	0	0
cmd_filter_1_rd_A	455154969	8867	0	0
cmd_filter_2_rd_A	455154969	6655	0	0
cmd_filter_3_rd_A	455154969	7765	0	0
cmd_filter_4_rd_A	455154969	6656	0	0
cmd_filter_5_rd_A	455154969	8279	0	0
cmd_filter_6_rd_A	455154969	7207	0	0
cmd_filter_7_rd_A	455154969	6309	0	0
cmd_info_0_rd_A	455154969	3749	0	0
cmd_info_10_rd_A	455154969	3759	0	0
cmd_info_11_rd_A	455154969	3419	0	0
cmd_info_12_rd_A	455154969	3842	0	0
cmd_info_13_rd_A	455154969	3553	0	0
cmd_info_14_rd_A	455154969	3885	0	0
cmd_info_15_rd_A	455154969	3776	0	0
cmd_info_16_rd_A	455154969	3582	0	0
cmd_info_17_rd_A	455154969	3790	0	0
cmd_info_18_rd_A	455154969	3830	0	0
cmd_info_19_rd_A	455154969	3488	0	0
cmd_info_1_rd_A	455154969	4027	0	0
cmd_info_20_rd_A	455154969	3940	0	0
cmd_info_21_rd_A	455154969	3828	0	0
cmd_info_22_rd_A	455154969	3433	0	0
cmd_info_23_rd_A	455154969	3781	0	0
cmd_info_2_rd_A	455154969	3901	0	0
cmd_info_3_rd_A	455154969	3587	0	0
cmd_info_4_rd_A	455154969	3611	0	0
cmd_info_5_rd_A	455154969	3715	0	0
cmd_info_6_rd_A	455154969	3830	0	0
cmd_info_7_rd_A	455154969	3272	0	0
cmd_info_8_rd_A	455154969	3763	0	0
cmd_info_9_rd_A	455154969	3905	0	0
cmd_info_en4b_rd_A	455154969	1480	0	0
cmd_info_ex4b_rd_A	455154969	1557	0	0
cmd_info_wrdi_rd_A	455154969	1578	0	0
cmd_info_wren_rd_A	455154969	1552	0	0
intercept_en_rd_A	455154969	1852	0	0
intr_enable_rd_A	455154969	3453	0	0
jedec_cc_rd_A	455154969	1648	0	0
jedec_id_rd_A	455154969	1655	0	0
mailbox_addr_rd_A	455154969	1391	0	0
payload_swap_data_rd_A	455154969	1299	0	0
payload_swap_mask_rd_A	455154969	1421	0	0
read_threshold_rd_A	455154969	1378	0	0
tpm_access_0_rd_A	455154969	2125	0	0
tpm_access_1_rd_A	455154969	1310	0	0
tpm_cfg_rd_A	455154969	2276	0	0
tpm_did_vid_rd_A	455154969	1545	0	0
tpm_int_enable_rd_A	455154969	1319	0	0
tpm_int_status_rd_A	455154969	1416	0	0
tpm_int_vector_rd_A	455154969	1346	0	0
tpm_intf_capability_rd_A	455154969	1387	0	0
tpm_rid_rd_A	455154969	1430	0	0
tpm_sts_rd_A	455154969	1347	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455154969	3586	0	0
T84	6543	4	0	0
T85	11408	62	0	0
T86	6795	259	0	0
T103	13873	154	0	0
T104	7873	77	0	0
T105	19046	3	0	0
T106	34114	3	0	0
T108	9757	2	0	0
T116	9755	7	0	0
T122	9156	11	0	0

addr_swap_data_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455154969	1285	0	0
T84	6543	7	0	0
T108	9757	2	0	0
T116	9755	8	0	0
T128	10187	14	0	0
T136	39908	236	0	0
T160	19930	16	0	0
T161	13775	8	0	0
T162	6950	5	0	0
T163	11938	10	0	0
T164	5665	16	0	0

addr_swap_mask_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455154969	1348	0	0
T84	6543	5	0	0
T108	9757	5	0	0
T116	9755	3	0	0
T128	10187	3	0	0
T136	39908	244	0	0
T160	19930	18	0	0
T161	13775	34	0	0
T162	6950	18	0	0
T163	11938	25	0	0
T164	5665	8	0	0

cfg_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455154969	1666	0	0
T84	6543	10	0	0
T108	9757	8	0	0
T116	9755	9	0	0
T128	10187	35	0	0
T136	39908	276	0	0
T160	19930	47	0	0
T161	13775	60	0	0
T162	6950	4	0	0
T163	11938	2	0	0
T164	5665	4	0	0

cmd_filter_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455154969	7332	0	0
T84	6543	12	0	0
T108	9757	64	0	0
T116	9755	119	0	0
T128	10187	139	0	0
T136	39908	244	0	0
T160	19930	60	0	0
T161	13775	61	0	0
T162	6950	14	0	0
T163	11938	22	0	0
T164	5665	120	0	0

cmd_filter_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455154969	8867	0	0
T84	6543	13	0	0
T108	9757	140	0	0
T116	9755	108	0	0
T128	10187	122	0	0
T136	39908	208	0	0
T160	19930	41	0	0
T161	13775	12	0	0
T162	6950	7	0	0
T163	11938	19	0	0
T164	5665	9	0	0

cmd_filter_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455154969	6655	0	0
T84	6543	3	0	0
T108	9757	7	0	0
T116	9755	54	0	0
T128	10187	142	0	0
T136	39908	214	0	0
T160	19930	49	0	0
T161	13775	8	0	0
T162	6950	11	0	0
T163	11938	16	0	0
T164	5665	5	0	0

cmd_filter_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455154969	7765	0	0
T84	6543	8	0	0
T108	9757	106	0	0
T116	9755	81	0	0
T128	10187	234	0	0
T136	39908	245	0	0
T160	19930	32	0	0
T161	13775	26	0	0
T162	6950	16	0	0
T163	11938	12	0	0
T165	24525	5	0	0

cmd_filter_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455154969	6656	0	0
T84	6543	94	0	0
T108	9757	67	0	0
T116	9755	90	0	0
T128	10187	10	0	0
T136	39908	234	0	0
T160	19930	66	0	0
T161	13775	44	0	0
T162	6950	19	0	0
T163	11938	16	0	0
T164	5665	9	0	0

cmd_filter_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455154969	8279	0	0
T84	6543	134	0	0
T108	9757	95	0	0
T116	9755	72	0	0
T128	10187	356	0	0
T136	39908	239	0	0
T160	19930	43	0	0
T161	13775	70	0	0
T162	6950	35	0	0
T163	11938	39	0	0
T164	5665	110	0	0

cmd_filter_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455154969	7207	0	0
T84	6543	134	0	0
T108	9757	92	0	0
T116	9755	143	0	0
T128	10187	90	0	0
T136	39908	276	0	0
T160	19930	61	0	0
T161	13775	28	0	0
T162	6950	3	0	0
T163	11938	11	0	0
T164	5665	123	0	0

cmd_filter_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455154969	6309	0	0
T84	6543	112	0	0
T108	9757	55	0	0
T116	9755	10	0	0
T128	10187	279	0	0
T136	39908	254	0	0
T160	19930	48	0	0
T161	13775	27	0	0
T162	6950	19	0	0
T163	11938	37	0	0
T164	5665	7	0	0

cmd_info_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455154969	3749	0	0
T84	6543	56	0	0
T108	9757	34	0	0
T116	9755	71	0	0
T128	10187	73	0	0
T136	39908	278	0	0
T160	19930	23	0	0
T161	13775	43	0	0
T162	6950	9	0	0
T163	11938	50	0	0
T164	5665	6	0	0

cmd_info_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455154969	3759	0	0
T84	6543	11	0	0
T108	9757	23	0	0
T116	9755	39	0	0
T128	10187	137	0	0
T136	39908	229	0	0
T160	19930	12	0	0
T161	13775	36	0	0
T162	6950	15	0	0
T163	11938	10	0	0
T164	5665	63	0	0

cmd_info_11_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455154969	3419	0	0
T84	6543	8	0	0
T108	9757	11	0	0
T116	9755	14	0	0
T128	10187	47	0	0
T136	39908	222	0	0
T160	19930	70	0	0
T161	13775	37	0	0
T162	6950	10	0	0
T163	11938	16	0	0
T164	5665	49	0	0

cmd_info_12_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455154969	3842	0	0
T84	6543	59	0	0
T108	9757	33	0	0
T116	9755	27	0	0
T128	10187	95	0	0
T136	39908	240	0	0
T160	19930	55	0	0
T161	13775	11	0	0
T162	6950	7	0	0
T163	11938	23	0	0
T164	5665	46	0	0

cmd_info_13_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455154969	3553	0	0
T84	6543	58	0	0
T108	9757	37	0	0
T116	9755	8	0	0
T128	10187	8	0	0
T136	39908	202	0	0
T160	19930	55	0	0
T161	13775	54	0	0
T162	6950	7	0	0
T163	11938	26	0	0
T165	24525	5	0	0

cmd_info_14_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455154969	3885	0	0
T84	6543	10	0	0
T108	9757	3	0	0
T116	9755	14	0	0
T128	10187	59	0	0
T136	39908	290	0	0
T160	19930	8	0	0
T161	13775	48	0	0
T162	6950	8	0	0
T163	11938	9	0	0
T164	5665	46	0	0

cmd_info_15_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455154969	3776	0	0
T84	6543	15	0	0
T108	9757	45	0	0
T116	9755	46	0	0
T128	10187	72	0	0
T136	39908	231	0	0
T160	19930	26	0	0
T161	13775	48	0	0
T162	6950	10	0	0
T163	11938	5	0	0
T164	5665	5	0	0

cmd_info_16_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455154969	3582	0	0
T84	6543	4	0	0
T108	9757	30	0	0
T116	9755	8	0	0
T128	10187	7	0	0
T136	39908	249	0	0
T160	19930	50	0	0
T161	13775	40	0	0
T162	6950	17	0	0
T163	11938	23	0	0
T164	5665	2	0	0

cmd_info_17_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455154969	3790	0	0
T84	6543	33	0	0
T108	9757	29	0	0
T116	9755	5	0	0
T128	10187	46	0	0
T136	39908	241	0	0
T160	19930	54	0	0
T161	13775	33	0	0
T162	6950	19	0	0
T163	11938	15	0	0
T164	5665	44	0	0

cmd_info_18_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455154969	3830	0	0
T84	6543	3	0	0
T108	9757	63	0	0
T116	9755	2	0	0
T128	10187	97	0	0
T136	39908	229	0	0
T160	19930	55	0	0
T161	13775	33	0	0
T162	6950	10	0	0
T163	11938	31	0	0
T164	5665	62	0	0

cmd_info_19_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455154969	3488	0	0
T84	6543	50	0	0
T108	9757	23	0	0
T114	6012	1	0	0
T116	9755	32	0	0
T128	10187	160	0	0
T136	39908	260	0	0
T160	19930	26	0	0
T161	13775	28	0	0
T162	6950	4	0	0
T163	11938	6	0	0

cmd_info_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455154969	4027	0	0
T84	6543	44	0	0
T108	9757	54	0	0
T116	9755	49	0	0
T128	10187	55	0	0
T136	39908	260	0	0
T160	19930	18	0	0
T161	13775	82	0	0
T162	6950	24	0	0
T163	11938	41	0	0
T164	5665	4	0	0

cmd_info_20_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455154969	3940	0	0
T84	6543	8	0	0
T108	9757	8	0	0
T116	9755	39	0	0
T128	10187	17	0	0
T136	39908	242	0	0
T160	19930	54	0	0
T161	13775	36	0	0
T162	6950	5	0	0
T163	11938	17	0	0
T164	5665	10	0	0

cmd_info_21_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455154969	3828	0	0
T84	6543	62	0	0
T108	9757	12	0	0
T116	9755	34	0	0
T128	10187	166	0	0
T136	39908	262	0	0
T160	19930	24	0	0
T161	13775	77	0	0
T163	11938	31	0	0
T164	5665	8	0	0
T166	67697	570	0	0

cmd_info_22_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455154969	3433	0	0
T84	6543	7	0	0
T108	9757	7	0	0
T116	9755	4	0	0
T128	10187	52	0	0
T136	39908	192	0	0
T160	19930	51	0	0
T161	13775	29	0	0
T162	6950	11	0	0
T163	11938	41	0	0
T164	5665	69	0	0

cmd_info_23_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455154969	3781	0	0
T84	6543	65	0	0
T108	9757	3	0	0
T116	9755	17	0	0
T128	10187	12	0	0
T136	39908	233	0	0
T160	19930	30	0	0
T161	13775	95	0	0
T162	6950	4	0	0
T163	11938	16	0	0
T164	5665	7	0	0

cmd_info_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455154969	3901	0	0
T84	6543	5	0	0
T108	9757	31	0	0
T116	9755	36	0	0
T128	10187	129	0	0
T136	39908	231	0	0
T160	19930	54	0	0
T161	13775	49	0	0
T162	6950	28	0	0
T163	11938	44	0	0
T164	5665	53	0	0

cmd_info_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455154969	3587	0	0
T84	6543	50	0	0
T108	9757	40	0	0
T116	9755	56	0	0
T128	10187	16	0	0
T136	39908	252	0	0
T160	19930	40	0	0
T161	13775	61	0	0
T162	6950	14	0	0
T164	5665	3	0	0
T166	67697	580	0	0

cmd_info_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455154969	3611	0	0
T84	6543	66	0	0
T108	9757	29	0	0
T116	9755	63	0	0
T128	10187	110	0	0
T136	39908	233	0	0
T160	19930	33	0	0
T161	13775	41	0	0
T162	6950	24	0	0
T163	11938	39	0	0
T165	24525	2	0	0

cmd_info_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455154969	3715	0	0
T84	6543	49	0	0
T108	9757	46	0	0
T116	9755	13	0	0
T128	10187	116	0	0
T136	39908	246	0	0
T160	19930	21	0	0
T161	13775	38	0	0
T162	6950	12	0	0
T163	11938	9	0	0
T164	5665	51	0	0

cmd_info_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455154969	3830	0	0
T84	6543	66	0	0
T116	9755	31	0	0
T128	10187	60	0	0
T136	39908	225	0	0
T160	19930	39	0	0
T161	13775	59	0	0
T162	6950	12	0	0
T163	11938	28	0	0
T164	5665	58	0	0
T166	67697	573	0	0

cmd_info_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455154969	3272	0	0
T84	6543	2	0	0
T108	9757	26	0	0
T116	9755	43	0	0
T128	10187	6	0	0
T136	39908	265	0	0
T160	19930	21	0	0
T161	13775	28	0	0
T162	6950	3	0	0
T163	11938	26	0	0
T164	5665	51	0	0

cmd_info_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455154969	3763	0	0
T84	6543	4	0	0
T108	9757	15	0	0
T128	10187	78	0	0
T136	39908	248	0	0
T160	19930	30	0	0
T161	13775	40	0	0
T162	6950	14	0	0
T163	11938	24	0	0
T164	5665	12	0	0
T166	67697	590	0	0

cmd_info_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455154969	3905	0	0
T84	6543	63	0	0
T108	9757	34	0	0
T116	9755	45	0	0
T128	10187	53	0	0
T136	39908	233	0	0
T160	19930	17	0	0
T161	13775	78	0	0
T162	6950	16	0	0
T163	11938	52	0	0
T164	5665	13	0	0

cmd_info_en4b_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455154969	1480	0	0
T84	6543	10	0	0
T108	9757	3	0	0
T116	9755	9	0	0
T128	10187	17	0	0
T136	39908	205	0	0
T160	19930	20	0	0
T161	13775	51	0	0
T162	6950	7	0	0
T164	5665	13	0	0
T166	67697	112	0	0

cmd_info_ex4b_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455154969	1557	0	0
T84	6543	16	0	0
T108	9757	17	0	0
T116	9755	12	0	0
T128	10187	14	0	0
T136	39908	225	0	0
T160	19930	43	0	0
T161	13775	41	0	0
T162	6950	15	0	0
T163	11938	32	0	0
T164	5665	13	0	0

cmd_info_wrdi_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455154969	1578	0	0
T84	6543	5	0	0
T108	9757	8	0	0
T116	9755	15	0	0
T128	10187	10	0	0
T136	39908	247	0	0
T160	19930	57	0	0
T161	13775	12	0	0
T162	6950	39	0	0
T163	11938	23	0	0
T164	5665	19	0	0

cmd_info_wren_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455154969	1552	0	0
T84	6543	4	0	0
T108	9757	5	0	0
T116	9755	11	0	0
T128	10187	14	0	0
T136	39908	241	0	0
T160	19930	32	0	0
T161	13775	41	0	0
T162	6950	24	0	0
T163	11938	3	0	0
T164	5665	7	0	0

intercept_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455154969	1852	0	0
T84	6543	17	0	0
T108	9757	15	0	0
T116	9755	1	0	0
T128	10187	27	0	0
T136	39908	235	0	0
T160	19930	16	0	0
T161	13775	23	0	0
T162	6950	11	0	0
T163	11938	28	0	0
T164	5665	21	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455154969	3453	0	0
T34	0	20	0	0
T58	419172	0	0	0
T64	0	16	0	0
T87	4243	61	0	0
T140	1441	0	0	0
T141	3894	0	0	0
T142	1462	0	0	0
T143	6831	0	0	0
T144	843333	0	0	0
T145	39618	0	0	0
T146	2262	0	0	0
T147	398805	0	0	0
T167	0	32	0	0
T168	0	27	0	0
T169	0	32	0	0
T170	0	27	0	0
T171	0	18	0	0
T172	0	18	0	0
T173	0	18	0	0

jedec_cc_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455154969	1648	0	0
T84	6543	12	0	0
T108	9757	13	0	0
T116	9755	13	0	0
T128	10187	17	0	0
T136	39908	252	0	0
T160	19930	18	0	0
T161	13775	56	0	0
T162	6950	28	0	0
T163	11938	4	0	0
T164	5665	8	0	0

jedec_id_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455154969	1655	0	0
T84	6543	4	0	0
T108	9757	20	0	0
T116	9755	6	0	0
T128	10187	8	0	0
T136	39908	265	0	0
T160	19930	16	0	0
T161	13775	74	0	0
T162	6950	4	0	0
T163	11938	1	0	0
T164	5665	15	0	0

mailbox_addr_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455154969	1391	0	0
T84	6543	5	0	0
T108	9757	8	0	0
T116	9755	12	0	0
T128	10187	10	0	0
T136	39908	263	0	0
T160	19930	15	0	0
T161	13775	54	0	0
T162	6950	9	0	0
T163	11938	21	0	0
T164	5665	6	0	0

payload_swap_data_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455154969	1299	0	0
T84	6543	4	0	0
T108	9757	3	0	0
T116	9755	7	0	0
T128	10187	2	0	0
T136	39908	201	0	0
T160	19930	48	0	0
T161	13775	41	0	0
T162	6950	9	0	0
T164	5665	8	0	0
T166	67697	86	0	0

payload_swap_mask_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455154969	1421	0	0
T84	6543	2	0	0
T108	9757	8	0	0
T116	9755	15	0	0
T128	10187	14	0	0
T136	39908	321	0	0
T160	19930	67	0	0
T161	13775	11	0	0
T162	6950	10	0	0
T163	11938	19	0	0
T164	5665	3	0	0

read_threshold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455154969	1378	0	0
T84	6543	10	0	0
T108	9757	12	0	0
T116	9755	5	0	0
T128	10187	16	0	0
T136	39908	264	0	0
T160	19930	24	0	0
T161	13775	36	0	0
T162	6950	6	0	0
T163	11938	20	0	0
T164	5665	1	0	0

tpm_access_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455154969	2125	0	0
T84	6543	9	0	0
T108	9757	37	0	0
T128	10187	26	0	0
T136	39908	275	0	0
T160	19930	53	0	0
T161	13775	6	0	0
T162	6950	24	0	0
T163	11938	30	0	0
T164	5665	14	0	0
T166	67697	210	0	0

tpm_access_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455154969	1310	0	0
T84	6543	13	0	0
T108	9757	3	0	0
T116	9755	8	0	0
T128	10187	14	0	0
T136	39908	221	0	0
T160	19930	34	0	0
T161	13775	46	0	0
T162	6950	5	0	0
T163	11938	9	0	0
T164	5665	5	0	0

tpm_cfg_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455154969	2276	0	0
T84	6543	31	0	0
T108	9757	18	0	0
T116	9755	7	0	0
T128	10187	26	0	0
T136	39908	257	0	0
T160	19930	44	0	0
T161	13775	42	0	0
T163	11938	46	0	0
T164	5665	35	0	0
T166	67697	242	0	0

tpm_did_vid_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455154969	1545	0	0
T84	6543	11	0	0
T108	9757	4	0	0
T116	9755	8	0	0
T128	10187	20	0	0
T136	39908	240	0	0
T160	19930	47	0	0
T161	13775	52	0	0
T162	6950	6	0	0
T163	11938	32	0	0
T164	5665	6	0	0

tpm_int_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455154969	1319	0	0
T84	6543	2	0	0
T108	9757	3	0	0
T116	9755	12	0	0
T128	10187	13	0	0
T136	39908	241	0	0
T160	19930	31	0	0
T161	13775	26	0	0
T162	6950	6	0	0
T163	11938	19	0	0
T164	5665	7	0	0

tpm_int_status_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455154969	1416	0	0
T84	6543	8	0	0
T108	9757	13	0	0
T116	9755	10	0	0
T128	10187	8	0	0
T136	39908	252	0	0
T160	19930	59	0	0
T161	13775	18	0	0
T162	6950	2	0	0
T163	11938	26	0	0
T164	5665	14	0	0

tpm_int_vector_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455154969	1346	0	0
T108	9757	5	0	0
T116	9755	15	0	0
T128	10187	5	0	0
T136	39908	236	0	0
T160	19930	44	0	0
T161	13775	66	0	0
T162	6950	10	0	0
T163	11938	13	0	0
T164	5665	8	0	0
T166	67697	84	0	0

tpm_intf_capability_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455154969	1387	0	0
T84	6543	8	0	0
T108	9757	13	0	0
T116	9755	7	0	0
T128	10187	11	0	0
T136	39908	205	0	0
T160	19930	72	0	0
T161	13775	35	0	0
T162	6950	16	0	0
T163	11938	15	0	0
T164	5665	8	0	0

tpm_rid_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455154969	1430	0	0
T84	6543	1	0	0
T108	9757	3	0	0
T116	9755	2	0	0
T128	10187	15	0	0
T136	39908	298	0	0
T160	19930	77	0	0
T161	13775	76	0	0
T162	6950	6	0	0
T163	11938	18	0	0
T164	5665	12	0	0

tpm_sts_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455154969	1347	0	0
T84	6543	11	0	0
T108	9757	9	0	0
T116	9755	8	0	0
T128	10187	14	0	0
T136	39908	243	0	0
T160	19930	66	0	0
T161	13775	44	0	0
T162	6950	12	0	0
T163	11938	30	0	0
T164	5665	3	0	0