Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64




Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 6283397 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 6588468 1 T1 934 T2 909 T3 892



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 8266233 1 T1 55 T2 13 T3 29
values[0x0] 2303852 1 T1 459 T2 467 T3 420
values[0x1] 2301780 1 T1 466 T2 441 T3 467



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 4546587 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 8325278 1 T1 949 T2 914 T3 897



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 50356 1 T1 2 T2 3 T3 2
valid_sources[0x01] 54692 1 T1 3 T2 5 T3 3
valid_sources[0x02] 49286 1 T1 3 T2 4 T3 3
valid_sources[0x03] 50760 1 T1 2 T2 6 T3 5
valid_sources[0x04] 46743 1 T1 2 T2 2 T3 1
valid_sources[0x05] 48803 1 T1 6 T2 5 T3 2
valid_sources[0x06] 50645 1 T1 3 T2 4 T3 6
valid_sources[0x07] 54478 1 T1 1 T2 2 T3 2
valid_sources[0x08] 52920 1 T1 4 T2 7 T3 6
valid_sources[0x09] 49026 1 T1 4 T2 6 T3 3
valid_sources[0x0a] 49068 1 T1 3 T2 2 T3 8
valid_sources[0x0b] 53564 1 T1 4 T2 1 T3 3
valid_sources[0x0c] 50967 1 T1 5 T2 3 T3 3
valid_sources[0x0d] 52974 1 T1 5 T2 6 T3 5
valid_sources[0x0e] 45485 1 T1 9 T2 4 T3 2
valid_sources[0x0f] 48612 1 T1 3 T2 7 T4 3
valid_sources[0x10] 49261 1 T1 7 T2 3 T3 2
valid_sources[0x11] 47110 1 T1 2 T2 3 T3 3
valid_sources[0x12] 48437 1 T1 1 T2 3 T3 2
valid_sources[0x13] 48686 1 T1 6 T2 2 T3 3
valid_sources[0x14] 48538 1 T1 5 T2 8 T3 3
valid_sources[0x15] 50717 1 T1 7 T2 3 T3 2
valid_sources[0x16] 47990 1 T1 5 T2 6 T3 2
valid_sources[0x17] 51327 1 T1 2 T2 8 T3 1
valid_sources[0x18] 47714 1 T1 8 T2 4 T3 2
valid_sources[0x19] 56815 1 T1 3 T2 2 T3 4
valid_sources[0x1a] 49820 1 T1 2 T2 3 T3 4
valid_sources[0x1b] 50261 1 T2 4 T3 5 T6 8
valid_sources[0x1c] 52939 1 T1 7 T2 2 T6 5
valid_sources[0x1d] 48075 1 T1 3 T2 5 T3 4
valid_sources[0x1e] 44779 1 T1 1 T3 5 T4 1
valid_sources[0x1f] 49646 1 T1 4 T2 2 T3 5
valid_sources[0x20] 48648 1 T1 6 T2 3 T3 4
valid_sources[0x21] 53809 1 T1 8 T2 4 T3 1
valid_sources[0x22] 52255 1 T2 4 T3 1 T4 3
valid_sources[0x23] 53341 1 T1 2 T2 3 T3 4
valid_sources[0x24] 51148 1 T1 4 T2 5 T3 2
valid_sources[0x25] 48914 1 T1 2 T2 6 T3 4
valid_sources[0x26] 54894 1 T1 6 T2 4 T3 5
valid_sources[0x27] 52149 1 T1 4 T2 1 T4 2
valid_sources[0x28] 53175 1 T1 3 T2 2 T3 4
valid_sources[0x29] 45314 1 T1 4 T2 2 T3 7
valid_sources[0x2a] 50100 1 T1 4 T2 3 T3 7
valid_sources[0x2b] 46266 1 T1 7 T2 5 T3 3
valid_sources[0x2c] 50132 1 T1 8 T2 4 T3 1
valid_sources[0x2d] 46869 1 T1 5 T2 4 T3 5
valid_sources[0x2e] 48286 1 T1 10 T2 8 T3 3
valid_sources[0x2f] 49071 1 T1 5 T2 3 T3 4
valid_sources[0x30] 51322 1 T1 2 T2 5 T3 5
valid_sources[0x31] 45939 1 T1 2 T2 1 T3 2
valid_sources[0x32] 48433 1 T1 4 T2 3 T3 3
valid_sources[0x33] 49728 1 T1 4 T2 4 T3 3
valid_sources[0x34] 50612 1 T1 7 T2 3 T3 3
valid_sources[0x35] 54388 1 T1 3 T2 5 T3 5
valid_sources[0x36] 56313 1 T1 3 T2 3 T3 5
valid_sources[0x37] 49921 1 T1 2 T2 2 T3 4
valid_sources[0x38] 50799 1 T1 2 T2 3 T3 8
valid_sources[0x39] 48039 1 T1 2 T2 1 T3 4
valid_sources[0x3a] 47826 1 T1 4 T2 11 T3 4
valid_sources[0x3b] 48130 1 T1 5 T2 1 T3 4
valid_sources[0x3c] 61748 1 T1 3 T2 2 T3 2
valid_sources[0x3d] 47342 1 T1 1 T2 3 T3 4
valid_sources[0x3e] 51305 1 T1 10 T2 3 T3 6
valid_sources[0x3f] 52396 1 T1 3 T2 1 T6 1
valid_sources[0x40] 51801 1 T1 3 T2 4 T3 3
valid_sources[0x41] 51516 1 T1 5 T2 8 T3 1
valid_sources[0x42] 49200 1 T1 2 T2 5 T3 3
valid_sources[0x43] 50865 1 T1 5 T2 6 T3 5
valid_sources[0x44] 52676 1 T1 4 T2 1 T3 3
valid_sources[0x45] 51108 1 T1 3 T2 6 T3 3
valid_sources[0x46] 48547 1 T1 2 T3 2 T6 4
valid_sources[0x47] 44368 1 T1 2 T2 6 T6 1
valid_sources[0x48] 51575 1 T1 1 T2 5 T3 4
valid_sources[0x49] 47285 1 T1 6 T2 3 T3 3
valid_sources[0x4a] 53552 1 T1 3 T2 7 T3 3
valid_sources[0x4b] 54049 1 T1 3 T2 5 T3 6
valid_sources[0x4c] 50344 1 T1 1 T2 2 T3 1
valid_sources[0x4d] 49691 1 T1 10 T2 3 T3 5
valid_sources[0x4e] 51136 1 T1 7 T2 4 T4 2
valid_sources[0x4f] 48336 1 T2 1 T3 5 T4 5
valid_sources[0x50] 51081 1 T1 3 T2 1 T3 1
valid_sources[0x51] 49286 1 T1 1 T2 6 T3 3
valid_sources[0x52] 51835 1 T1 5 T2 5 T3 2
valid_sources[0x53] 50077 1 T2 7 T3 7 T4 3
valid_sources[0x54] 46151 1 T2 5 T3 1 T6 5
valid_sources[0x55] 52492 1 T1 4 T2 2 T3 9
valid_sources[0x56] 46389 1 T2 5 T3 1 T4 5
valid_sources[0x57] 51142 1 T1 4 T2 2 T3 4
valid_sources[0x58] 54169 1 T1 3 T2 8 T3 2
valid_sources[0x59] 50321 1 T1 1 T2 5 T3 1
valid_sources[0x5a] 50543 1 T1 4 T2 4 T3 8
valid_sources[0x5b] 53324 1 T1 2 T2 5 T3 4
valid_sources[0x5c] 48058 1 T3 7 T4 1 T6 4
valid_sources[0x5d] 45389 1 T1 3 T2 3 T3 4
valid_sources[0x5e] 48488 1 T1 6 T2 1 T3 1
valid_sources[0x5f] 56495 1 T1 4 T2 9 T3 3
valid_sources[0x60] 52450 1 T1 2 T2 6 T3 5
valid_sources[0x61] 50938 1 T1 5 T2 6 T3 4
valid_sources[0x62] 56536 1 T2 5 T3 3 T4 3
valid_sources[0x63] 51151 1 T1 12 T2 4 T3 4
valid_sources[0x64] 52110 1 T1 4 T2 4 T3 1
valid_sources[0x65] 48316 1 T1 4 T2 1 T3 2
valid_sources[0x66] 46332 1 T1 6 T2 4 T3 4
valid_sources[0x67] 46777 1 T1 4 T2 3 T3 4
valid_sources[0x68] 47892 1 T1 2 T2 5 T3 3
valid_sources[0x69] 50332 1 T1 2 T2 3 T3 4
valid_sources[0x6a] 49787 1 T1 3 T2 6 T3 7
valid_sources[0x6b] 47108 1 T1 2 T2 2 T3 5
valid_sources[0x6c] 49083 1 T1 7 T2 6 T3 3
valid_sources[0x6d] 48531 1 T1 6 T2 1 T3 2
valid_sources[0x6e] 51081 1 T1 3 T2 5 T3 5
valid_sources[0x6f] 49172 1 T1 2 T2 2 T3 1
valid_sources[0x70] 48661 1 T1 4 T2 2 T3 2
valid_sources[0x71] 54064 1 T1 1 T2 2 T3 4
valid_sources[0x72] 51757 1 T1 9 T2 2 T3 1
valid_sources[0x73] 50672 1 T1 6 T2 3 T3 3
valid_sources[0x74] 48613 1 T1 6 T2 1 T3 7
valid_sources[0x75] 48615 1 T1 4 T2 7 T3 6
valid_sources[0x76] 51437 1 T1 2 T2 3 T3 6
valid_sources[0x77] 49110 1 T1 5 T2 2 T3 1
valid_sources[0x78] 50351 1 T1 3 T2 4 T3 1
valid_sources[0x79] 47721 1 T1 1 T2 3 T3 2
valid_sources[0x7a] 48300 1 T1 4 T2 3 T3 5
valid_sources[0x7b] 44826 1 T1 6 T2 3 T3 13
valid_sources[0x7c] 52282 1 T1 4 T2 2 T3 2
valid_sources[0x7d] 47612 1 T1 8 T2 2 T3 1
valid_sources[0x7e] 50667 1 T1 6 T2 3 T3 3
valid_sources[0x7f] 50193 1 T1 4 T2 5 T3 1
valid_sources[0x80] 49498 1 T1 4 T2 3 T3 1



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 2472633 1 T1 14 T2 8 T3 15
values[0x0] all_enables biggest_size 2076220 1 T1 459 T2 465 T3 417
values[0x1] all_enables biggest_size 2039615 1 T1 461 T2 436 T3 460

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%