Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

6306607

1

T1

46

T2

12

T3

24

full_word

6587756

1

T1

934

T2

909

T3

892

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	12893973	1			T1	980		T2	921		T3	916
auto[TlIntgErrCmd]	151	1			T100	5		T106	5		T104	4
auto[TlIntgErrData]	118	1			T100	2		T106	7		T104	5
auto[TlIntgErrBoth]	121	1			T100	3		T106	8		T104	1

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8268208

1

T1

55

T2

13

T3

29

auto[1]

4626155

1

T1

925

T2

908

T3

887

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	5795257	1			T1	41		T2	5		T3	14
auto[TlIntgErrNone]	partial	auto[1]	510995	1			T1	5		T2	7		T3	10
auto[TlIntgErrNone]	full_word	auto[0]	2472775	1			T1	14		T2	8		T3	15
auto[TlIntgErrNone]	full_word	auto[1]	4114946	1			T1	920		T2	901		T3	877
auto[TlIntgErrCmd]	partial	auto[0]	45	1			T100	2		T106	1		T104	2
auto[TlIntgErrCmd]	partial	auto[1]	86	1			T100	2		T106	3		T104	2
auto[TlIntgErrCmd]	full_word	auto[0]	9	1			T100	1		T106	1		T148	1
auto[TlIntgErrCmd]	full_word	auto[1]	11	1			T178	1		T150	1		T179	1
auto[TlIntgErrData]	partial	auto[0]	69	1			T100	2		T106	3		T104	3
auto[TlIntgErrData]	partial	auto[1]	43	1			T106	3		T104	2		T105	1
auto[TlIntgErrData]	full_word	auto[0]	4	1			T106	1		T148	1		T180	1
auto[TlIntgErrData]	full_word	auto[1]	2	1			T179	1		T180	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	45	1			T106	2		T104	1		T105	2
auto[TlIntgErrBoth]	partial	auto[1]	67	1			T100	3		T106	6		T105	3
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T178	1		T179	1		T181	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T105	1		T147	1		T182	1