Unified Coverage Report :: Module :: prim_generic_ram_2p

Module : prim_generic_ram_2p

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_2p_0/rtl/prim_generic_ram_2p.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_mem

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : prim_generic_ram_2p

	Line No.	Total	Covered	Percent
TOTAL		21	21	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	61	1	1	100.00
CONT_ASSIGN	61	1	1	100.00
CONT_ASSIGN	61	1	1	100.00
CONT_ASSIGN	61	1	1	100.00
ALWAYS	76	6	6	100.00
ALWAYS	91	6	6	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_2p_0/rtl/prim_generic_ram_2p.sv' or '../src/lowrisc_prim_generic_ram_2p_0/rtl/prim_generic_ram_2p.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
49	1	1
60	4	4
61	4	4
76	1	1
77	1	1
78	1	1
79	1	1
80	1	1
			==> MISSING_ELSE
85	1	1
			MISSING_ELSE
91	1	1
92	1	1
93	1	1
94	1	1
95	1	1
			MISSING_ELSE
100	1	1
			MISSING_ELSE

---

Branch Coverage for Module : prim_generic_ram_2p

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
IF	76	3	3	100.00
IF	91	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_2p_0/rtl/prim_generic_ram_2p.sv' or '../src/lowrisc_prim_generic_ram_2p_0/rtl/prim_generic_ram_2p.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	if (a_req_i)
-2-:	77	if (a_write_i)

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T2,T3
1	0	Covered	T10,T12,T14
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	91	if (b_req_i)
-2-:	92	if (b_write_i)

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T10,T12,T14
1	0	Covered	T2,T3,T5
0	-	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_generic_ram_2p

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_wmask[0].MaskCheckPortA_A	561563399	2512220	0	0
gen_wmask[0].MaskCheckPortB_A	187870219	1292463	0	0
gen_wmask[1].MaskCheckPortA_A	561563399	2512220	0	0
gen_wmask[1].MaskCheckPortB_A	187870219	1292463	0	0
gen_wmask[2].MaskCheckPortA_A	561563399	2512220	0	0
gen_wmask[2].MaskCheckPortB_A	187870219	1292463	0	0
gen_wmask[3].MaskCheckPortA_A	561563399	2512220	0	0
gen_wmask[3].MaskCheckPortB_A	187870219	1292463	0	0

gen_wmask[0].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	561563399	2512220	0	0
T1	76827	832	0	0
T2	519741	832	0	0
T3	10882	832	0	0
T4	886987	832	0	0
T5	5997	832	0	0
T6	809247	832	0	0
T7	93200	832	0	0
T8	70006	832	0	0
T9	756879	1856	0	0
T10	544458	16640	0	0

gen_wmask[0].MaskCheckPortB_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	187870219	1292463	0	0
T10	755288	6289	0	0
T11	134448	0	0	0
T12	172805	4544	0	0
T14	62956	1790	0	0
T15	569392	2799	0	0
T16	180205	0	0	0
T17	0	1175	0	0
T18	0	8361	0	0
T19	0	3118	0	0
T27	0	2011	0	0
T28	0	2128	0	0
T30	32998	0	0	0
T31	6776	0	0	0
T32	25484	0	0	0
T33	0	6566	0	0
T45	83	0	0	0

gen_wmask[1].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	561563399	2512220	0	0
T1	76827	832	0	0
T2	519741	832	0	0
T3	10882	832	0	0
T4	886987	832	0	0
T5	5997	832	0	0
T6	809247	832	0	0
T7	93200	832	0	0
T8	70006	832	0	0
T9	756879	1856	0	0
T10	544458	16640	0	0

gen_wmask[1].MaskCheckPortB_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	187870219	1292463	0	0
T10	755288	6289	0	0
T11	134448	0	0	0
T12	172805	4544	0	0
T14	62956	1790	0	0
T15	569392	2799	0	0
T16	180205	0	0	0
T17	0	1175	0	0
T18	0	8361	0	0
T19	0	3118	0	0
T27	0	2011	0	0
T28	0	2128	0	0
T30	32998	0	0	0
T31	6776	0	0	0
T32	25484	0	0	0
T33	0	6566	0	0
T45	83	0	0	0

gen_wmask[2].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	561563399	2512220	0	0
T1	76827	832	0	0
T2	519741	832	0	0
T3	10882	832	0	0
T4	886987	832	0	0
T5	5997	832	0	0
T6	809247	832	0	0
T7	93200	832	0	0
T8	70006	832	0	0
T9	756879	1856	0	0
T10	544458	16640	0	0

gen_wmask[2].MaskCheckPortB_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	187870219	1292463	0	0
T10	755288	6289	0	0
T11	134448	0	0	0
T12	172805	4544	0	0
T14	62956	1790	0	0
T15	569392	2799	0	0
T16	180205	0	0	0
T17	0	1175	0	0
T18	0	8361	0	0
T19	0	3118	0	0
T27	0	2011	0	0
T28	0	2128	0	0
T30	32998	0	0	0
T31	6776	0	0	0
T32	25484	0	0	0
T33	0	6566	0	0
T45	83	0	0	0

gen_wmask[3].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	561563399	2512220	0	0
T1	76827	832	0	0
T2	519741	832	0	0
T3	10882	832	0	0
T4	886987	832	0	0
T5	5997	832	0	0
T6	809247	832	0	0
T7	93200	832	0	0
T8	70006	832	0	0
T9	756879	1856	0	0
T10	544458	16640	0	0

gen_wmask[3].MaskCheckPortB_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	187870219	1292463	0	0
T10	755288	6289	0	0
T11	134448	0	0	0
T12	172805	4544	0	0
T14	62956	1790	0	0
T15	569392	2799	0	0
T16	180205	0	0	0
T17	0	1175	0	0
T18	0	8361	0	0
T19	0	3118	0	0
T27	0	2011	0	0
T28	0	2128	0	0
T30	32998	0	0	0
T31	6776	0	0	0
T32	25484	0	0	0
T33	0	6566	0	0
T45	83	0	0	0