Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.fifo_h.reqfifo

Module Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	564094712	15170147	0	0
DepthKnown_A	564094712	563968614	0	0
RvalidKnown_A	564094712	563968614	0	0
WreadyKnown_A	564094712	563968614	0	0
gen_passthru_fifo.paramCheckPass	1114	1114	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	564094712	15170147	0	0
T1	76827	980	0	0
T2	519741	1753	0	0
T3	10882	1751	0	0
T4	886987	953	0	0
T5	5997	884	0	0
T6	809247	917	0	0
T7	93200	916	0	0
T8	70006	1746	0	0
T9	756879	10564	0	0
T10	544458	82166	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	564094712	563968614	0	0
T1	76827	76737	0	0
T2	519741	519668	0	0
T3	10882	10827	0	0
T4	886987	886887	0	0
T5	5997	5911	0	0
T6	809247	809170	0	0
T7	93200	93130	0	0
T8	70006	69924	0	0
T9	756879	756782	0	0
T10	544458	544451	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	564094712	563968614	0	0
T1	76827	76737	0	0
T2	519741	519668	0	0
T3	10882	10827	0	0
T4	886987	886887	0	0
T5	5997	5911	0	0
T6	809247	809170	0	0
T7	93200	93130	0	0
T8	70006	69924	0	0
T9	756879	756782	0	0
T10	544458	544451	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	564094712	563968614	0	0
T1	76827	76737	0	0
T2	519741	519668	0	0
T3	10882	10827	0	0
T4	886987	886887	0	0
T5	5997	5911	0	0
T6	809247	809170	0	0
T7	93200	93130	0	0
T8	70006	69924	0	0
T9	756879	756782	0	0
T10	544458	544451	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1114	1114	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	564094712	29482147	0	0
DepthKnown_A	564094712	563968614	0	0
RvalidKnown_A	564094712	563968614	0	0
WreadyKnown_A	564094712	563968614	0	0
gen_passthru_fifo.paramCheckPass	1114	1114	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	564094712	29482147	0	0
T1	76827	980	0	0
T2	519741	1093	0	0
T3	10882	1229	0	0
T4	886987	4335	0	0
T5	5997	884	0	0
T6	809247	917	0	0
T7	93200	4069	0	0
T8	70006	1182	0	0
T9	756879	8712	0	0
T10	544458	214173	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	564094712	563968614	0	0
T1	76827	76737	0	0
T2	519741	519668	0	0
T3	10882	10827	0	0
T4	886987	886887	0	0
T5	5997	5911	0	0
T6	809247	809170	0	0
T7	93200	93130	0	0
T8	70006	69924	0	0
T9	756879	756782	0	0
T10	544458	544451	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	564094712	563968614	0	0
T1	76827	76737	0	0
T2	519741	519668	0	0
T3	10882	10827	0	0
T4	886987	886887	0	0
T5	5997	5911	0	0
T6	809247	809170	0	0
T7	93200	93130	0	0
T8	70006	69924	0	0
T9	756879	756782	0	0
T10	544458	544451	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	564094712	563968614	0	0
T1	76827	76737	0	0
T2	519741	519668	0	0
T3	10882	10827	0	0
T4	886987	886887	0	0
T5	5997	5911	0	0
T6	809247	809170	0	0
T7	93200	93130	0	0
T8	70006	69924	0	0
T9	756879	756782	0	0
T10	544458	544451	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1114	1114	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	564094712	3433047	0	0
DepthKnown_A	564094712	563968614	0	0
RvalidKnown_A	564094712	563968614	0	0
WreadyKnown_A	564094712	563968614	0	0
gen_passthru_fifo.paramCheckPass	1114	1114	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	564094712	3433047	0	0
T1	76827	832	0	0
T2	519741	1664	0	0
T3	10882	1667	0	0
T4	886987	832	0	0
T5	5997	832	0	0
T6	809247	832	0	0
T7	93200	832	0	0
T8	70006	1665	0	0
T9	756879	3707	0	0
T10	544458	23312	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	564094712	563968614	0	0
T1	76827	76737	0	0
T2	519741	519668	0	0
T3	10882	10827	0	0
T4	886987	886887	0	0
T5	5997	5911	0	0
T6	809247	809170	0	0
T7	93200	93130	0	0
T8	70006	69924	0	0
T9	756879	756782	0	0
T10	544458	544451	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	564094712	563968614	0	0
T1	76827	76737	0	0
T2	519741	519668	0	0
T3	10882	10827	0	0
T4	886987	886887	0	0
T5	5997	5911	0	0
T6	809247	809170	0	0
T7	93200	93130	0	0
T8	70006	69924	0	0
T9	756879	756782	0	0
T10	544458	544451	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	564094712	563968614	0	0
T1	76827	76737	0	0
T2	519741	519668	0	0
T3	10882	10827	0	0
T4	886987	886887	0	0
T5	5997	5911	0	0
T6	809247	809170	0	0
T7	93200	93130	0	0
T8	70006	69924	0	0
T9	756879	756782	0	0
T10	544458	544451	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1114	1114	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	564094712	3728819	0	0
DepthKnown_A	564094712	563968614	0	0
RvalidKnown_A	564094712	563968614	0	0
WreadyKnown_A	564094712	563968614	0	0
gen_passthru_fifo.paramCheckPass	1114	1114	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	564094712	3728819	0	0
T1	76827	832	0	0
T2	519741	833	0	0
T3	10882	837	0	0
T4	886987	3795	0	0
T5	5997	832	0	0
T6	809247	832	0	0
T7	93200	3752	0	0
T8	70006	835	0	0
T9	756879	1856	0	0
T10	544458	37505	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	564094712	563968614	0	0
T1	76827	76737	0	0
T2	519741	519668	0	0
T3	10882	10827	0	0
T4	886987	886887	0	0
T5	5997	5911	0	0
T6	809247	809170	0	0
T7	93200	93130	0	0
T8	70006	69924	0	0
T9	756879	756782	0	0
T10	544458	544451	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	564094712	563968614	0	0
T1	76827	76737	0	0
T2	519741	519668	0	0
T3	10882	10827	0	0
T4	886987	886887	0	0
T5	5997	5911	0	0
T6	809247	809170	0	0
T7	93200	93130	0	0
T8	70006	69924	0	0
T9	756879	756782	0	0
T10	544458	544451	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	564094712	563968614	0	0
T1	76827	76737	0	0
T2	519741	519668	0	0
T3	10882	10827	0	0
T4	886987	886887	0	0
T5	5997	5911	0	0
T6	809247	809170	0	0
T7	93200	93130	0	0
T8	70006	69924	0	0
T9	756879	756782	0	0
T10	544458	544451	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1114	1114	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	564094712	227180	0	0
DepthKnown_A	564094712	563968614	0	0
RvalidKnown_A	564094712	563968614	0	0
WreadyKnown_A	564094712	563968614	0	0
gen_passthru_fifo.paramCheckPass	1114	1114	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	564094712	227180	0	0
T10	544458	390	0	0
T11	679601	0	0	0
T12	177852	1162	0	0
T13	1465	0	0	0
T14	392344	465	0	0
T15	159872	710	0	0
T17	0	307	0	0
T18	0	1232	0	0
T19	0	806	0	0
T24	0	100	0	0
T27	0	519	0	0
T28	0	488	0	0
T29	1526	0	0	0
T30	69415	0	0	0
T31	4770	0	0	0
T32	84150	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	564094712	563968614	0	0
T1	76827	76737	0	0
T2	519741	519668	0	0
T3	10882	10827	0	0
T4	886987	886887	0	0
T5	5997	5911	0	0
T6	809247	809170	0	0
T7	93200	93130	0	0
T8	70006	69924	0	0
T9	756879	756782	0	0
T10	544458	544451	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	564094712	563968614	0	0
T1	76827	76737	0	0
T2	519741	519668	0	0
T3	10882	10827	0	0
T4	886987	886887	0	0
T5	5997	5911	0	0
T6	809247	809170	0	0
T7	93200	93130	0	0
T8	70006	69924	0	0
T9	756879	756782	0	0
T10	544458	544451	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	564094712	563968614	0	0
T1	76827	76737	0	0
T2	519741	519668	0	0
T3	10882	10827	0	0
T4	886987	886887	0	0
T5	5997	5911	0	0
T6	809247	809170	0	0
T7	93200	93130	0	0
T8	70006	69924	0	0
T9	756879	756782	0	0
T10	544458	544451	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1114	1114	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	564094712	515738	0	0
DepthKnown_A	564094712	563968614	0	0
RvalidKnown_A	564094712	563968614	0	0
WreadyKnown_A	564094712	563968614	0	0
gen_passthru_fifo.paramCheckPass	1114	1114	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	564094712	515738	0	0
T10	544458	1368	0	0
T11	679601	0	0	0
T12	177852	1161	0	0
T13	1465	0	0	0
T14	392344	465	0	0
T15	159872	710	0	0
T17	0	307	0	0
T18	0	1232	0	0
T19	0	3615	0	0
T24	0	100	0	0
T27	0	1565	0	0
T28	0	2270	0	0
T29	1526	0	0	0
T30	69415	0	0	0
T31	4770	0	0	0
T32	84150	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	564094712	563968614	0	0
T1	76827	76737	0	0
T2	519741	519668	0	0
T3	10882	10827	0	0
T4	886987	886887	0	0
T5	5997	5911	0	0
T6	809247	809170	0	0
T7	93200	93130	0	0
T8	70006	69924	0	0
T9	756879	756782	0	0
T10	544458	544451	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	564094712	563968614	0	0
T1	76827	76737	0	0
T2	519741	519668	0	0
T3	10882	10827	0	0
T4	886987	886887	0	0
T5	5997	5911	0	0
T6	809247	809170	0	0
T7	93200	93130	0	0
T8	70006	69924	0	0
T9	756879	756782	0	0
T10	544458	544451	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	564094712	563968614	0	0
T1	76827	76737	0	0
T2	519741	519668	0	0
T3	10882	10827	0	0
T4	886987	886887	0	0
T5	5997	5911	0	0
T6	809247	809170	0	0
T7	93200	93130	0	0
T8	70006	69924	0	0
T9	756879	756782	0	0
T10	544458	544451	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1114	1114	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0