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Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 gen_dfifo[2].fifo_d


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
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Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 gen_dfifo[2].fifo_d


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
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Module Instances:
tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo
tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo
Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo
Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN4811100.00
CONT_ASSIGN4911100.00
CONT_ASSIGN5300
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
45 1 1
48 1 1
49 1 1
53 unreachable


Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 564094712 11163405 0 0
DepthKnown_A 564094712 563968614 0 0
RvalidKnown_A 564094712 563968614 0 0
WreadyKnown_A 564094712 563968614 0 0
gen_passthru_fifo.paramCheckPass 1114 1114 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 564094712 11163405 0 0
T1 76827 148 0 0
T2 519741 89 0 0
T3 10882 84 0 0
T4 886987 121 0 0
T5 5997 52 0 0
T6 809247 85 0 0
T7 93200 84 0 0
T8 70006 81 0 0
T9 756879 6856 0 0
T10 544458 57087 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 564094712 563968614 0 0
T1 76827 76737 0 0
T2 519741 519668 0 0
T3 10882 10827 0 0
T4 886987 886887 0 0
T5 5997 5911 0 0
T6 809247 809170 0 0
T7 93200 93130 0 0
T8 70006 69924 0 0
T9 756879 756782 0 0
T10 544458 544451 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 564094712 563968614 0 0
T1 76827 76737 0 0
T2 519741 519668 0 0
T3 10882 10827 0 0
T4 886987 886887 0 0
T5 5997 5911 0 0
T6 809247 809170 0 0
T7 93200 93130 0 0
T8 70006 69924 0 0
T9 756879 756782 0 0
T10 544458 544451 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 564094712 563968614 0 0
T1 76827 76737 0 0
T2 519741 519668 0 0
T3 10882 10827 0 0
T4 886987 886887 0 0
T5 5997 5911 0 0
T6 809247 809170 0 0
T7 93200 93130 0 0
T8 70006 69924 0 0
T9 756879 756782 0 0
T10 544458 544451 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 1114 1114 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo
Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN4811100.00
CONT_ASSIGN4911100.00
CONT_ASSIGN5300
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
45 1 1
48 1 1
49 1 1
53 unreachable


Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 564094712 25237590 0 0
DepthKnown_A 564094712 563968614 0 0
RvalidKnown_A 564094712 563968614 0 0
WreadyKnown_A 564094712 563968614 0 0
gen_passthru_fifo.paramCheckPass 1114 1114 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 564094712 25237590 0 0
T1 76827 148 0 0
T2 519741 260 0 0
T3 10882 392 0 0
T4 886987 540 0 0
T5 5997 52 0 0
T6 809247 85 0 0
T7 93200 317 0 0
T8 70006 347 0 0
T9 756879 6856 0 0
T10 544458 175300 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 564094712 563968614 0 0
T1 76827 76737 0 0
T2 519741 519668 0 0
T3 10882 10827 0 0
T4 886987 886887 0 0
T5 5997 5911 0 0
T6 809247 809170 0 0
T7 93200 93130 0 0
T8 70006 69924 0 0
T9 756879 756782 0 0
T10 544458 544451 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 564094712 563968614 0 0
T1 76827 76737 0 0
T2 519741 519668 0 0
T3 10882 10827 0 0
T4 886987 886887 0 0
T5 5997 5911 0 0
T6 809247 809170 0 0
T7 93200 93130 0 0
T8 70006 69924 0 0
T9 756879 756782 0 0
T10 544458 544451 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 564094712 563968614 0 0
T1 76827 76737 0 0
T2 519741 519668 0 0
T3 10882 10827 0 0
T4 886987 886887 0 0
T5 5997 5911 0 0
T6 809247 809170 0 0
T7 93200 93130 0 0
T8 70006 69924 0 0
T9 756879 756782 0 0
T10 544458 544451 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 1114 1114 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

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