Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T14,T15
1	0	Covered	T12,T14,T15

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T14
1	0	Unreachable
1	1	Covered	T12,T14,T15

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T10,T12,T15

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T12,T15
1	0	Covered	T10,T12,T15

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T10,T12,T15

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T10,T12,T14

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T12,T14
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T10,T12,T14
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	937303837	747467530	0	0
CheckNGreaterZero_A	2817	2817	0	0
GntImpliesReady_A	937303837	4339738	0	0
GntImpliesValid_A	937303837	4339738	0	0
GrantKnown_A	937303837	747467530	0	0
IdxKnown_A	937303837	747467530	0	0
IndexIsCorrect_A	937303837	4339738	0	0
LockArbDecision_A	937303837	0	0	0
NoReadyValidNoGrant_A	937303837	0	0	0
ReadyAndValidImplyGrant_A	937303837	4339738	0	0
ReqAndReadyImplyGrant_A	937303837	4339738	0	0
ReqImpliesValid_A	937303837	4339738	0	0
ReqStaysHighUntilGranted0_M	937303837	0	0	0
RoundRobin_A	937303837	10	0	939
ValidKnown_A	937303837	747467530	0	0
gen_data_port_assertion.DataFlow_A	937303837	4339738	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	937303837	747467530	0	0
T1	93681	92961	0	0
T2	605781	605708	0	0
T3	31529	31474	0	0
T4	996329	995863	0	0
T5	15917	15831	0	0
T6	923974	922834	0	0
T7	175897	175130	0	0
T8	78278	78196	0	0
T9	882691	882104	0	0
T10	1299746	1295444	0	0
T11	134448	128320	0	0
T12	172805	204792	0	0
T14	62956	60168	0	0
T15	569392	303672	0	0
T16	180205	172440	0	0
T17	0	38432	0	0
T18	0	126776	0	0
T19	0	157152	0	0
T27	0	93344	0	0
T30	32998	0	0	0
T31	6776	0	0	0
T32	25484	0	0	0
T35	65684	0	0	0
T44	0	792	0	0
T45	83	0	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2817	2817	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	937303837	4339738	0	0
T1	76827	832	0	0
T2	519741	832	0	0
T3	10882	832	0	0
T4	886987	832	0	0
T5	5997	832	0	0
T6	809247	832	0	0
T7	93200	832	0	0
T8	70006	832	0	0
T9	756879	1856	0	0
T10	1299746	23362	0	0
T11	134448	0	0	0
T12	345610	6279	0	0
T14	125912	2750	0	0
T15	1138784	3868	0	0
T16	360410	0	0	0
T17	41360	1781	0	0
T18	0	9027	0	0
T19	0	4293	0	0
T27	0	3128	0	0
T28	0	2928	0	0
T30	65996	0	0	0
T31	13552	0	0	0
T32	50968	0	0	0
T33	0	7858	0	0
T34	0	26241	0	0
T35	65684	0	0	0
T45	166	0	0	0
T46	0	775	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	937303837	4339738	0	0
T1	76827	832	0	0
T2	519741	832	0	0
T3	10882	832	0	0
T4	886987	832	0	0
T5	5997	832	0	0
T6	809247	832	0	0
T7	93200	832	0	0
T8	70006	832	0	0
T9	756879	1856	0	0
T10	1299746	23362	0	0
T11	134448	0	0	0
T12	345610	6279	0	0
T14	125912	2750	0	0
T15	1138784	3868	0	0
T16	360410	0	0	0
T17	41360	1781	0	0
T18	0	9027	0	0
T19	0	4293	0	0
T27	0	3128	0	0
T28	0	2928	0	0
T30	65996	0	0	0
T31	13552	0	0	0
T32	50968	0	0	0
T33	0	7858	0	0
T34	0	26241	0	0
T35	65684	0	0	0
T45	166	0	0	0
T46	0	775	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	937303837	747467530	0	0
T1	93681	92961	0	0
T2	605781	605708	0	0
T3	31529	31474	0	0
T4	996329	995863	0	0
T5	15917	15831	0	0
T6	923974	922834	0	0
T7	175897	175130	0	0
T8	78278	78196	0	0
T9	882691	882104	0	0
T10	1299746	1295444	0	0
T11	134448	128320	0	0
T12	172805	204792	0	0
T14	62956	60168	0	0
T15	569392	303672	0	0
T16	180205	172440	0	0
T17	0	38432	0	0
T18	0	126776	0	0
T19	0	157152	0	0
T27	0	93344	0	0
T30	32998	0	0	0
T31	6776	0	0	0
T32	25484	0	0	0
T35	65684	0	0	0
T44	0	792	0	0
T45	83	0	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	937303837	747467530	0	0
T1	93681	92961	0	0
T2	605781	605708	0	0
T3	31529	31474	0	0
T4	996329	995863	0	0
T5	15917	15831	0	0
T6	923974	922834	0	0
T7	175897	175130	0	0
T8	78278	78196	0	0
T9	882691	882104	0	0
T10	1299746	1295444	0	0
T11	134448	128320	0	0
T12	172805	204792	0	0
T14	62956	60168	0	0
T15	569392	303672	0	0
T16	180205	172440	0	0
T17	0	38432	0	0
T18	0	126776	0	0
T19	0	157152	0	0
T27	0	93344	0	0
T30	32998	0	0	0
T31	6776	0	0	0
T32	25484	0	0	0
T35	65684	0	0	0
T44	0	792	0	0
T45	83	0	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	937303837	4339738	0	0
T1	76827	832	0	0
T2	519741	832	0	0
T3	10882	832	0	0
T4	886987	832	0	0
T5	5997	832	0	0
T6	809247	832	0	0
T7	93200	832	0	0
T8	70006	832	0	0
T9	756879	1856	0	0
T10	1299746	23362	0	0
T11	134448	0	0	0
T12	345610	6279	0	0
T14	125912	2750	0	0
T15	1138784	3868	0	0
T16	360410	0	0	0
T17	41360	1781	0	0
T18	0	9027	0	0
T19	0	4293	0	0
T27	0	3128	0	0
T28	0	2928	0	0
T30	65996	0	0	0
T31	13552	0	0	0
T32	50968	0	0	0
T33	0	7858	0	0
T34	0	26241	0	0
T35	65684	0	0	0
T45	166	0	0	0
T46	0	775	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	937303837	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	937303837	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	937303837	4339738	0	0
T1	76827	832	0	0
T2	519741	832	0	0
T3	10882	832	0	0
T4	886987	832	0	0
T5	5997	832	0	0
T6	809247	832	0	0
T7	93200	832	0	0
T8	70006	832	0	0
T9	756879	1856	0	0
T10	1299746	23362	0	0
T11	134448	0	0	0
T12	345610	6279	0	0
T14	125912	2750	0	0
T15	1138784	3868	0	0
T16	360410	0	0	0
T17	41360	1781	0	0
T18	0	9027	0	0
T19	0	4293	0	0
T27	0	3128	0	0
T28	0	2928	0	0
T30	65996	0	0	0
T31	13552	0	0	0
T32	50968	0	0	0
T33	0	7858	0	0
T34	0	26241	0	0
T35	65684	0	0	0
T45	166	0	0	0
T46	0	775	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	937303837	4339738	0	0
T1	76827	832	0	0
T2	519741	832	0	0
T3	10882	832	0	0
T4	886987	832	0	0
T5	5997	832	0	0
T6	809247	832	0	0
T7	93200	832	0	0
T8	70006	832	0	0
T9	756879	1856	0	0
T10	1299746	23362	0	0
T11	134448	0	0	0
T12	345610	6279	0	0
T14	125912	2750	0	0
T15	1138784	3868	0	0
T16	360410	0	0	0
T17	41360	1781	0	0
T18	0	9027	0	0
T19	0	4293	0	0
T27	0	3128	0	0
T28	0	2928	0	0
T30	65996	0	0	0
T31	13552	0	0	0
T32	50968	0	0	0
T33	0	7858	0	0
T34	0	26241	0	0
T35	65684	0	0	0
T45	166	0	0	0
T46	0	775	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	937303837	4339738	0	0
T1	76827	832	0	0
T2	519741	832	0	0
T3	10882	832	0	0
T4	886987	832	0	0
T5	5997	832	0	0
T6	809247	832	0	0
T7	93200	832	0	0
T8	70006	832	0	0
T9	756879	1856	0	0
T10	1299746	23362	0	0
T11	134448	0	0	0
T12	345610	6279	0	0
T14	125912	2750	0	0
T15	1138784	3868	0	0
T16	360410	0	0	0
T17	41360	1781	0	0
T18	0	9027	0	0
T19	0	4293	0	0
T27	0	3128	0	0
T28	0	2928	0	0
T30	65996	0	0	0
T31	13552	0	0	0
T32	50968	0	0	0
T33	0	7858	0	0
T34	0	26241	0	0
T35	65684	0	0	0
T45	166	0	0	0
T46	0	775	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	937303837	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	937303837	10	0	939
T22	0	1	0	0
T47	595909	1	0	1
T48	0	1	0	0
T49	0	1	0	0
T50	0	2	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	154257	0	0	1
T56	1490	0	0	1
T57	1309	0	0	1
T58	124832	0	0	1
T59	10487	0	0	1
T60	888195	0	0	1
T61	139142	0	0	1
T62	88681	0	0	1
T63	428517	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	937303837	747467530	0	0
T1	93681	92961	0	0
T2	605781	605708	0	0
T3	31529	31474	0	0
T4	996329	995863	0	0
T5	15917	15831	0	0
T6	923974	922834	0	0
T7	175897	175130	0	0
T8	78278	78196	0	0
T9	882691	882104	0	0
T10	1299746	1295444	0	0
T11	134448	128320	0	0
T12	172805	204792	0	0
T14	62956	60168	0	0
T15	569392	303672	0	0
T16	180205	172440	0	0
T17	0	38432	0	0
T18	0	126776	0	0
T19	0	157152	0	0
T27	0	93344	0	0
T30	32998	0	0	0
T31	6776	0	0	0
T32	25484	0	0	0
T35	65684	0	0	0
T44	0	792	0	0
T45	83	0	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	937303837	4339738	0	0
T1	76827	832	0	0
T2	519741	832	0	0
T3	10882	832	0	0
T4	886987	832	0	0
T5	5997	832	0	0
T6	809247	832	0	0
T7	93200	832	0	0
T8	70006	832	0	0
T9	756879	1856	0	0
T10	1299746	23362	0	0
T11	134448	0	0	0
T12	345610	6279	0	0
T14	125912	2750	0	0
T15	1138784	3868	0	0
T16	360410	0	0	0
T17	41360	1781	0	0
T18	0	9027	0	0
T19	0	4293	0	0
T27	0	3128	0	0
T28	0	2928	0	0
T30	65996	0	0	0
T31	13552	0	0	0
T32	50968	0	0	0
T33	0	7858	0	0
T34	0	26241	0	0
T35	65684	0	0	0
T45	166	0	0	0
T46	0	775	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T14,T15
1	0	Covered	T12,T14,T15

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T14
1	0	Unreachable
1	1	Covered	T12,T14,T15

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T12,T14,T15
0	0	1	Unreachable
0	0	0	Covered	T11,T12,T14

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T12,T14,T15
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T12,T14,T15
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	187870219	41964292	0	0
CheckNGreaterZero_A	939	939	0	0
GntImpliesReady_A	187870219	943426	0	0
GntImpliesValid_A	187870219	943426	0	0
GrantKnown_A	187870219	41964292	0	0
IdxKnown_A	187870219	41964292	0	0
IndexIsCorrect_A	187870219	943426	0	0
LockArbDecision_A	187870219	0	0	0
NoReadyValidNoGrant_A	187870219	0	0	0
ReadyAndValidImplyGrant_A	187870219	943426	0	0
ReqAndReadyImplyGrant_A	187870219	943426	0	0
ReqImpliesValid_A	187870219	943426	0	0
ReqStaysHighUntilGranted0_M	187870219	0	0	0
RoundRobin_A	187870219	0	0	0
ValidKnown_A	187870219	41964292	0	0
gen_data_port_assertion.DataFlow_A	187870219	943426	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	187870219	41964292	0	0
T11	134448	128320	0	0
T12	172805	204792	0	0
T14	62956	60168	0	0
T15	569392	303672	0	0
T16	180205	172440	0	0
T17	0	38432	0	0
T18	0	126776	0	0
T19	0	157152	0	0
T27	0	93344	0	0
T30	32998	0	0	0
T31	6776	0	0	0
T32	25484	0	0	0
T35	65684	0	0	0
T44	0	792	0	0
T45	83	0	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	939	939	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	187870219	943426	0	0
T12	172805	5314	0	0
T14	62956	2750	0	0
T15	569392	3248	0	0
T16	180205	0	0	0
T17	41360	1781	0	0
T18	0	2337	0	0
T19	0	4293	0	0
T27	0	3128	0	0
T28	0	2398	0	0
T30	32998	0	0	0
T31	6776	0	0	0
T32	25484	0	0	0
T33	0	4874	0	0
T34	0	8717	0	0
T35	65684	0	0	0
T45	83	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	187870219	943426	0	0
T12	172805	5314	0	0
T14	62956	2750	0	0
T15	569392	3248	0	0
T16	180205	0	0	0
T17	41360	1781	0	0
T18	0	2337	0	0
T19	0	4293	0	0
T27	0	3128	0	0
T28	0	2398	0	0
T30	32998	0	0	0
T31	6776	0	0	0
T32	25484	0	0	0
T33	0	4874	0	0
T34	0	8717	0	0
T35	65684	0	0	0
T45	83	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	187870219	41964292	0	0
T11	134448	128320	0	0
T12	172805	204792	0	0
T14	62956	60168	0	0
T15	569392	303672	0	0
T16	180205	172440	0	0
T17	0	38432	0	0
T18	0	126776	0	0
T19	0	157152	0	0
T27	0	93344	0	0
T30	32998	0	0	0
T31	6776	0	0	0
T32	25484	0	0	0
T35	65684	0	0	0
T44	0	792	0	0
T45	83	0	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	187870219	41964292	0	0
T11	134448	128320	0	0
T12	172805	204792	0	0
T14	62956	60168	0	0
T15	569392	303672	0	0
T16	180205	172440	0	0
T17	0	38432	0	0
T18	0	126776	0	0
T19	0	157152	0	0
T27	0	93344	0	0
T30	32998	0	0	0
T31	6776	0	0	0
T32	25484	0	0	0
T35	65684	0	0	0
T44	0	792	0	0
T45	83	0	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	187870219	943426	0	0
T12	172805	5314	0	0
T14	62956	2750	0	0
T15	569392	3248	0	0
T16	180205	0	0	0
T17	41360	1781	0	0
T18	0	2337	0	0
T19	0	4293	0	0
T27	0	3128	0	0
T28	0	2398	0	0
T30	32998	0	0	0
T31	6776	0	0	0
T32	25484	0	0	0
T33	0	4874	0	0
T34	0	8717	0	0
T35	65684	0	0	0
T45	83	0	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	187870219	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	187870219	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	187870219	943426	0	0
T12	172805	5314	0	0
T14	62956	2750	0	0
T15	569392	3248	0	0
T16	180205	0	0	0
T17	41360	1781	0	0
T18	0	2337	0	0
T19	0	4293	0	0
T27	0	3128	0	0
T28	0	2398	0	0
T30	32998	0	0	0
T31	6776	0	0	0
T32	25484	0	0	0
T33	0	4874	0	0
T34	0	8717	0	0
T35	65684	0	0	0
T45	83	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	187870219	943426	0	0
T12	172805	5314	0	0
T14	62956	2750	0	0
T15	569392	3248	0	0
T16	180205	0	0	0
T17	41360	1781	0	0
T18	0	2337	0	0
T19	0	4293	0	0
T27	0	3128	0	0
T28	0	2398	0	0
T30	32998	0	0	0
T31	6776	0	0	0
T32	25484	0	0	0
T33	0	4874	0	0
T34	0	8717	0	0
T35	65684	0	0	0
T45	83	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	187870219	943426	0	0
T12	172805	5314	0	0
T14	62956	2750	0	0
T15	569392	3248	0	0
T16	180205	0	0	0
T17	41360	1781	0	0
T18	0	2337	0	0
T19	0	4293	0	0
T27	0	3128	0	0
T28	0	2398	0	0
T30	32998	0	0	0
T31	6776	0	0	0
T32	25484	0	0	0
T33	0	4874	0	0
T34	0	8717	0	0
T35	65684	0	0	0
T45	83	0	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	187870219	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	187870219	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	187870219	41964292	0	0
T11	134448	128320	0	0
T12	172805	204792	0	0
T14	62956	60168	0	0
T15	569392	303672	0	0
T16	180205	172440	0	0
T17	0	38432	0	0
T18	0	126776	0	0
T19	0	157152	0	0
T27	0	93344	0	0
T30	32998	0	0	0
T31	6776	0	0	0
T32	25484	0	0	0
T35	65684	0	0	0
T44	0	792	0	0
T45	83	0	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	187870219	943426	0	0
T12	172805	5314	0	0
T14	62956	2750	0	0
T15	569392	3248	0	0
T16	180205	0	0	0
T17	41360	1781	0	0
T18	0	2337	0	0
T19	0	4293	0	0
T27	0	3128	0	0
T28	0	2398	0	0
T30	32998	0	0	0
T31	6776	0	0	0
T32	25484	0	0	0
T33	0	4874	0	0
T34	0	8717	0	0
T35	65684	0	0	0
T45	83	0	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T10,T12,T15

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T12,T15
1	0	Covered	T10,T12,T15

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T10,T12,T15

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T10,T12,T15
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T10,T12,T15
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T10,T12,T15
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T10,T12,T15
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	187870219	144021107	0	0
CheckNGreaterZero_A	939	939	0	0
GntImpliesReady_A	187870219	660456	0	0
GntImpliesValid_A	187870219	660456	0	0
GrantKnown_A	187870219	144021107	0	0
IdxKnown_A	187870219	144021107	0	0
IndexIsCorrect_A	187870219	660456	0	0
LockArbDecision_A	187870219	0	0	0
NoReadyValidNoGrant_A	187870219	0	0	0
ReadyAndValidImplyGrant_A	187870219	660456	0	0
ReqAndReadyImplyGrant_A	187870219	660456	0	0
ReqImpliesValid_A	187870219	660456	0	0
ReqStaysHighUntilGranted0_M	187870219	0	0	0
RoundRobin_A	187870219	0	0	0
ValidKnown_A	187870219	144021107	0	0
gen_data_port_assertion.DataFlow_A	187870219	660456	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	187870219	144021107	0	0
T1	16854	16224	0	0
T2	86040	86040	0	0
T3	20647	20647	0	0
T4	109342	108976	0	0
T5	9920	9920	0	0
T6	114727	113664	0	0
T7	82697	82000	0	0
T8	8272	8272	0	0
T9	125812	125322	0	0
T10	755288	750993	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	939	939	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	187870219	660456	0	0
T10	755288	6289	0	0
T11	134448	0	0	0
T12	172805	965	0	0
T14	62956	0	0	0
T15	569392	620	0	0
T16	180205	0	0	0
T18	0	6690	0	0
T28	0	530	0	0
T30	32998	0	0	0
T31	6776	0	0	0
T32	25484	0	0	0
T33	0	2984	0	0
T34	0	17524	0	0
T45	83	0	0	0
T46	0	775	0	0
T64	0	135	0	0
T65	0	1106	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	187870219	660456	0	0
T10	755288	6289	0	0
T11	134448	0	0	0
T12	172805	965	0	0
T14	62956	0	0	0
T15	569392	620	0	0
T16	180205	0	0	0
T18	0	6690	0	0
T28	0	530	0	0
T30	32998	0	0	0
T31	6776	0	0	0
T32	25484	0	0	0
T33	0	2984	0	0
T34	0	17524	0	0
T45	83	0	0	0
T46	0	775	0	0
T64	0	135	0	0
T65	0	1106	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	187870219	144021107	0	0
T1	16854	16224	0	0
T2	86040	86040	0	0
T3	20647	20647	0	0
T4	109342	108976	0	0
T5	9920	9920	0	0
T6	114727	113664	0	0
T7	82697	82000	0	0
T8	8272	8272	0	0
T9	125812	125322	0	0
T10	755288	750993	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	187870219	144021107	0	0
T1	16854	16224	0	0
T2	86040	86040	0	0
T3	20647	20647	0	0
T4	109342	108976	0	0
T5	9920	9920	0	0
T6	114727	113664	0	0
T7	82697	82000	0	0
T8	8272	8272	0	0
T9	125812	125322	0	0
T10	755288	750993	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	187870219	660456	0	0
T10	755288	6289	0	0
T11	134448	0	0	0
T12	172805	965	0	0
T14	62956	0	0	0
T15	569392	620	0	0
T16	180205	0	0	0
T18	0	6690	0	0
T28	0	530	0	0
T30	32998	0	0	0
T31	6776	0	0	0
T32	25484	0	0	0
T33	0	2984	0	0
T34	0	17524	0	0
T45	83	0	0	0
T46	0	775	0	0
T64	0	135	0	0
T65	0	1106	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	187870219	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	187870219	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	187870219	660456	0	0
T10	755288	6289	0	0
T11	134448	0	0	0
T12	172805	965	0	0
T14	62956	0	0	0
T15	569392	620	0	0
T16	180205	0	0	0
T18	0	6690	0	0
T28	0	530	0	0
T30	32998	0	0	0
T31	6776	0	0	0
T32	25484	0	0	0
T33	0	2984	0	0
T34	0	17524	0	0
T45	83	0	0	0
T46	0	775	0	0
T64	0	135	0	0
T65	0	1106	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	187870219	660456	0	0
T10	755288	6289	0	0
T11	134448	0	0	0
T12	172805	965	0	0
T14	62956	0	0	0
T15	569392	620	0	0
T16	180205	0	0	0
T18	0	6690	0	0
T28	0	530	0	0
T30	32998	0	0	0
T31	6776	0	0	0
T32	25484	0	0	0
T33	0	2984	0	0
T34	0	17524	0	0
T45	83	0	0	0
T46	0	775	0	0
T64	0	135	0	0
T65	0	1106	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	187870219	660456	0	0
T10	755288	6289	0	0
T11	134448	0	0	0
T12	172805	965	0	0
T14	62956	0	0	0
T15	569392	620	0	0
T16	180205	0	0	0
T18	0	6690	0	0
T28	0	530	0	0
T30	32998	0	0	0
T31	6776	0	0	0
T32	25484	0	0	0
T33	0	2984	0	0
T34	0	17524	0	0
T45	83	0	0	0
T46	0	775	0	0
T64	0	135	0	0
T65	0	1106	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	187870219	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	187870219	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	187870219	144021107	0	0
T1	16854	16224	0	0
T2	86040	86040	0	0
T3	20647	20647	0	0
T4	109342	108976	0	0
T5	9920	9920	0	0
T6	114727	113664	0	0
T7	82697	82000	0	0
T8	8272	8272	0	0
T9	125812	125322	0	0
T10	755288	750993	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	187870219	660456	0	0
T10	755288	6289	0	0
T11	134448	0	0	0
T12	172805	965	0	0
T14	62956	0	0	0
T15	569392	620	0	0
T16	180205	0	0	0
T18	0	6690	0	0
T28	0	530	0	0
T30	32998	0	0	0
T31	6776	0	0	0
T32	25484	0	0	0
T33	0	2984	0	0
T34	0	17524	0	0
T45	83	0	0	0
T46	0	775	0	0
T64	0	135	0	0
T65	0	1106	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T10,T12,T14

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T12,T14
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T10,T12,T14
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	561563399	561482131	0	0
CheckNGreaterZero_A	939	939	0	0
GntImpliesReady_A	561563399	2735856	0	0
GntImpliesValid_A	561563399	2735856	0	0
GrantKnown_A	561563399	561482131	0	0
IdxKnown_A	561563399	561482131	0	0
IndexIsCorrect_A	561563399	2735856	0	0
LockArbDecision_A	561563399	0	0	0
NoReadyValidNoGrant_A	561563399	0	0	0
ReadyAndValidImplyGrant_A	561563399	2735856	0	0
ReqAndReadyImplyGrant_A	561563399	2735856	0	0
ReqImpliesValid_A	561563399	2735856	0	0
ReqStaysHighUntilGranted0_M	561563399	0	0	0
RoundRobin_A	561563399	10	0	939
ValidKnown_A	561563399	561482131	0	0
gen_data_port_assertion.DataFlow_A	561563399	2735856	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	561563399	561482131	0	0
T1	76827	76737	0	0
T2	519741	519668	0	0
T3	10882	10827	0	0
T4	886987	886887	0	0
T5	5997	5911	0	0
T6	809247	809170	0	0
T7	93200	93130	0	0
T8	70006	69924	0	0
T9	756879	756782	0	0
T10	544458	544451	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	939	939	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	561563399	2735856	0	0
T1	76827	832	0	0
T2	519741	832	0	0
T3	10882	832	0	0
T4	886987	832	0	0
T5	5997	832	0	0
T6	809247	832	0	0
T7	93200	832	0	0
T8	70006	832	0	0
T9	756879	1856	0	0
T10	544458	17073	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	561563399	2735856	0	0
T1	76827	832	0	0
T2	519741	832	0	0
T3	10882	832	0	0
T4	886987	832	0	0
T5	5997	832	0	0
T6	809247	832	0	0
T7	93200	832	0	0
T8	70006	832	0	0
T9	756879	1856	0	0
T10	544458	17073	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	561563399	561482131	0	0
T1	76827	76737	0	0
T2	519741	519668	0	0
T3	10882	10827	0	0
T4	886987	886887	0	0
T5	5997	5911	0	0
T6	809247	809170	0	0
T7	93200	93130	0	0
T8	70006	69924	0	0
T9	756879	756782	0	0
T10	544458	544451	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	561563399	561482131	0	0
T1	76827	76737	0	0
T2	519741	519668	0	0
T3	10882	10827	0	0
T4	886987	886887	0	0
T5	5997	5911	0	0
T6	809247	809170	0	0
T7	93200	93130	0	0
T8	70006	69924	0	0
T9	756879	756782	0	0
T10	544458	544451	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	561563399	2735856	0	0
T1	76827	832	0	0
T2	519741	832	0	0
T3	10882	832	0	0
T4	886987	832	0	0
T5	5997	832	0	0
T6	809247	832	0	0
T7	93200	832	0	0
T8	70006	832	0	0
T9	756879	1856	0	0
T10	544458	17073	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	561563399	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	561563399	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	561563399	2735856	0	0
T1	76827	832	0	0
T2	519741	832	0	0
T3	10882	832	0	0
T4	886987	832	0	0
T5	5997	832	0	0
T6	809247	832	0	0
T7	93200	832	0	0
T8	70006	832	0	0
T9	756879	1856	0	0
T10	544458	17073	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	561563399	2735856	0	0
T1	76827	832	0	0
T2	519741	832	0	0
T3	10882	832	0	0
T4	886987	832	0	0
T5	5997	832	0	0
T6	809247	832	0	0
T7	93200	832	0	0
T8	70006	832	0	0
T9	756879	1856	0	0
T10	544458	17073	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	561563399	2735856	0	0
T1	76827	832	0	0
T2	519741	832	0	0
T3	10882	832	0	0
T4	886987	832	0	0
T5	5997	832	0	0
T6	809247	832	0	0
T7	93200	832	0	0
T8	70006	832	0	0
T9	756879	1856	0	0
T10	544458	17073	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	561563399	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	561563399	10	0	939
T22	0	1	0	0
T47	595909	1	0	1
T48	0	1	0	0
T49	0	1	0	0
T50	0	2	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	154257	0	0	1
T56	1490	0	0	1
T57	1309	0	0	1
T58	124832	0	0	1
T59	10487	0	0	1
T60	888195	0	0	1
T61	139142	0	0	1
T62	88681	0	0	1
T63	428517	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	561563399	561482131	0	0
T1	76827	76737	0	0
T2	519741	519668	0	0
T3	10882	10827	0	0
T4	886987	886887	0	0
T5	5997	5911	0	0
T6	809247	809170	0	0
T7	93200	93130	0	0
T8	70006	69924	0	0
T9	756879	756782	0	0
T10	544458	544451	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	561563399	2735856	0	0
T1	76827	832	0	0
T2	519741	832	0	0
T3	10882	832	0	0
T4	886987	832	0	0
T5	5997	832	0	0
T6	809247	832	0	0
T7	93200	832	0	0
T8	70006	832	0	0
T9	756879	1856	0	0
T10	544458	17073	0	0