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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.99 98.39 94.43 98.61 89.36 97.10 95.82 98.22


Total test records in report: 1114
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T131 /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.3348308356 Mar 19 03:18:45 PM PDT 24 Mar 19 03:18:47 PM PDT 24 73346353 ps
T1023 /workspace/coverage/cover_reg_top/10.spi_device_intr_test.548029810 Mar 19 03:18:29 PM PDT 24 Mar 19 03:18:30 PM PDT 24 11852318 ps
T1024 /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.3504892332 Mar 19 03:18:49 PM PDT 24 Mar 19 03:18:52 PM PDT 24 109669889 ps
T1025 /workspace/coverage/cover_reg_top/44.spi_device_intr_test.276690707 Mar 19 03:19:00 PM PDT 24 Mar 19 03:19:01 PM PDT 24 31785878 ps
T1026 /workspace/coverage/cover_reg_top/32.spi_device_intr_test.1664581694 Mar 19 03:18:38 PM PDT 24 Mar 19 03:18:40 PM PDT 24 33917983 ps
T110 /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.2806508769 Mar 19 03:18:38 PM PDT 24 Mar 19 03:18:44 PM PDT 24 722740929 ps
T1027 /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.3777660732 Mar 19 03:18:25 PM PDT 24 Mar 19 03:18:27 PM PDT 24 93744502 ps
T1028 /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.4033142170 Mar 19 03:18:43 PM PDT 24 Mar 19 03:18:47 PM PDT 24 362590955 ps
T1029 /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.3893775904 Mar 19 03:18:17 PM PDT 24 Mar 19 03:18:18 PM PDT 24 124071225 ps
T1030 /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.2962867189 Mar 19 03:18:32 PM PDT 24 Mar 19 03:18:34 PM PDT 24 121324373 ps
T148 /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.3954911927 Mar 19 03:18:47 PM PDT 24 Mar 19 03:19:11 PM PDT 24 980742902 ps
T91 /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.1433970977 Mar 19 03:18:42 PM PDT 24 Mar 19 03:18:43 PM PDT 24 56358435 ps
T1031 /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.3361295544 Mar 19 03:18:37 PM PDT 24 Mar 19 03:18:42 PM PDT 24 290016085 ps
T178 /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.3218375703 Mar 19 03:18:49 PM PDT 24 Mar 19 03:19:01 PM PDT 24 622036335 ps
T1032 /workspace/coverage/cover_reg_top/1.spi_device_intr_test.850312088 Mar 19 03:18:25 PM PDT 24 Mar 19 03:18:26 PM PDT 24 17426803 ps
T1033 /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.4184978492 Mar 19 03:18:29 PM PDT 24 Mar 19 03:18:31 PM PDT 24 176892776 ps
T1034 /workspace/coverage/cover_reg_top/47.spi_device_intr_test.3385577755 Mar 19 03:18:48 PM PDT 24 Mar 19 03:18:49 PM PDT 24 26726987 ps
T117 /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.4284514118 Mar 19 03:18:46 PM PDT 24 Mar 19 03:18:50 PM PDT 24 580840961 ps
T149 /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.4104638806 Mar 19 03:18:48 PM PDT 24 Mar 19 03:18:50 PM PDT 24 52255914 ps
T1035 /workspace/coverage/cover_reg_top/11.spi_device_intr_test.2165499739 Mar 19 03:18:29 PM PDT 24 Mar 19 03:18:30 PM PDT 24 19796066 ps
T1036 /workspace/coverage/cover_reg_top/38.spi_device_intr_test.3023794815 Mar 19 03:18:52 PM PDT 24 Mar 19 03:18:53 PM PDT 24 13479668 ps
T132 /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.3866235559 Mar 19 03:18:19 PM PDT 24 Mar 19 03:18:31 PM PDT 24 2531795924 ps
T150 /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.4077429759 Mar 19 03:18:27 PM PDT 24 Mar 19 03:18:49 PM PDT 24 3989124917 ps
T1037 /workspace/coverage/cover_reg_top/19.spi_device_intr_test.3722163853 Mar 19 03:18:48 PM PDT 24 Mar 19 03:18:49 PM PDT 24 16843990 ps
T182 /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.4006116158 Mar 19 03:18:18 PM PDT 24 Mar 19 03:18:32 PM PDT 24 204024331 ps
T1038 /workspace/coverage/cover_reg_top/42.spi_device_intr_test.3746217690 Mar 19 03:18:47 PM PDT 24 Mar 19 03:18:48 PM PDT 24 38149464 ps
T112 /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.1071151243 Mar 19 03:18:47 PM PDT 24 Mar 19 03:18:52 PM PDT 24 228699142 ps
T92 /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.4134667410 Mar 19 03:18:21 PM PDT 24 Mar 19 03:18:24 PM PDT 24 97447999 ps
T1039 /workspace/coverage/cover_reg_top/21.spi_device_intr_test.1003349057 Mar 19 03:18:48 PM PDT 24 Mar 19 03:18:49 PM PDT 24 20992639 ps
T151 /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.1825634487 Mar 19 03:18:30 PM PDT 24 Mar 19 03:18:32 PM PDT 24 93016568 ps
T1040 /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.1742455945 Mar 19 03:18:39 PM PDT 24 Mar 19 03:18:41 PM PDT 24 48856972 ps
T1041 /workspace/coverage/cover_reg_top/46.spi_device_intr_test.1051553744 Mar 19 03:18:51 PM PDT 24 Mar 19 03:18:52 PM PDT 24 42936083 ps
T118 /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.1485370487 Mar 19 03:18:51 PM PDT 24 Mar 19 03:18:55 PM PDT 24 152990004 ps
T1042 /workspace/coverage/cover_reg_top/49.spi_device_intr_test.15725179 Mar 19 03:18:48 PM PDT 24 Mar 19 03:18:50 PM PDT 24 12996283 ps
T179 /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.2056323419 Mar 19 03:18:45 PM PDT 24 Mar 19 03:19:06 PM PDT 24 4918788294 ps
T1043 /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.431818336 Mar 19 03:18:38 PM PDT 24 Mar 19 03:18:43 PM PDT 24 603710605 ps
T1044 /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.2270560484 Mar 19 03:18:32 PM PDT 24 Mar 19 03:18:35 PM PDT 24 172756053 ps
T111 /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.1823567568 Mar 19 03:18:31 PM PDT 24 Mar 19 03:18:33 PM PDT 24 69239314 ps
T1045 /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.786548488 Mar 19 03:18:33 PM PDT 24 Mar 19 03:18:40 PM PDT 24 336246445 ps
T1046 /workspace/coverage/cover_reg_top/33.spi_device_intr_test.1413724599 Mar 19 03:18:38 PM PDT 24 Mar 19 03:18:39 PM PDT 24 65199845 ps
T1047 /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.291062525 Mar 19 03:18:39 PM PDT 24 Mar 19 03:18:42 PM PDT 24 60153531 ps
T1048 /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.1420694072 Mar 19 03:18:30 PM PDT 24 Mar 19 03:18:31 PM PDT 24 12529934 ps
T113 /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.1710488474 Mar 19 03:18:28 PM PDT 24 Mar 19 03:18:31 PM PDT 24 994270081 ps
T1049 /workspace/coverage/cover_reg_top/39.spi_device_intr_test.2467440533 Mar 19 03:18:49 PM PDT 24 Mar 19 03:18:50 PM PDT 24 16650571 ps
T1050 /workspace/coverage/cover_reg_top/45.spi_device_intr_test.1444356179 Mar 19 03:18:49 PM PDT 24 Mar 19 03:18:50 PM PDT 24 19016175 ps
T181 /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.373962188 Mar 19 03:18:26 PM PDT 24 Mar 19 03:18:41 PM PDT 24 8427301009 ps
T1051 /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.3593871243 Mar 19 03:18:46 PM PDT 24 Mar 19 03:18:49 PM PDT 24 422296833 ps
T1052 /workspace/coverage/cover_reg_top/7.spi_device_intr_test.1044826663 Mar 19 03:18:29 PM PDT 24 Mar 19 03:18:30 PM PDT 24 62641428 ps
T1053 /workspace/coverage/cover_reg_top/6.spi_device_intr_test.2531769914 Mar 19 03:18:40 PM PDT 24 Mar 19 03:18:41 PM PDT 24 23103754 ps
T1054 /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.2774211205 Mar 19 03:18:31 PM PDT 24 Mar 19 03:18:33 PM PDT 24 180410071 ps
T1055 /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.1391972281 Mar 19 03:18:49 PM PDT 24 Mar 19 03:18:53 PM PDT 24 181476668 ps
T1056 /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.66859095 Mar 19 03:18:41 PM PDT 24 Mar 19 03:18:45 PM PDT 24 95556098 ps
T115 /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.3350603692 Mar 19 03:18:14 PM PDT 24 Mar 19 03:18:19 PM PDT 24 182644738 ps
T1057 /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.2338878926 Mar 19 03:18:21 PM PDT 24 Mar 19 03:18:23 PM PDT 24 52245652 ps
T1058 /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.1851192793 Mar 19 03:18:43 PM PDT 24 Mar 19 03:18:46 PM PDT 24 74620919 ps
T1059 /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.3771605476 Mar 19 03:18:18 PM PDT 24 Mar 19 03:18:31 PM PDT 24 215103127 ps
T1060 /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.317019333 Mar 19 03:18:49 PM PDT 24 Mar 19 03:18:52 PM PDT 24 165426715 ps
T1061 /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.4200114773 Mar 19 03:18:43 PM PDT 24 Mar 19 03:18:45 PM PDT 24 274165633 ps
T1062 /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.1306056855 Mar 19 03:18:21 PM PDT 24 Mar 19 03:18:24 PM PDT 24 95461098 ps
T1063 /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.341440010 Mar 19 03:18:18 PM PDT 24 Mar 19 03:18:19 PM PDT 24 50273347 ps
T1064 /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.3733536892 Mar 19 03:18:18 PM PDT 24 Mar 19 03:18:22 PM PDT 24 55046625 ps
T1065 /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.2488507024 Mar 19 03:18:41 PM PDT 24 Mar 19 03:18:43 PM PDT 24 74279276 ps
T1066 /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.373876296 Mar 19 03:18:19 PM PDT 24 Mar 19 03:18:27 PM PDT 24 456456757 ps
T1067 /workspace/coverage/cover_reg_top/15.spi_device_intr_test.4132300770 Mar 19 03:18:42 PM PDT 24 Mar 19 03:18:43 PM PDT 24 40906712 ps
T1068 /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.113077333 Mar 19 03:18:17 PM PDT 24 Mar 19 03:18:19 PM PDT 24 26123155 ps
T1069 /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.1219332506 Mar 19 03:18:46 PM PDT 24 Mar 19 03:18:50 PM PDT 24 453835778 ps
T1070 /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.1914872971 Mar 19 03:18:41 PM PDT 24 Mar 19 03:18:43 PM PDT 24 38613150 ps
T1071 /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.2872172681 Mar 19 03:18:38 PM PDT 24 Mar 19 03:18:41 PM PDT 24 177747782 ps
T1072 /workspace/coverage/cover_reg_top/35.spi_device_intr_test.905180112 Mar 19 03:18:39 PM PDT 24 Mar 19 03:18:41 PM PDT 24 61487403 ps
T1073 /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.3388858110 Mar 19 03:18:27 PM PDT 24 Mar 19 03:18:34 PM PDT 24 407078928 ps
T1074 /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.1656227072 Mar 19 03:18:38 PM PDT 24 Mar 19 03:18:41 PM PDT 24 99643948 ps
T176 /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.3151595466 Mar 19 03:18:36 PM PDT 24 Mar 19 03:18:41 PM PDT 24 287801002 ps
T1075 /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.1107858697 Mar 19 03:18:40 PM PDT 24 Mar 19 03:18:44 PM PDT 24 127810905 ps
T1076 /workspace/coverage/cover_reg_top/31.spi_device_intr_test.1902200110 Mar 19 03:18:46 PM PDT 24 Mar 19 03:18:46 PM PDT 24 23435614 ps
T1077 /workspace/coverage/cover_reg_top/14.spi_device_intr_test.2798224430 Mar 19 03:18:38 PM PDT 24 Mar 19 03:18:40 PM PDT 24 12894739 ps
T1078 /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.4280328187 Mar 19 03:18:38 PM PDT 24 Mar 19 03:18:40 PM PDT 24 42245448 ps
T1079 /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.723722913 Mar 19 03:18:40 PM PDT 24 Mar 19 03:18:43 PM PDT 24 102126932 ps
T1080 /workspace/coverage/cover_reg_top/4.spi_device_intr_test.3194587182 Mar 19 03:18:21 PM PDT 24 Mar 19 03:18:22 PM PDT 24 11866050 ps
T1081 /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.2633518610 Mar 19 03:18:39 PM PDT 24 Mar 19 03:18:54 PM PDT 24 2582543611 ps
T1082 /workspace/coverage/cover_reg_top/48.spi_device_intr_test.374329074 Mar 19 03:18:49 PM PDT 24 Mar 19 03:18:51 PM PDT 24 13823179 ps
T1083 /workspace/coverage/cover_reg_top/24.spi_device_intr_test.4235517338 Mar 19 03:18:45 PM PDT 24 Mar 19 03:18:46 PM PDT 24 22584761 ps
T1084 /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.4020864358 Mar 19 03:18:36 PM PDT 24 Mar 19 03:18:39 PM PDT 24 111619005 ps
T177 /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.1221702534 Mar 19 03:18:36 PM PDT 24 Mar 19 03:18:38 PM PDT 24 172692583 ps
T1085 /workspace/coverage/cover_reg_top/43.spi_device_intr_test.4218054289 Mar 19 03:18:49 PM PDT 24 Mar 19 03:18:50 PM PDT 24 14887697 ps
T1086 /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.1516713555 Mar 19 03:18:28 PM PDT 24 Mar 19 03:18:32 PM PDT 24 56885391 ps
T1087 /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.2406970613 Mar 19 03:18:31 PM PDT 24 Mar 19 03:18:34 PM PDT 24 585362575 ps
T1088 /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.1002278978 Mar 19 03:18:20 PM PDT 24 Mar 19 03:18:23 PM PDT 24 153220631 ps
T1089 /workspace/coverage/cover_reg_top/13.spi_device_intr_test.1248862662 Mar 19 03:18:38 PM PDT 24 Mar 19 03:18:40 PM PDT 24 148783753 ps
T1090 /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.983599785 Mar 19 03:18:32 PM PDT 24 Mar 19 03:18:37 PM PDT 24 153894606 ps
T1091 /workspace/coverage/cover_reg_top/26.spi_device_intr_test.469612651 Mar 19 03:18:48 PM PDT 24 Mar 19 03:18:50 PM PDT 24 18687650 ps
T1092 /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.768785910 Mar 19 03:18:18 PM PDT 24 Mar 19 03:18:26 PM PDT 24 371672753 ps
T1093 /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.465589610 Mar 19 03:18:47 PM PDT 24 Mar 19 03:18:56 PM PDT 24 290182875 ps
T1094 /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.3792175149 Mar 19 03:18:19 PM PDT 24 Mar 19 03:18:23 PM PDT 24 154964665 ps
T1095 /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.766521397 Mar 19 03:18:21 PM PDT 24 Mar 19 03:18:22 PM PDT 24 30439948 ps
T180 /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.2327218893 Mar 19 03:18:15 PM PDT 24 Mar 19 03:18:37 PM PDT 24 1008738298 ps
T1096 /workspace/coverage/cover_reg_top/3.spi_device_intr_test.25725365 Mar 19 03:18:46 PM PDT 24 Mar 19 03:18:46 PM PDT 24 18817669 ps
T1097 /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.1485396594 Mar 19 03:18:31 PM PDT 24 Mar 19 03:18:33 PM PDT 24 29455042 ps
T1098 /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.2679490624 Mar 19 03:18:28 PM PDT 24 Mar 19 03:18:33 PM PDT 24 62056355 ps
T1099 /workspace/coverage/cover_reg_top/16.spi_device_intr_test.928640737 Mar 19 03:18:46 PM PDT 24 Mar 19 03:18:47 PM PDT 24 31531731 ps
T1100 /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.2338570225 Mar 19 03:18:42 PM PDT 24 Mar 19 03:18:45 PM PDT 24 250511479 ps
T1101 /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.204347701 Mar 19 03:18:16 PM PDT 24 Mar 19 03:18:17 PM PDT 24 34796079 ps
T1102 /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.2634024039 Mar 19 03:18:46 PM PDT 24 Mar 19 03:18:50 PM PDT 24 122975685 ps
T1103 /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.4191549713 Mar 19 03:18:43 PM PDT 24 Mar 19 03:18:47 PM PDT 24 222416192 ps
T1104 /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.2138991704 Mar 19 03:18:47 PM PDT 24 Mar 19 03:19:06 PM PDT 24 676388548 ps
T1105 /workspace/coverage/cover_reg_top/18.spi_device_intr_test.1395634958 Mar 19 03:18:45 PM PDT 24 Mar 19 03:18:46 PM PDT 24 242880194 ps
T1106 /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.782332129 Mar 19 03:18:34 PM PDT 24 Mar 19 03:18:36 PM PDT 24 28535791 ps
T1107 /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.3432730943 Mar 19 03:18:48 PM PDT 24 Mar 19 03:18:52 PM PDT 24 481418128 ps
T1108 /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.2608280453 Mar 19 03:18:17 PM PDT 24 Mar 19 03:18:20 PM PDT 24 83445702 ps
T1109 /workspace/coverage/cover_reg_top/36.spi_device_intr_test.545768803 Mar 19 03:18:43 PM PDT 24 Mar 19 03:18:44 PM PDT 24 40427005 ps
T1110 /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.1595191428 Mar 19 03:18:45 PM PDT 24 Mar 19 03:18:46 PM PDT 24 51271332 ps
T1111 /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.2005970237 Mar 19 03:18:32 PM PDT 24 Mar 19 03:18:35 PM PDT 24 375516768 ps
T1112 /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.1631169977 Mar 19 03:18:18 PM PDT 24 Mar 19 03:18:27 PM PDT 24 391243801 ps
T1113 /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.4249895590 Mar 19 03:18:33 PM PDT 24 Mar 19 03:19:09 PM PDT 24 1867222687 ps
T1114 /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.1399448881 Mar 19 03:18:40 PM PDT 24 Mar 19 03:18:44 PM PDT 24 170762259 ps

Test location /workspace/coverage/default/17.spi_device_flash_all.1634093826
Short name T10
Test name
Test status
Simulation time 54445914628 ps
CPU time 252.51 seconds
Started Mar 19 02:17:32 PM PDT 24
Finished Mar 19 02:21:44 PM PDT 24
Peak memory 255012 kb
Host smart-e6b8de7e-a714-4865-b168-a39092ddca0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1634093826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.1634093826
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.3071613609
Short name T12
Test name
Test status
Simulation time 68405616746 ps
CPU time 238.46 seconds
Started Mar 19 02:19:34 PM PDT 24
Finished Mar 19 02:23:33 PM PDT 24
Peak memory 274192 kb
Host smart-323b162f-d40d-4879-807f-0d6cb22a7956
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3071613609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idl
e.3071613609
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.3583299970
Short name T39
Test name
Test status
Simulation time 412467336203 ps
CPU time 1259.8 seconds
Started Mar 19 02:19:38 PM PDT 24
Finished Mar 19 02:40:38 PM PDT 24
Peak memory 306992 kb
Host smart-8028ba0e-ce15-4f6e-96ac-7a39f0d39295
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583299970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stre
ss_all.3583299970
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.2271288606
Short name T47
Test name
Test status
Simulation time 62075951775 ps
CPU time 571.21 seconds
Started Mar 19 02:14:41 PM PDT 24
Finished Mar 19 02:24:12 PM PDT 24
Peak memory 286512 kb
Host smart-19ae2cfd-c579-4688-ac84-520c7bd2d717
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271288606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stres
s_all.2271288606
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.717845268
Short name T106
Test name
Test status
Simulation time 1370522707 ps
CPU time 14.73 seconds
Started Mar 19 03:18:29 PM PDT 24
Finished Mar 19 03:18:44 PM PDT 24
Peak memory 215540 kb
Host smart-fb9cb43a-c1cb-49af-ae01-8c5beba92948
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717845268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_
tl_intg_err.717845268
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.3465659825
Short name T33
Test name
Test status
Simulation time 81706829961 ps
CPU time 555.2 seconds
Started Mar 19 02:15:40 PM PDT 24
Finished Mar 19 02:24:55 PM PDT 24
Peak memory 254360 kb
Host smart-08e386b6-02ba-4cdf-a4cc-92119ad422ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3465659825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.3465659825
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.879472380
Short name T568
Test name
Test status
Simulation time 21960994 ps
CPU time 0.75 seconds
Started Mar 19 02:13:23 PM PDT 24
Finished Mar 19 02:13:24 PM PDT 24
Peak memory 216520 kb
Host smart-79962595-c153-479d-8e51-52c1c3fdb250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=879472380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.879472380
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.692270555
Short name T34
Test name
Test status
Simulation time 125211090275 ps
CPU time 480.22 seconds
Started Mar 19 02:17:47 PM PDT 24
Finished Mar 19 02:25:47 PM PDT 24
Peak memory 283868 kb
Host smart-41c45728-d382-43fc-8d36-3aa377f4a73d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692270555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idle
.692270555
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.2814778064
Short name T103
Test name
Test status
Simulation time 140169275 ps
CPU time 4.69 seconds
Started Mar 19 03:18:28 PM PDT 24
Finished Mar 19 03:18:33 PM PDT 24
Peak memory 215636 kb
Host smart-985224c7-1f70-4ee8-9869-4159f44eaff1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814778064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.2
814778064
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.1186694972
Short name T9
Test name
Test status
Simulation time 34404032791 ps
CPU time 41.12 seconds
Started Mar 19 02:18:00 PM PDT 24
Finished Mar 19 02:18:42 PM PDT 24
Peak memory 248280 kb
Host smart-49eb4439-c824-4927-9d46-ab7b4644cb95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1186694972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.1186694972
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.4193612405
Short name T188
Test name
Test status
Simulation time 281287207187 ps
CPU time 339.19 seconds
Started Mar 19 02:18:05 PM PDT 24
Finished Mar 19 02:23:45 PM PDT 24
Peak memory 282488 kb
Host smart-bea8e045-0a46-48a4-8af7-c4d3fbd78ae1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193612405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stre
ss_all.4193612405
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.873928479
Short name T75
Test name
Test status
Simulation time 133580286 ps
CPU time 1 seconds
Started Mar 19 02:13:34 PM PDT 24
Finished Mar 19 02:13:36 PM PDT 24
Peak memory 234840 kb
Host smart-fcf8900f-4a4f-498c-aa1f-c68297f8d530
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873928479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.873928479
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.773221671
Short name T86
Test name
Test status
Simulation time 14658159085 ps
CPU time 188.47 seconds
Started Mar 19 02:20:34 PM PDT 24
Finished Mar 19 02:23:42 PM PDT 24
Peak memory 265004 kb
Host smart-56f5a4d3-1ad3-474e-9d84-f4f1a15e213b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=773221671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.773221671
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.730530199
Short name T126
Test name
Test status
Simulation time 1264755120 ps
CPU time 8.92 seconds
Started Mar 19 03:18:20 PM PDT 24
Finished Mar 19 03:18:29 PM PDT 24
Peak memory 215556 kb
Host smart-1d2a3fda-a9e8-47c8-9f8a-f0391c605b11
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730530199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr
_aliasing.730530199
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.1485544931
Short name T41
Test name
Test status
Simulation time 164226053454 ps
CPU time 608.2 seconds
Started Mar 19 02:21:01 PM PDT 24
Finished Mar 19 02:31:10 PM PDT 24
Peak memory 264432 kb
Host smart-ec499cc3-d4ca-4a2f-ad47-3b727820327e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1485544931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idl
e.1485544931
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_mem_parity.1620936192
Short name T25
Test name
Test status
Simulation time 57720366 ps
CPU time 1.06 seconds
Started Mar 19 02:16:18 PM PDT 24
Finished Mar 19 02:16:19 PM PDT 24
Peak memory 217096 kb
Host smart-21ca726f-6a01-4996-a5f9-27853e580989
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620936192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 10.spi_device_mem_parity.1620936192
Directory /workspace/10.spi_device_mem_parity/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.3240421626
Short name T134
Test name
Test status
Simulation time 21338228175 ps
CPU time 251.28 seconds
Started Mar 19 02:16:27 PM PDT 24
Finished Mar 19 02:20:39 PM PDT 24
Peak memory 284192 kb
Host smart-6fbfb476-694b-43cc-b32b-6b55ed1db51f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240421626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stre
ss_all.3240421626
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.3960225289
Short name T196
Test name
Test status
Simulation time 64403956842 ps
CPU time 206.89 seconds
Started Mar 19 02:20:35 PM PDT 24
Finished Mar 19 02:24:02 PM PDT 24
Peak memory 266908 kb
Host smart-e3d75da8-b6b2-4596-9ca7-2b0480839b08
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960225289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stre
ss_all.3960225289
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.1381614328
Short name T18
Test name
Test status
Simulation time 5590897298 ps
CPU time 88.21 seconds
Started Mar 19 02:18:13 PM PDT 24
Finished Mar 19 02:19:42 PM PDT 24
Peak memory 257840 kb
Host smart-ffc7dc21-6ade-4244-be1d-aa91781d0363
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381614328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stre
ss_all.1381614328
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.1140024902
Short name T93
Test name
Test status
Simulation time 10307220492 ps
CPU time 38.02 seconds
Started Mar 19 02:16:15 PM PDT 24
Finished Mar 19 02:16:53 PM PDT 24
Peak memory 221336 kb
Host smart-809c2fff-131c-474a-9d5d-9ee299bfa81a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1140024902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.1140024902
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.1742244365
Short name T135
Test name
Test status
Simulation time 21889702193 ps
CPU time 138.44 seconds
Started Mar 19 02:14:01 PM PDT 24
Finished Mar 19 02:16:19 PM PDT 24
Peak memory 282164 kb
Host smart-508fd3b7-d869-4a9a-9b02-c7a05fcf0fbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1742244365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle
.1742244365
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.24561276
Short name T288
Test name
Test status
Simulation time 41256177 ps
CPU time 0.71 seconds
Started Mar 19 02:16:52 PM PDT 24
Finished Mar 19 02:16:53 PM PDT 24
Peak memory 205132 kb
Host smart-942916f2-702b-4a55-9a00-96b39326c119
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24561276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.24561276
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.2056323419
Short name T179
Test name
Test status
Simulation time 4918788294 ps
CPU time 20.85 seconds
Started Mar 19 03:18:45 PM PDT 24
Finished Mar 19 03:19:06 PM PDT 24
Peak memory 216188 kb
Host smart-b41e8855-c175-47cf-98f4-18b6bce1b05c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056323419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_devic
e_tl_intg_err.2056323419
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.1791489186
Short name T51
Test name
Test status
Simulation time 533992885270 ps
CPU time 907 seconds
Started Mar 19 02:19:01 PM PDT 24
Finished Mar 19 02:34:08 PM PDT 24
Peak memory 282460 kb
Host smart-874417d8-4caa-4a96-a450-d33ba397298a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791489186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stre
ss_all.1791489186
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.662191973
Short name T184
Test name
Test status
Simulation time 103843730483 ps
CPU time 196.28 seconds
Started Mar 19 02:16:54 PM PDT 24
Finished Mar 19 02:20:10 PM PDT 24
Peak memory 250728 kb
Host smart-cd9831eb-d00c-4994-be28-0527b88dd62d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=662191973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.662191973
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.48375477
Short name T281
Test name
Test status
Simulation time 3171525464 ps
CPU time 30.98 seconds
Started Mar 19 02:17:46 PM PDT 24
Finished Mar 19 02:18:17 PM PDT 24
Peak memory 216840 kb
Host smart-99a65bf2-8099-411d-b760-7c4d2b88b4b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48375477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.48375477
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.1062767888
Short name T382
Test name
Test status
Simulation time 3954157656 ps
CPU time 27.51 seconds
Started Mar 19 02:20:47 PM PDT 24
Finished Mar 19 02:21:15 PM PDT 24
Peak memory 233300 kb
Host smart-921442f2-9c5e-44f4-9bc2-4b99066c0f27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1062767888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.1062767888
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.4153988013
Short name T60
Test name
Test status
Simulation time 370084657669 ps
CPU time 691.37 seconds
Started Mar 19 02:20:48 PM PDT 24
Finished Mar 19 02:32:19 PM PDT 24
Peak memory 273248 kb
Host smart-8a8a379b-b987-423f-b45b-38982ea0f2c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153988013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stre
ss_all.4153988013
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.3151595466
Short name T176
Test name
Test status
Simulation time 287801002 ps
CPU time 4.16 seconds
Started Mar 19 03:18:36 PM PDT 24
Finished Mar 19 03:18:41 PM PDT 24
Peak memory 215916 kb
Host smart-332df7a7-aaa0-4af1-aafc-6a65423a68b2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151595466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.
3151595466
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.1025087328
Short name T263
Test name
Test status
Simulation time 58231524446 ps
CPU time 392.28 seconds
Started Mar 19 02:17:15 PM PDT 24
Finished Mar 19 02:23:48 PM PDT 24
Peak memory 256184 kb
Host smart-e881093c-bd67-4dc5-85ef-2007878a899c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1025087328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.1025087328
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.1111456367
Short name T206
Test name
Test status
Simulation time 90878935620 ps
CPU time 469.84 seconds
Started Mar 19 02:21:32 PM PDT 24
Finished Mar 19 02:29:22 PM PDT 24
Peak memory 265964 kb
Host smart-e9f6038b-e7c2-4516-9455-cd0e0a056627
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1111456367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.1111456367
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.3945459248
Short name T6
Test name
Test status
Simulation time 8429955604 ps
CPU time 22.17 seconds
Started Mar 19 02:16:41 PM PDT 24
Finished Mar 19 02:17:03 PM PDT 24
Peak memory 224984 kb
Host smart-c4b9042a-e360-4ddc-8a3b-8115bb4eac36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3945459248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swa
p.3945459248
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.2678942441
Short name T23
Test name
Test status
Simulation time 25621063758 ps
CPU time 129.74 seconds
Started Mar 19 02:21:01 PM PDT 24
Finished Mar 19 02:23:11 PM PDT 24
Peak memory 271660 kb
Host smart-62d61441-63aa-4af7-b880-455efb4f021a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2678942441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.2678942441
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.3498143755
Short name T147
Test name
Test status
Simulation time 670443046 ps
CPU time 15.77 seconds
Started Mar 19 03:18:32 PM PDT 24
Finished Mar 19 03:18:48 PM PDT 24
Peak memory 215620 kb
Host smart-bcb93845-961d-4522-8545-6339471526ca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498143755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_devic
e_tl_intg_err.3498143755
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.370033853
Short name T274
Test name
Test status
Simulation time 15699149541 ps
CPU time 61.22 seconds
Started Mar 19 02:16:53 PM PDT 24
Finished Mar 19 02:17:55 PM PDT 24
Peak memory 249756 kb
Host smart-85d367f0-a6cb-4aa0-a0c8-aaf243407424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=370033853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idle
.370033853
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.2981030761
Short name T278
Test name
Test status
Simulation time 2319854972 ps
CPU time 22.31 seconds
Started Mar 19 02:16:54 PM PDT 24
Finished Mar 19 02:17:17 PM PDT 24
Peak memory 243912 kb
Host smart-d5da9421-c9bb-42a8-9fd1-272d772847fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2981030761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.2981030761
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.1150949802
Short name T268
Test name
Test status
Simulation time 20175956932 ps
CPU time 28.37 seconds
Started Mar 19 02:18:21 PM PDT 24
Finished Mar 19 02:18:50 PM PDT 24
Peak memory 239896 kb
Host smart-db3f8f25-7b28-4bf6-851c-f3b34a04aa02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1150949802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swa
p.1150949802
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.2269730987
Short name T95
Test name
Test status
Simulation time 65667753717 ps
CPU time 317.1 seconds
Started Mar 19 02:18:25 PM PDT 24
Finished Mar 19 02:23:43 PM PDT 24
Peak memory 257236 kb
Host smart-25577efe-15d9-4b92-9fe0-729ca3c13e9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2269730987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.2269730987
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.1433970977
Short name T91
Test name
Test status
Simulation time 56358435 ps
CPU time 0.98 seconds
Started Mar 19 03:18:42 PM PDT 24
Finished Mar 19 03:18:43 PM PDT 24
Peak memory 207044 kb
Host smart-837d9113-95c1-4171-be08-482e11919cd7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433970977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_hw_reset.1433970977
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.3866235559
Short name T132
Test name
Test status
Simulation time 2531795924 ps
CPU time 12.06 seconds
Started Mar 19 03:18:19 PM PDT 24
Finished Mar 19 03:18:31 PM PDT 24
Peak memory 207272 kb
Host smart-ce1adbde-9f08-46dc-bd52-82641f738020
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866235559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_bit_bash.3866235559
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.2135561540
Short name T90
Test name
Test status
Simulation time 77545596 ps
CPU time 1.42 seconds
Started Mar 19 03:18:16 PM PDT 24
Finished Mar 19 03:18:18 PM PDT 24
Peak memory 207360 kb
Host smart-c7f2115a-078e-4492-bf97-a09ec176b747
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135561540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_hw_reset.2135561540
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.3733536892
Short name T1064
Test name
Test status
Simulation time 55046625 ps
CPU time 3.74 seconds
Started Mar 19 03:18:18 PM PDT 24
Finished Mar 19 03:18:22 PM PDT 24
Peak memory 217204 kb
Host smart-89d967c9-8785-43da-8148-e678f5256529
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733536892 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.3733536892
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.66859095
Short name T1056
Test name
Test status
Simulation time 95556098 ps
CPU time 2.61 seconds
Started Mar 19 03:18:41 PM PDT 24
Finished Mar 19 03:18:45 PM PDT 24
Peak memory 207212 kb
Host smart-7e442b30-8482-4697-b6ec-67a48691140b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66859095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.66859095
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.1184243473
Short name T1012
Test name
Test status
Simulation time 19449425 ps
CPU time 0.69 seconds
Started Mar 19 03:18:43 PM PDT 24
Finished Mar 19 03:18:44 PM PDT 24
Peak memory 203684 kb
Host smart-ae98e2f8-5224-4be4-b444-18a9ad5f2b96
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184243473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.1
184243473
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.2774211205
Short name T1054
Test name
Test status
Simulation time 180410071 ps
CPU time 1.64 seconds
Started Mar 19 03:18:31 PM PDT 24
Finished Mar 19 03:18:33 PM PDT 24
Peak memory 215512 kb
Host smart-4a339d71-66fd-4d9f-b3ae-b712b7c62e08
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774211205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi
_device_mem_partial_access.2774211205
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.3893775904
Short name T1029
Test name
Test status
Simulation time 124071225 ps
CPU time 0.65 seconds
Started Mar 19 03:18:17 PM PDT 24
Finished Mar 19 03:18:18 PM PDT 24
Peak memory 203628 kb
Host smart-ff5ef28a-e88a-4539-824b-d8562b4de495
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893775904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_me
m_walk.3893775904
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.3792175149
Short name T1094
Test name
Test status
Simulation time 154964665 ps
CPU time 4.11 seconds
Started Mar 19 03:18:19 PM PDT 24
Finished Mar 19 03:18:23 PM PDT 24
Peak memory 215540 kb
Host smart-a12747b2-bb20-4642-87a7-69bd91e2d347
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792175149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.s
pi_device_same_csr_outstanding.3792175149
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.3350603692
Short name T115
Test name
Test status
Simulation time 182644738 ps
CPU time 4.53 seconds
Started Mar 19 03:18:14 PM PDT 24
Finished Mar 19 03:18:19 PM PDT 24
Peak memory 215616 kb
Host smart-5524193c-829d-4e4c-ba5d-d40ce1c73828
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350603692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.3
350603692
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.2931555491
Short name T104
Test name
Test status
Simulation time 288008915 ps
CPU time 7.91 seconds
Started Mar 19 03:18:13 PM PDT 24
Finished Mar 19 03:18:22 PM PDT 24
Peak memory 215644 kb
Host smart-5559946d-b120-4698-92b0-fff0cfc62298
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931555491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.2931555491
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.1631169977
Short name T1112
Test name
Test status
Simulation time 391243801 ps
CPU time 8.65 seconds
Started Mar 19 03:18:18 PM PDT 24
Finished Mar 19 03:18:27 PM PDT 24
Peak memory 207304 kb
Host smart-2f346309-eca4-4131-9ed5-3a2953417bcc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631169977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_aliasing.1631169977
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.4249895590
Short name T1113
Test name
Test status
Simulation time 1867222687 ps
CPU time 35.38 seconds
Started Mar 19 03:18:33 PM PDT 24
Finished Mar 19 03:19:09 PM PDT 24
Peak memory 207332 kb
Host smart-d5e585f2-f246-40db-b591-e3722f58363b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249895590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_bit_bash.4249895590
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.4134667410
Short name T92
Test name
Test status
Simulation time 97447999 ps
CPU time 1.5 seconds
Started Mar 19 03:18:21 PM PDT 24
Finished Mar 19 03:18:24 PM PDT 24
Peak memory 207164 kb
Host smart-cda136e7-3c43-4d8c-97a2-9e92affd86b6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134667410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_hw_reset.4134667410
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.3033667561
Short name T114
Test name
Test status
Simulation time 51537258 ps
CPU time 1.63 seconds
Started Mar 19 03:18:31 PM PDT 24
Finished Mar 19 03:18:33 PM PDT 24
Peak memory 215504 kb
Host smart-c7c041b0-6e92-4557-8a7a-0b611f9a1629
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033667561 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.3033667561
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.2338570225
Short name T1100
Test name
Test status
Simulation time 250511479 ps
CPU time 2.32 seconds
Started Mar 19 03:18:42 PM PDT 24
Finished Mar 19 03:18:45 PM PDT 24
Peak memory 215472 kb
Host smart-c98e592a-89f5-4ad7-b874-2c9b675329d2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338570225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.2
338570225
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.850312088
Short name T1032
Test name
Test status
Simulation time 17426803 ps
CPU time 0.73 seconds
Started Mar 19 03:18:25 PM PDT 24
Finished Mar 19 03:18:26 PM PDT 24
Peak memory 203640 kb
Host smart-ff6dbe1a-a239-4377-9113-ce5c7fd7461d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850312088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.850312088
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.3348308356
Short name T131
Test name
Test status
Simulation time 73346353 ps
CPU time 2.23 seconds
Started Mar 19 03:18:45 PM PDT 24
Finished Mar 19 03:18:47 PM PDT 24
Peak memory 215456 kb
Host smart-ced7aae5-597d-409b-a53e-751597ac2b54
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348308356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi
_device_mem_partial_access.3348308356
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.1420694072
Short name T1048
Test name
Test status
Simulation time 12529934 ps
CPU time 0.67 seconds
Started Mar 19 03:18:30 PM PDT 24
Finished Mar 19 03:18:31 PM PDT 24
Peak memory 203604 kb
Host smart-ba80f157-c81b-4581-9ffd-f6752d49b0e3
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420694072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_me
m_walk.1420694072
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.1002278978
Short name T1088
Test name
Test status
Simulation time 153220631 ps
CPU time 3.43 seconds
Started Mar 19 03:18:20 PM PDT 24
Finished Mar 19 03:18:23 PM PDT 24
Peak memory 215500 kb
Host smart-1a62a0cb-d5ba-4e89-b3de-79b8678ed010
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002278978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s
pi_device_same_csr_outstanding.1002278978
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.341440010
Short name T1063
Test name
Test status
Simulation time 50273347 ps
CPU time 1.6 seconds
Started Mar 19 03:18:18 PM PDT 24
Finished Mar 19 03:18:19 PM PDT 24
Peak memory 215628 kb
Host smart-da78bf7c-3761-4e08-a1c4-1182a6f1ebca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341440010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.341440010
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.2327218893
Short name T180
Test name
Test status
Simulation time 1008738298 ps
CPU time 22.51 seconds
Started Mar 19 03:18:15 PM PDT 24
Finished Mar 19 03:18:37 PM PDT 24
Peak memory 215560 kb
Host smart-43f46602-3e0b-4380-a5b4-c2e8ddf5399d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327218893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device
_tl_intg_err.2327218893
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.1825634487
Short name T151
Test name
Test status
Simulation time 93016568 ps
CPU time 2.6 seconds
Started Mar 19 03:18:30 PM PDT 24
Finished Mar 19 03:18:32 PM PDT 24
Peak memory 216736 kb
Host smart-61751288-9cb1-4232-98e6-1a5764f03077
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825634487 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.1825634487
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.4184978492
Short name T1033
Test name
Test status
Simulation time 176892776 ps
CPU time 1.13 seconds
Started Mar 19 03:18:29 PM PDT 24
Finished Mar 19 03:18:31 PM PDT 24
Peak memory 215516 kb
Host smart-e120ddda-beb6-4e59-8a63-bbd3ed4ee0cf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184978492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.
4184978492
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.548029810
Short name T1023
Test name
Test status
Simulation time 11852318 ps
CPU time 0.69 seconds
Started Mar 19 03:18:29 PM PDT 24
Finished Mar 19 03:18:30 PM PDT 24
Peak memory 203648 kb
Host smart-c5208764-a9c2-4e55-bf4d-fdd14d88ebd0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548029810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.548029810
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.3361295544
Short name T1031
Test name
Test status
Simulation time 290016085 ps
CPU time 4.17 seconds
Started Mar 19 03:18:37 PM PDT 24
Finished Mar 19 03:18:42 PM PDT 24
Peak memory 215844 kb
Host smart-80d9b2a5-d1c0-4bbd-b4e4-4fede1d5adfe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361295544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
spi_device_same_csr_outstanding.3361295544
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.373962188
Short name T181
Test name
Test status
Simulation time 8427301009 ps
CPU time 14.94 seconds
Started Mar 19 03:18:26 PM PDT 24
Finished Mar 19 03:18:41 PM PDT 24
Peak memory 215592 kb
Host smart-618f2723-e00a-451f-91ba-45b59dcc7261
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373962188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device
_tl_intg_err.373962188
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.723722913
Short name T1079
Test name
Test status
Simulation time 102126932 ps
CPU time 2.13 seconds
Started Mar 19 03:18:40 PM PDT 24
Finished Mar 19 03:18:43 PM PDT 24
Peak memory 215620 kb
Host smart-9198d766-1354-4df4-8519-e5b775305258
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723722913 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.723722913
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.287999108
Short name T130
Test name
Test status
Simulation time 102780101 ps
CPU time 1.86 seconds
Started Mar 19 03:18:31 PM PDT 24
Finished Mar 19 03:18:33 PM PDT 24
Peak memory 207252 kb
Host smart-01398da6-0f13-4b83-8c93-30675b134115
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287999108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.287999108
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.2165499739
Short name T1035
Test name
Test status
Simulation time 19796066 ps
CPU time 0.68 seconds
Started Mar 19 03:18:29 PM PDT 24
Finished Mar 19 03:18:30 PM PDT 24
Peak memory 204028 kb
Host smart-4abb8119-316c-43f1-b340-4fe94fde3af1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165499739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.
2165499739
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.2831723943
Short name T998
Test name
Test status
Simulation time 55275154 ps
CPU time 3.19 seconds
Started Mar 19 03:18:40 PM PDT 24
Finished Mar 19 03:18:44 PM PDT 24
Peak memory 215484 kb
Host smart-8a571128-2635-4fbb-a95c-4c51eec998be
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831723943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
spi_device_same_csr_outstanding.2831723943
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.1656227072
Short name T1074
Test name
Test status
Simulation time 99643948 ps
CPU time 2.62 seconds
Started Mar 19 03:18:38 PM PDT 24
Finished Mar 19 03:18:41 PM PDT 24
Peak memory 215768 kb
Host smart-e233bd7e-af88-44f5-82ab-c2f46ed4d03e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656227072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.
1656227072
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.4131420929
Short name T102
Test name
Test status
Simulation time 937438307 ps
CPU time 2.78 seconds
Started Mar 19 03:18:38 PM PDT 24
Finished Mar 19 03:18:42 PM PDT 24
Peak memory 216680 kb
Host smart-e8647297-ee20-4742-882f-4510ee34268c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131420929 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.4131420929
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.4104638806
Short name T149
Test name
Test status
Simulation time 52255914 ps
CPU time 1.39 seconds
Started Mar 19 03:18:48 PM PDT 24
Finished Mar 19 03:18:50 PM PDT 24
Peak memory 207204 kb
Host smart-206b960b-3e40-4db4-80e1-f30d2a9e6de6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104638806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.
4104638806
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.3174562825
Short name T1007
Test name
Test status
Simulation time 11363210 ps
CPU time 0.73 seconds
Started Mar 19 03:18:44 PM PDT 24
Finished Mar 19 03:18:45 PM PDT 24
Peak memory 203692 kb
Host smart-fc0d4eb0-5d7c-45bd-a030-4083029e868a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174562825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.
3174562825
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.317019333
Short name T1060
Test name
Test status
Simulation time 165426715 ps
CPU time 2.83 seconds
Started Mar 19 03:18:49 PM PDT 24
Finished Mar 19 03:18:52 PM PDT 24
Peak memory 215536 kb
Host smart-247bf3cd-2182-4745-a4f9-6c8e9dcdad8e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317019333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.s
pi_device_same_csr_outstanding.317019333
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.3432730943
Short name T1107
Test name
Test status
Simulation time 481418128 ps
CPU time 3.49 seconds
Started Mar 19 03:18:48 PM PDT 24
Finished Mar 19 03:18:52 PM PDT 24
Peak memory 215644 kb
Host smart-a269120e-a866-4163-802e-c6bb16d2f91e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432730943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.
3432730943
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.465589610
Short name T1093
Test name
Test status
Simulation time 290182875 ps
CPU time 8.11 seconds
Started Mar 19 03:18:47 PM PDT 24
Finished Mar 19 03:18:56 PM PDT 24
Peak memory 216212 kb
Host smart-c97494d9-9789-4100-9215-19fb08561690
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465589610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device
_tl_intg_err.465589610
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.4284514118
Short name T117
Test name
Test status
Simulation time 580840961 ps
CPU time 3.65 seconds
Started Mar 19 03:18:46 PM PDT 24
Finished Mar 19 03:18:50 PM PDT 24
Peak memory 217308 kb
Host smart-d3934134-49da-44c6-9324-61a8598dbcb6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284514118 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.4284514118
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.111001161
Short name T123
Test name
Test status
Simulation time 226955623 ps
CPU time 2.6 seconds
Started Mar 19 03:18:45 PM PDT 24
Finished Mar 19 03:18:48 PM PDT 24
Peak memory 219244 kb
Host smart-a0d5eb1a-b3bd-4da6-a10b-b7f6dd9f5f5d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111001161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.111001161
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.1248862662
Short name T1089
Test name
Test status
Simulation time 148783753 ps
CPU time 0.73 seconds
Started Mar 19 03:18:38 PM PDT 24
Finished Mar 19 03:18:40 PM PDT 24
Peak memory 203716 kb
Host smart-d4db00b8-d127-48b6-b2ce-8d2217b9baa6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248862662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.
1248862662
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.161716905
Short name T1009
Test name
Test status
Simulation time 50520664 ps
CPU time 1.79 seconds
Started Mar 19 03:18:46 PM PDT 24
Finished Mar 19 03:18:47 PM PDT 24
Peak memory 215560 kb
Host smart-12a64b0f-ef97-4f51-939f-dd9aff264f63
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161716905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.s
pi_device_same_csr_outstanding.161716905
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.1071151243
Short name T112
Test name
Test status
Simulation time 228699142 ps
CPU time 4.45 seconds
Started Mar 19 03:18:47 PM PDT 24
Finished Mar 19 03:18:52 PM PDT 24
Peak memory 215624 kb
Host smart-a312e7e6-7429-474a-9fde-d99733c7c54a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071151243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.
1071151243
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.3988217101
Short name T119
Test name
Test status
Simulation time 124158707 ps
CPU time 3.14 seconds
Started Mar 19 03:18:45 PM PDT 24
Finished Mar 19 03:18:49 PM PDT 24
Peak memory 216508 kb
Host smart-5698accf-8d4e-4f61-859e-aa6eae6f1904
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988217101 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.3988217101
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.1742455945
Short name T1040
Test name
Test status
Simulation time 48856972 ps
CPU time 1.43 seconds
Started Mar 19 03:18:39 PM PDT 24
Finished Mar 19 03:18:41 PM PDT 24
Peak memory 215500 kb
Host smart-cc0dbb85-c367-4447-97f7-5fa20c7675d9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742455945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.
1742455945
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.2798224430
Short name T1077
Test name
Test status
Simulation time 12894739 ps
CPU time 0.76 seconds
Started Mar 19 03:18:38 PM PDT 24
Finished Mar 19 03:18:40 PM PDT 24
Peak memory 203728 kb
Host smart-1cefac26-54af-49b4-866f-2c655d59c292
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798224430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.
2798224430
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.4033142170
Short name T1028
Test name
Test status
Simulation time 362590955 ps
CPU time 3.79 seconds
Started Mar 19 03:18:43 PM PDT 24
Finished Mar 19 03:18:47 PM PDT 24
Peak memory 215564 kb
Host smart-b67124d8-6448-4206-9f5f-b596d663512a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033142170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
spi_device_same_csr_outstanding.4033142170
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.2806508769
Short name T110
Test name
Test status
Simulation time 722740929 ps
CPU time 5.55 seconds
Started Mar 19 03:18:38 PM PDT 24
Finished Mar 19 03:18:44 PM PDT 24
Peak memory 215740 kb
Host smart-29e123de-7996-40d9-bc3a-9c0286cda6b1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806508769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.
2806508769
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.428603621
Short name T100
Test name
Test status
Simulation time 119470576 ps
CPU time 7.04 seconds
Started Mar 19 03:18:38 PM PDT 24
Finished Mar 19 03:18:47 PM PDT 24
Peak memory 215588 kb
Host smart-0c54406e-dc32-45bb-b1a7-b61829241d02
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428603621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device
_tl_intg_err.428603621
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.1485370487
Short name T118
Test name
Test status
Simulation time 152990004 ps
CPU time 3.07 seconds
Started Mar 19 03:18:51 PM PDT 24
Finished Mar 19 03:18:55 PM PDT 24
Peak memory 217920 kb
Host smart-39732255-53b8-49da-b294-22777a9f5681
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485370487 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.1485370487
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.4280328187
Short name T1078
Test name
Test status
Simulation time 42245448 ps
CPU time 1.37 seconds
Started Mar 19 03:18:38 PM PDT 24
Finished Mar 19 03:18:40 PM PDT 24
Peak memory 207356 kb
Host smart-266607bd-b160-4290-9475-1bd95969014e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280328187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.
4280328187
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.4132300770
Short name T1067
Test name
Test status
Simulation time 40906712 ps
CPU time 0.69 seconds
Started Mar 19 03:18:42 PM PDT 24
Finished Mar 19 03:18:43 PM PDT 24
Peak memory 203672 kb
Host smart-3f4ff109-1c45-49a9-93cc-412932f7daa4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132300770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.
4132300770
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.3504892332
Short name T1024
Test name
Test status
Simulation time 109669889 ps
CPU time 2.94 seconds
Started Mar 19 03:18:49 PM PDT 24
Finished Mar 19 03:18:52 PM PDT 24
Peak memory 215596 kb
Host smart-4cf62c18-e502-4670-ba09-6cd75b6dc3df
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504892332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
spi_device_same_csr_outstanding.3504892332
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.1579903981
Short name T107
Test name
Test status
Simulation time 107923818 ps
CPU time 3.42 seconds
Started Mar 19 03:18:41 PM PDT 24
Finished Mar 19 03:18:45 PM PDT 24
Peak memory 215496 kb
Host smart-9d84249d-be8c-4358-acc8-2b8bf7569e42
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579903981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.
1579903981
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.2319318935
Short name T105
Test name
Test status
Simulation time 3002036723 ps
CPU time 22.08 seconds
Started Mar 19 03:18:46 PM PDT 24
Finished Mar 19 03:19:09 PM PDT 24
Peak memory 215704 kb
Host smart-4d9a964d-1ef8-4d47-bb7a-bec3f64d6bec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319318935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_devic
e_tl_intg_err.2319318935
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.1595191428
Short name T1110
Test name
Test status
Simulation time 51271332 ps
CPU time 1.77 seconds
Started Mar 19 03:18:45 PM PDT 24
Finished Mar 19 03:18:46 PM PDT 24
Peak memory 216612 kb
Host smart-15ca2328-0876-4d15-94f8-184ab459cba7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595191428 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.1595191428
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.1914872971
Short name T1070
Test name
Test status
Simulation time 38613150 ps
CPU time 1.26 seconds
Started Mar 19 03:18:41 PM PDT 24
Finished Mar 19 03:18:43 PM PDT 24
Peak memory 207280 kb
Host smart-a62ac417-5dd8-416a-917c-871c79426168
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914872971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.
1914872971
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.928640737
Short name T1099
Test name
Test status
Simulation time 31531731 ps
CPU time 0.7 seconds
Started Mar 19 03:18:46 PM PDT 24
Finished Mar 19 03:18:47 PM PDT 24
Peak memory 203640 kb
Host smart-3cf2deeb-e8fe-419e-9447-2a02c261b547
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928640737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.928640737
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.4087914592
Short name T1010
Test name
Test status
Simulation time 229097111 ps
CPU time 3.67 seconds
Started Mar 19 03:18:48 PM PDT 24
Finished Mar 19 03:18:52 PM PDT 24
Peak memory 215540 kb
Host smart-0c0c60be-05b8-4c32-9434-6d26dbd6dd0b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087914592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
spi_device_same_csr_outstanding.4087914592
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.2634024039
Short name T1102
Test name
Test status
Simulation time 122975685 ps
CPU time 4.17 seconds
Started Mar 19 03:18:46 PM PDT 24
Finished Mar 19 03:18:50 PM PDT 24
Peak memory 215548 kb
Host smart-d95ac017-e6f5-4dca-95f6-1e586e9991ad
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634024039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.
2634024039
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.2138991704
Short name T1104
Test name
Test status
Simulation time 676388548 ps
CPU time 13.55 seconds
Started Mar 19 03:18:47 PM PDT 24
Finished Mar 19 03:19:06 PM PDT 24
Peak memory 215592 kb
Host smart-196214b3-2ac5-4a1b-a590-05d6100f3e6d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138991704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_devic
e_tl_intg_err.2138991704
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.4191549713
Short name T1103
Test name
Test status
Simulation time 222416192 ps
CPU time 4.18 seconds
Started Mar 19 03:18:43 PM PDT 24
Finished Mar 19 03:18:47 PM PDT 24
Peak memory 217524 kb
Host smart-4ee793ec-51b2-451d-b4c4-a724ace814bd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191549713 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.4191549713
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.3185107952
Short name T128
Test name
Test status
Simulation time 18331814 ps
CPU time 1.21 seconds
Started Mar 19 03:18:41 PM PDT 24
Finished Mar 19 03:18:43 PM PDT 24
Peak memory 207240 kb
Host smart-771f9039-4d50-415b-8e50-6a35e6ebfbf3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185107952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.
3185107952
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.658435977
Short name T1013
Test name
Test status
Simulation time 55595164 ps
CPU time 0.72 seconds
Started Mar 19 03:18:47 PM PDT 24
Finished Mar 19 03:18:48 PM PDT 24
Peak memory 204008 kb
Host smart-f72aa6dc-789e-4065-8960-0fc68e22f230
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658435977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.658435977
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.431818336
Short name T1043
Test name
Test status
Simulation time 603710605 ps
CPU time 3.22 seconds
Started Mar 19 03:18:38 PM PDT 24
Finished Mar 19 03:18:43 PM PDT 24
Peak memory 215488 kb
Host smart-d58c2446-67ff-4401-9cd4-ae70c041032c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431818336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.s
pi_device_same_csr_outstanding.431818336
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.1889690558
Short name T116
Test name
Test status
Simulation time 67282215 ps
CPU time 1.9 seconds
Started Mar 19 03:18:51 PM PDT 24
Finished Mar 19 03:18:53 PM PDT 24
Peak memory 215616 kb
Host smart-301081e8-8858-4890-a282-5bdf6fb625f6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889690558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.
1889690558
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.3218375703
Short name T178
Test name
Test status
Simulation time 622036335 ps
CPU time 11.44 seconds
Started Mar 19 03:18:49 PM PDT 24
Finished Mar 19 03:19:01 PM PDT 24
Peak memory 215416 kb
Host smart-98a697d5-d78a-411d-9674-c0e1aa2a0a10
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218375703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_devic
e_tl_intg_err.3218375703
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.2872172681
Short name T1071
Test name
Test status
Simulation time 177747782 ps
CPU time 1.74 seconds
Started Mar 19 03:18:38 PM PDT 24
Finished Mar 19 03:18:41 PM PDT 24
Peak memory 215656 kb
Host smart-2c52a9b2-c34e-48a6-bc7a-dd0ff73ae9e9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872172681 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.2872172681
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.291062525
Short name T1047
Test name
Test status
Simulation time 60153531 ps
CPU time 1.98 seconds
Started Mar 19 03:18:39 PM PDT 24
Finished Mar 19 03:18:42 PM PDT 24
Peak memory 207244 kb
Host smart-b78d687c-698b-4492-8597-77cdbd56eb27
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291062525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.291062525
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.1395634958
Short name T1105
Test name
Test status
Simulation time 242880194 ps
CPU time 0.73 seconds
Started Mar 19 03:18:45 PM PDT 24
Finished Mar 19 03:18:46 PM PDT 24
Peak memory 203980 kb
Host smart-b3763773-362e-49f8-b771-40d1b96851e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395634958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.
1395634958
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.4200114773
Short name T1061
Test name
Test status
Simulation time 274165633 ps
CPU time 1.75 seconds
Started Mar 19 03:18:43 PM PDT 24
Finished Mar 19 03:18:45 PM PDT 24
Peak memory 207292 kb
Host smart-1a0b64dd-dd0d-4d2c-8892-3659caee74d3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200114773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
spi_device_same_csr_outstanding.4200114773
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.2821492005
Short name T99
Test name
Test status
Simulation time 224044980 ps
CPU time 5.13 seconds
Started Mar 19 03:18:41 PM PDT 24
Finished Mar 19 03:18:47 PM PDT 24
Peak memory 215504 kb
Host smart-6f71aad5-7c24-4e10-99e8-10236e00964f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821492005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.
2821492005
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.2633518610
Short name T1081
Test name
Test status
Simulation time 2582543611 ps
CPU time 13.72 seconds
Started Mar 19 03:18:39 PM PDT 24
Finished Mar 19 03:18:54 PM PDT 24
Peak memory 223696 kb
Host smart-1daf4d44-04c2-412c-a487-9593586cf637
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633518610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_devic
e_tl_intg_err.2633518610
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.1931222634
Short name T109
Test name
Test status
Simulation time 1210558315 ps
CPU time 2.77 seconds
Started Mar 19 03:18:42 PM PDT 24
Finished Mar 19 03:18:45 PM PDT 24
Peak memory 216588 kb
Host smart-55df76c2-b69c-4eff-b85f-137a70861fd6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931222634 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.1931222634
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.3593871243
Short name T1051
Test name
Test status
Simulation time 422296833 ps
CPU time 2.7 seconds
Started Mar 19 03:18:46 PM PDT 24
Finished Mar 19 03:18:49 PM PDT 24
Peak memory 215396 kb
Host smart-d97c4459-fd79-4e70-8be3-d8f3ddf92d03
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593871243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.
3593871243
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.3722163853
Short name T1037
Test name
Test status
Simulation time 16843990 ps
CPU time 0.73 seconds
Started Mar 19 03:18:48 PM PDT 24
Finished Mar 19 03:18:49 PM PDT 24
Peak memory 203672 kb
Host smart-d8805218-166a-4d8a-8d89-515cbd4a4f3a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722163853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.
3722163853
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.1391972281
Short name T1055
Test name
Test status
Simulation time 181476668 ps
CPU time 4.02 seconds
Started Mar 19 03:18:49 PM PDT 24
Finished Mar 19 03:18:53 PM PDT 24
Peak memory 215496 kb
Host smart-7a503bae-26bc-425c-9d40-0243a8b838aa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391972281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
spi_device_same_csr_outstanding.1391972281
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.1219332506
Short name T1069
Test name
Test status
Simulation time 453835778 ps
CPU time 3.56 seconds
Started Mar 19 03:18:46 PM PDT 24
Finished Mar 19 03:18:50 PM PDT 24
Peak memory 215600 kb
Host smart-298d12dc-88b3-447f-b1a2-0dac6b7b780e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219332506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.
1219332506
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.3246781397
Short name T120
Test name
Test status
Simulation time 215931635 ps
CPU time 12.68 seconds
Started Mar 19 03:18:37 PM PDT 24
Finished Mar 19 03:18:51 PM PDT 24
Peak memory 215560 kb
Host smart-6f67b719-c73b-4356-9f01-93b1853efbc3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246781397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_devic
e_tl_intg_err.3246781397
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.373876296
Short name T1066
Test name
Test status
Simulation time 456456757 ps
CPU time 8.02 seconds
Started Mar 19 03:18:19 PM PDT 24
Finished Mar 19 03:18:27 PM PDT 24
Peak memory 207340 kb
Host smart-e295f69e-f80f-4e70-9ef7-79b4a6bb7c0f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373876296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr
_aliasing.373876296
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.3965419536
Short name T1006
Test name
Test status
Simulation time 1276371969 ps
CPU time 24.66 seconds
Started Mar 19 03:18:18 PM PDT 24
Finished Mar 19 03:18:43 PM PDT 24
Peak memory 207152 kb
Host smart-b98bef5e-ecc5-48a4-bd3e-82b8cd7b7229
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965419536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_bit_bash.3965419536
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.3777660732
Short name T1027
Test name
Test status
Simulation time 93744502 ps
CPU time 1.6 seconds
Started Mar 19 03:18:25 PM PDT 24
Finished Mar 19 03:18:27 PM PDT 24
Peak memory 215548 kb
Host smart-1d6239f3-f1da-484c-80f4-20d7e4f11a9c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777660732 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.3777660732
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.1306056855
Short name T1062
Test name
Test status
Simulation time 95461098 ps
CPU time 2.73 seconds
Started Mar 19 03:18:21 PM PDT 24
Finished Mar 19 03:18:24 PM PDT 24
Peak memory 215560 kb
Host smart-3742c99d-8592-4233-bda6-3032a9ec388b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306056855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.1
306056855
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.3204960626
Short name T1022
Test name
Test status
Simulation time 18696809 ps
CPU time 0.75 seconds
Started Mar 19 03:18:21 PM PDT 24
Finished Mar 19 03:18:23 PM PDT 24
Peak memory 203916 kb
Host smart-56c33a94-9c21-4654-914e-69515b85c782
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204960626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.3
204960626
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.1141772896
Short name T124
Test name
Test status
Simulation time 19885543 ps
CPU time 1.2 seconds
Started Mar 19 03:18:20 PM PDT 24
Finished Mar 19 03:18:22 PM PDT 24
Peak memory 215532 kb
Host smart-791c7348-d2aa-418f-a4a0-1f4d298c47dd
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141772896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi
_device_mem_partial_access.1141772896
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.766521397
Short name T1095
Test name
Test status
Simulation time 30439948 ps
CPU time 0.65 seconds
Started Mar 19 03:18:21 PM PDT 24
Finished Mar 19 03:18:22 PM PDT 24
Peak memory 203592 kb
Host smart-7c7083e3-23b3-4d4e-99e5-28ef1f3a20b4
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766521397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_mem
_walk.766521397
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.3809464481
Short name T990
Test name
Test status
Simulation time 296416763 ps
CPU time 4.08 seconds
Started Mar 19 03:18:20 PM PDT 24
Finished Mar 19 03:18:24 PM PDT 24
Peak memory 215544 kb
Host smart-f6da5131-8a93-4ab1-afb5-21ea895f0444
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809464481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s
pi_device_same_csr_outstanding.3809464481
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.2005970237
Short name T1111
Test name
Test status
Simulation time 375516768 ps
CPU time 2.79 seconds
Started Mar 19 03:18:32 PM PDT 24
Finished Mar 19 03:18:35 PM PDT 24
Peak memory 215688 kb
Host smart-b9ab3000-6a4e-4be4-a266-49dfff5778e0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005970237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.2
005970237
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.4006116158
Short name T182
Test name
Test status
Simulation time 204024331 ps
CPU time 13.3 seconds
Started Mar 19 03:18:18 PM PDT 24
Finished Mar 19 03:18:32 PM PDT 24
Peak memory 215532 kb
Host smart-25100ecf-f793-4383-a8f5-3df75bc52570
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006116158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device
_tl_intg_err.4006116158
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.1637127057
Short name T1011
Test name
Test status
Simulation time 15031879 ps
CPU time 0.67 seconds
Started Mar 19 03:18:46 PM PDT 24
Finished Mar 19 03:18:47 PM PDT 24
Peak memory 204008 kb
Host smart-d359f6be-1e2d-433b-ac8a-4ebc4fd3b1f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637127057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.
1637127057
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.1003349057
Short name T1039
Test name
Test status
Simulation time 20992639 ps
CPU time 0.71 seconds
Started Mar 19 03:18:48 PM PDT 24
Finished Mar 19 03:18:49 PM PDT 24
Peak memory 203688 kb
Host smart-09a344e0-ddc4-4cf9-a388-c41f8e7c7b47
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003349057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.
1003349057
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.90481807
Short name T1016
Test name
Test status
Simulation time 17640091 ps
CPU time 0.79 seconds
Started Mar 19 03:18:36 PM PDT 24
Finished Mar 19 03:18:37 PM PDT 24
Peak memory 203672 kb
Host smart-83e28b4f-8c32-44b0-9afc-a752af026f79
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90481807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.90481807
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.3974424730
Short name T999
Test name
Test status
Simulation time 203548850 ps
CPU time 0.73 seconds
Started Mar 19 03:18:45 PM PDT 24
Finished Mar 19 03:18:46 PM PDT 24
Peak memory 203668 kb
Host smart-41262bc3-6f15-4e9a-ab3b-2b758a95555a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974424730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.
3974424730
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.4235517338
Short name T1083
Test name
Test status
Simulation time 22584761 ps
CPU time 0.7 seconds
Started Mar 19 03:18:45 PM PDT 24
Finished Mar 19 03:18:46 PM PDT 24
Peak memory 203964 kb
Host smart-c46371b3-e511-4f33-b6c4-b0cc6ef0072a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235517338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.
4235517338
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.3597797674
Short name T1014
Test name
Test status
Simulation time 10714382 ps
CPU time 0.69 seconds
Started Mar 19 03:18:41 PM PDT 24
Finished Mar 19 03:18:43 PM PDT 24
Peak memory 203996 kb
Host smart-d9d5a173-436d-46a0-a19c-bafb5d0ae4bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597797674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.
3597797674
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.469612651
Short name T1091
Test name
Test status
Simulation time 18687650 ps
CPU time 0.78 seconds
Started Mar 19 03:18:48 PM PDT 24
Finished Mar 19 03:18:50 PM PDT 24
Peak memory 203684 kb
Host smart-b399fabe-95cd-47d1-b12b-ab1b2d984a3f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469612651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.469612651
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.923846162
Short name T1008
Test name
Test status
Simulation time 19421545 ps
CPU time 0.79 seconds
Started Mar 19 03:18:37 PM PDT 24
Finished Mar 19 03:18:39 PM PDT 24
Peak memory 204036 kb
Host smart-8b3bce08-b7a1-47ed-9c9d-bed53b164e3b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923846162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.923846162
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.71205936
Short name T1003
Test name
Test status
Simulation time 17080813 ps
CPU time 0.73 seconds
Started Mar 19 03:18:46 PM PDT 24
Finished Mar 19 03:18:47 PM PDT 24
Peak memory 203668 kb
Host smart-cd68296b-adf2-44f1-90dc-605f00d0b832
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71205936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.71205936
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.2757348269
Short name T997
Test name
Test status
Simulation time 20499684 ps
CPU time 0.8 seconds
Started Mar 19 03:18:40 PM PDT 24
Finished Mar 19 03:18:42 PM PDT 24
Peak memory 204016 kb
Host smart-5aaf3c89-7aa7-47fb-9e7f-dc7df3bf4837
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757348269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
2757348269
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.89589682
Short name T125
Test name
Test status
Simulation time 1271582916 ps
CPU time 7.8 seconds
Started Mar 19 03:18:29 PM PDT 24
Finished Mar 19 03:18:37 PM PDT 24
Peak memory 207276 kb
Host smart-9c8b3f22-dda3-48c3-a7dc-6f67598224a4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89589682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_
aliasing.89589682
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.1848116848
Short name T1001
Test name
Test status
Simulation time 3749999012 ps
CPU time 38.06 seconds
Started Mar 19 03:18:43 PM PDT 24
Finished Mar 19 03:19:21 PM PDT 24
Peak memory 216100 kb
Host smart-d2e12600-4092-4b55-b5f5-05fd7d14e5d6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848116848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_bit_bash.1848116848
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.3650588712
Short name T89
Test name
Test status
Simulation time 23689360 ps
CPU time 1.31 seconds
Started Mar 19 03:18:41 PM PDT 24
Finished Mar 19 03:18:43 PM PDT 24
Peak memory 216548 kb
Host smart-7abbbdec-fb3f-4993-ae41-f22ae9371157
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650588712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_hw_reset.3650588712
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.2608280453
Short name T1108
Test name
Test status
Simulation time 83445702 ps
CPU time 2.89 seconds
Started Mar 19 03:18:17 PM PDT 24
Finished Mar 19 03:18:20 PM PDT 24
Peak memory 217188 kb
Host smart-fd4940a3-f5ef-4290-ab2f-22450af4754c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608280453 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.2608280453
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.2680040454
Short name T122
Test name
Test status
Simulation time 34209099 ps
CPU time 2.41 seconds
Started Mar 19 03:18:18 PM PDT 24
Finished Mar 19 03:18:21 PM PDT 24
Peak memory 215368 kb
Host smart-6c692551-2bb4-4dda-80de-9116c9243fb7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680040454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.2
680040454
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.25725365
Short name T1096
Test name
Test status
Simulation time 18817669 ps
CPU time 0.69 seconds
Started Mar 19 03:18:46 PM PDT 24
Finished Mar 19 03:18:46 PM PDT 24
Peak memory 203680 kb
Host smart-c1b21dfe-e851-46ff-918f-1d94ce8cd2a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25725365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.25725365
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.2338878926
Short name T1057
Test name
Test status
Simulation time 52245652 ps
CPU time 1.91 seconds
Started Mar 19 03:18:21 PM PDT 24
Finished Mar 19 03:18:23 PM PDT 24
Peak memory 215504 kb
Host smart-d53eb4a3-abd8-4e76-8290-133e9988c3b8
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338878926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi
_device_mem_partial_access.2338878926
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.449941718
Short name T992
Test name
Test status
Simulation time 10306075 ps
CPU time 0.64 seconds
Started Mar 19 03:18:20 PM PDT 24
Finished Mar 19 03:18:21 PM PDT 24
Peak memory 203556 kb
Host smart-89fc2795-8055-4fb5-800d-01278d77ead7
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449941718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_mem
_walk.449941718
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.2488507024
Short name T1065
Test name
Test status
Simulation time 74279276 ps
CPU time 1.83 seconds
Started Mar 19 03:18:41 PM PDT 24
Finished Mar 19 03:18:43 PM PDT 24
Peak memory 215480 kb
Host smart-db341150-aa28-4804-9857-1945add3e6f9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488507024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.s
pi_device_same_csr_outstanding.2488507024
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.1221702534
Short name T177
Test name
Test status
Simulation time 172692583 ps
CPU time 1.56 seconds
Started Mar 19 03:18:36 PM PDT 24
Finished Mar 19 03:18:38 PM PDT 24
Peak memory 215908 kb
Host smart-9a156f82-e79c-4e78-a6a3-b062e3862941
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221702534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.1
221702534
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.2137086979
Short name T1021
Test name
Test status
Simulation time 308035182 ps
CPU time 7.62 seconds
Started Mar 19 03:18:23 PM PDT 24
Finished Mar 19 03:18:32 PM PDT 24
Peak memory 215568 kb
Host smart-1bef1ae4-802c-4770-99cb-f52480b73092
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137086979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device
_tl_intg_err.2137086979
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.3944071049
Short name T1000
Test name
Test status
Simulation time 58787172 ps
CPU time 0.78 seconds
Started Mar 19 03:18:42 PM PDT 24
Finished Mar 19 03:18:44 PM PDT 24
Peak memory 203960 kb
Host smart-9666de15-a133-4abf-9e30-81330834f6bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944071049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.
3944071049
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.1902200110
Short name T1076
Test name
Test status
Simulation time 23435614 ps
CPU time 0.74 seconds
Started Mar 19 03:18:46 PM PDT 24
Finished Mar 19 03:18:46 PM PDT 24
Peak memory 203692 kb
Host smart-759bca7e-1ced-41da-bb27-6cdf92dab675
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902200110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.
1902200110
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.1664581694
Short name T1026
Test name
Test status
Simulation time 33917983 ps
CPU time 0.72 seconds
Started Mar 19 03:18:38 PM PDT 24
Finished Mar 19 03:18:40 PM PDT 24
Peak memory 203688 kb
Host smart-56e38b09-9a30-4b69-9216-482ea8ed1bd4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664581694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.
1664581694
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.1413724599
Short name T1046
Test name
Test status
Simulation time 65199845 ps
CPU time 0.69 seconds
Started Mar 19 03:18:38 PM PDT 24
Finished Mar 19 03:18:39 PM PDT 24
Peak memory 204012 kb
Host smart-f5e661e3-9c7c-43db-8b86-23202de9049a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413724599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.
1413724599
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.2694588675
Short name T1020
Test name
Test status
Simulation time 14141572 ps
CPU time 0.74 seconds
Started Mar 19 03:18:41 PM PDT 24
Finished Mar 19 03:18:43 PM PDT 24
Peak memory 203648 kb
Host smart-5280b411-77bc-4a97-b207-f0ba720a0573
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694588675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
2694588675
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.905180112
Short name T1072
Test name
Test status
Simulation time 61487403 ps
CPU time 0.77 seconds
Started Mar 19 03:18:39 PM PDT 24
Finished Mar 19 03:18:41 PM PDT 24
Peak memory 203652 kb
Host smart-26ce7fb8-adbd-413b-9a0a-9f44b569fe92
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905180112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.905180112
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.545768803
Short name T1109
Test name
Test status
Simulation time 40427005 ps
CPU time 0.72 seconds
Started Mar 19 03:18:43 PM PDT 24
Finished Mar 19 03:18:44 PM PDT 24
Peak memory 203668 kb
Host smart-ad349d8c-6fcd-42b4-bb9d-631cf9231cdd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545768803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.545768803
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.2222930938
Short name T1015
Test name
Test status
Simulation time 16143377 ps
CPU time 0.76 seconds
Started Mar 19 03:18:45 PM PDT 24
Finished Mar 19 03:18:46 PM PDT 24
Peak memory 203724 kb
Host smart-27543dc3-6b43-47d4-bdf7-a35144a6b856
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222930938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.
2222930938
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.3023794815
Short name T1036
Test name
Test status
Simulation time 13479668 ps
CPU time 0.74 seconds
Started Mar 19 03:18:52 PM PDT 24
Finished Mar 19 03:18:53 PM PDT 24
Peak memory 203668 kb
Host smart-ee0814a9-1c6b-4c2b-8d27-bba0fd8b3a72
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023794815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.
3023794815
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.2467440533
Short name T1049
Test name
Test status
Simulation time 16650571 ps
CPU time 0.77 seconds
Started Mar 19 03:18:49 PM PDT 24
Finished Mar 19 03:18:50 PM PDT 24
Peak memory 204016 kb
Host smart-1b3f6b5d-fc46-450c-9b5f-74b180917d20
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467440533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.
2467440533
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.768785910
Short name T1092
Test name
Test status
Simulation time 371672753 ps
CPU time 8.24 seconds
Started Mar 19 03:18:18 PM PDT 24
Finished Mar 19 03:18:26 PM PDT 24
Peak memory 215508 kb
Host smart-d6bc8442-09b5-47f0-a2f3-6c7b319e9c9c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768785910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr
_aliasing.768785910
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.2352816817
Short name T129
Test name
Test status
Simulation time 1862883133 ps
CPU time 36.59 seconds
Started Mar 19 03:18:29 PM PDT 24
Finished Mar 19 03:19:06 PM PDT 24
Peak memory 207612 kb
Host smart-7fab2d4b-ae4e-4be5-93b7-1cd5ec69cf66
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352816817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_bit_bash.2352816817
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.204347701
Short name T1101
Test name
Test status
Simulation time 34796079 ps
CPU time 1.19 seconds
Started Mar 19 03:18:16 PM PDT 24
Finished Mar 19 03:18:17 PM PDT 24
Peak memory 207372 kb
Host smart-0df3df52-3b69-40e8-a746-739ccda080e2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204347701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr
_hw_reset.204347701
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.1722631393
Short name T101
Test name
Test status
Simulation time 53794969 ps
CPU time 3.68 seconds
Started Mar 19 03:18:30 PM PDT 24
Finished Mar 19 03:18:34 PM PDT 24
Peak memory 217212 kb
Host smart-8718875a-585c-4f35-b450-0cca1b527ae1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722631393 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.1722631393
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.1113553009
Short name T994
Test name
Test status
Simulation time 98135432 ps
CPU time 2.58 seconds
Started Mar 19 03:18:30 PM PDT 24
Finished Mar 19 03:18:32 PM PDT 24
Peak memory 215780 kb
Host smart-f164a5a2-19ab-4ce4-8847-f2226486f632
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113553009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.1
113553009
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.3194587182
Short name T1080
Test name
Test status
Simulation time 11866050 ps
CPU time 0.71 seconds
Started Mar 19 03:18:21 PM PDT 24
Finished Mar 19 03:18:22 PM PDT 24
Peak memory 203688 kb
Host smart-d061c2a1-feb0-4e31-955f-f7d27c606358
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194587182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.3
194587182
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.113077333
Short name T1068
Test name
Test status
Simulation time 26123155 ps
CPU time 1.95 seconds
Started Mar 19 03:18:17 PM PDT 24
Finished Mar 19 03:18:19 PM PDT 24
Peak memory 215508 kb
Host smart-18c8a5dc-7921-4034-851b-980e7b326150
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113077333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_
device_mem_partial_access.113077333
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.4096821298
Short name T996
Test name
Test status
Simulation time 20240048 ps
CPU time 0.67 seconds
Started Mar 19 03:18:19 PM PDT 24
Finished Mar 19 03:18:20 PM PDT 24
Peak memory 203640 kb
Host smart-310669dc-98a6-4858-8896-f75f5acad08e
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096821298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.4096821298
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.1321067814
Short name T989
Test name
Test status
Simulation time 129562089 ps
CPU time 1.53 seconds
Started Mar 19 03:18:44 PM PDT 24
Finished Mar 19 03:18:45 PM PDT 24
Peak memory 207292 kb
Host smart-58208759-7397-47c2-bdf5-e840d660b853
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321067814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.s
pi_device_same_csr_outstanding.1321067814
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.2406970613
Short name T1087
Test name
Test status
Simulation time 585362575 ps
CPU time 3.02 seconds
Started Mar 19 03:18:31 PM PDT 24
Finished Mar 19 03:18:34 PM PDT 24
Peak memory 215592 kb
Host smart-ee5de195-0fbb-4500-8f08-fd69f61827b4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406970613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.2
406970613
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.3771605476
Short name T1059
Test name
Test status
Simulation time 215103127 ps
CPU time 12.91 seconds
Started Mar 19 03:18:18 PM PDT 24
Finished Mar 19 03:18:31 PM PDT 24
Peak memory 215556 kb
Host smart-4103ec71-ec53-4f9e-9053-2262a2fde2c5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771605476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device
_tl_intg_err.3771605476
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.375853600
Short name T1018
Test name
Test status
Simulation time 12816595 ps
CPU time 0.75 seconds
Started Mar 19 03:18:49 PM PDT 24
Finished Mar 19 03:18:50 PM PDT 24
Peak memory 203680 kb
Host smart-3569b903-d739-4aa8-b122-b8eade81ab0b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375853600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.375853600
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.1776260334
Short name T1002
Test name
Test status
Simulation time 20058731 ps
CPU time 0.7 seconds
Started Mar 19 03:18:48 PM PDT 24
Finished Mar 19 03:18:48 PM PDT 24
Peak memory 204036 kb
Host smart-ff9cddff-9291-4974-b26d-7de258587091
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776260334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.
1776260334
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.3746217690
Short name T1038
Test name
Test status
Simulation time 38149464 ps
CPU time 0.74 seconds
Started Mar 19 03:18:47 PM PDT 24
Finished Mar 19 03:18:48 PM PDT 24
Peak memory 203640 kb
Host smart-e86f4ddb-8ba4-4f2d-9658-f9be23a3dbbe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746217690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.
3746217690
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.4218054289
Short name T1085
Test name
Test status
Simulation time 14887697 ps
CPU time 0.74 seconds
Started Mar 19 03:18:49 PM PDT 24
Finished Mar 19 03:18:50 PM PDT 24
Peak memory 203900 kb
Host smart-0d126af1-ee39-4d7e-b2f5-53d37fd4285c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218054289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.
4218054289
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.276690707
Short name T1025
Test name
Test status
Simulation time 31785878 ps
CPU time 0.77 seconds
Started Mar 19 03:19:00 PM PDT 24
Finished Mar 19 03:19:01 PM PDT 24
Peak memory 203672 kb
Host smart-290a43fc-0a0f-4f6e-9a55-ec0e2d2952b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276690707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.276690707
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.1444356179
Short name T1050
Test name
Test status
Simulation time 19016175 ps
CPU time 0.72 seconds
Started Mar 19 03:18:49 PM PDT 24
Finished Mar 19 03:18:50 PM PDT 24
Peak memory 203984 kb
Host smart-1f69a21b-018a-4587-bef3-c52aa108867d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444356179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.
1444356179
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.1051553744
Short name T1041
Test name
Test status
Simulation time 42936083 ps
CPU time 0.72 seconds
Started Mar 19 03:18:51 PM PDT 24
Finished Mar 19 03:18:52 PM PDT 24
Peak memory 204032 kb
Host smart-47a83198-ed00-4f59-84ba-52f38783f102
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051553744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.
1051553744
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.3385577755
Short name T1034
Test name
Test status
Simulation time 26726987 ps
CPU time 0.7 seconds
Started Mar 19 03:18:48 PM PDT 24
Finished Mar 19 03:18:49 PM PDT 24
Peak memory 204024 kb
Host smart-0dc5e6c7-737a-44fd-afd0-21e528b2daf9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385577755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.
3385577755
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.374329074
Short name T1082
Test name
Test status
Simulation time 13823179 ps
CPU time 0.78 seconds
Started Mar 19 03:18:49 PM PDT 24
Finished Mar 19 03:18:51 PM PDT 24
Peak memory 204024 kb
Host smart-2c9a97e7-7df1-4e0a-ba85-a4586804afd9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374329074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.374329074
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.15725179
Short name T1042
Test name
Test status
Simulation time 12996283 ps
CPU time 0.71 seconds
Started Mar 19 03:18:48 PM PDT 24
Finished Mar 19 03:18:50 PM PDT 24
Peak memory 203664 kb
Host smart-1dea76f4-fa58-4454-ba30-4dff4a381e95
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15725179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.15725179
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.1072878110
Short name T146
Test name
Test status
Simulation time 150348327 ps
CPU time 3.69 seconds
Started Mar 19 03:18:40 PM PDT 24
Finished Mar 19 03:18:44 PM PDT 24
Peak memory 217936 kb
Host smart-05373ff3-05e4-4387-b48d-ce98b4a625c6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072878110 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.1072878110
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.782332129
Short name T1106
Test name
Test status
Simulation time 28535791 ps
CPU time 1.9 seconds
Started Mar 19 03:18:34 PM PDT 24
Finished Mar 19 03:18:36 PM PDT 24
Peak memory 215536 kb
Host smart-fc947999-3758-41b6-87a4-446fde0c5a38
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782332129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.782332129
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.319424252
Short name T995
Test name
Test status
Simulation time 37082315 ps
CPU time 0.78 seconds
Started Mar 19 03:18:33 PM PDT 24
Finished Mar 19 03:18:34 PM PDT 24
Peak memory 203696 kb
Host smart-b1ba8846-2a0e-4003-b7a2-9c45543cd827
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319424252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.319424252
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.1880108852
Short name T1004
Test name
Test status
Simulation time 62216670 ps
CPU time 3.78 seconds
Started Mar 19 03:18:29 PM PDT 24
Finished Mar 19 03:18:33 PM PDT 24
Peak memory 215532 kb
Host smart-288c000d-64df-4e35-96b0-2b9e53878da5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880108852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.s
pi_device_same_csr_outstanding.1880108852
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.1710488474
Short name T113
Test name
Test status
Simulation time 994270081 ps
CPU time 3.12 seconds
Started Mar 19 03:18:28 PM PDT 24
Finished Mar 19 03:18:31 PM PDT 24
Peak memory 215812 kb
Host smart-e704ba5a-6792-4d29-bb83-485139fb1cb3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710488474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.1
710488474
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.3388858110
Short name T1073
Test name
Test status
Simulation time 407078928 ps
CPU time 6.79 seconds
Started Mar 19 03:18:27 PM PDT 24
Finished Mar 19 03:18:34 PM PDT 24
Peak memory 215816 kb
Host smart-a4c61141-ad61-4d9e-8013-218cde92c701
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388858110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.3388858110
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.2962867189
Short name T1030
Test name
Test status
Simulation time 121324373 ps
CPU time 1.96 seconds
Started Mar 19 03:18:32 PM PDT 24
Finished Mar 19 03:18:34 PM PDT 24
Peak memory 216696 kb
Host smart-3e720d9c-b9d7-42a3-ad9e-6f983a02386d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962867189 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.2962867189
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.4020864358
Short name T1084
Test name
Test status
Simulation time 111619005 ps
CPU time 2.69 seconds
Started Mar 19 03:18:36 PM PDT 24
Finished Mar 19 03:18:39 PM PDT 24
Peak memory 207320 kb
Host smart-c9e8b113-e801-48dc-967b-6722c91f4c6e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020864358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.4
020864358
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.2531769914
Short name T1053
Test name
Test status
Simulation time 23103754 ps
CPU time 0.71 seconds
Started Mar 19 03:18:40 PM PDT 24
Finished Mar 19 03:18:41 PM PDT 24
Peak memory 203692 kb
Host smart-836ea35f-1a6a-47fa-a050-dd641b286963
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531769914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.2
531769914
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.1399448881
Short name T1114
Test name
Test status
Simulation time 170762259 ps
CPU time 2.92 seconds
Started Mar 19 03:18:40 PM PDT 24
Finished Mar 19 03:18:44 PM PDT 24
Peak memory 215524 kb
Host smart-01edebe7-9f0e-4fd5-a07b-02e13120da79
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399448881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.s
pi_device_same_csr_outstanding.1399448881
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.1516713555
Short name T1086
Test name
Test status
Simulation time 56885391 ps
CPU time 3.98 seconds
Started Mar 19 03:18:28 PM PDT 24
Finished Mar 19 03:18:32 PM PDT 24
Peak memory 215496 kb
Host smart-78e0952e-c6cd-49f5-b2c3-948181d1543a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516713555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.1
516713555
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.3954911927
Short name T148
Test name
Test status
Simulation time 980742902 ps
CPU time 23.14 seconds
Started Mar 19 03:18:47 PM PDT 24
Finished Mar 19 03:19:11 PM PDT 24
Peak memory 216976 kb
Host smart-b7090973-06e5-4611-be96-12bef7f1a2e2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954911927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device
_tl_intg_err.3954911927
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.1107858697
Short name T1075
Test name
Test status
Simulation time 127810905 ps
CPU time 3.74 seconds
Started Mar 19 03:18:40 PM PDT 24
Finished Mar 19 03:18:44 PM PDT 24
Peak memory 218056 kb
Host smart-14d33537-6c06-4e4c-8bbe-62b8a2dba7ed
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107858697 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.1107858697
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.1851192793
Short name T1058
Test name
Test status
Simulation time 74620919 ps
CPU time 2.66 seconds
Started Mar 19 03:18:43 PM PDT 24
Finished Mar 19 03:18:46 PM PDT 24
Peak memory 207308 kb
Host smart-24315d2d-0c26-4d54-a702-cbc7f3008e9d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851192793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.1
851192793
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.1044826663
Short name T1052
Test name
Test status
Simulation time 62641428 ps
CPU time 0.69 seconds
Started Mar 19 03:18:29 PM PDT 24
Finished Mar 19 03:18:30 PM PDT 24
Peak memory 203664 kb
Host smart-a58096e2-869c-4623-b27d-f3be6d35e369
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044826663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.1
044826663
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.919543938
Short name T993
Test name
Test status
Simulation time 26168868 ps
CPU time 1.55 seconds
Started Mar 19 03:18:37 PM PDT 24
Finished Mar 19 03:18:39 PM PDT 24
Peak memory 207360 kb
Host smart-6cae84ed-598f-495d-aa41-72f7e2d32272
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919543938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sp
i_device_same_csr_outstanding.919543938
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.1823567568
Short name T111
Test name
Test status
Simulation time 69239314 ps
CPU time 2.01 seconds
Started Mar 19 03:18:31 PM PDT 24
Finished Mar 19 03:18:33 PM PDT 24
Peak memory 215640 kb
Host smart-c170aaa6-05b1-4dae-8c17-de2b38c9eb9c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823567568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.1
823567568
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.786548488
Short name T1045
Test name
Test status
Simulation time 336246445 ps
CPU time 7.51 seconds
Started Mar 19 03:18:33 PM PDT 24
Finished Mar 19 03:18:40 PM PDT 24
Peak memory 215668 kb
Host smart-4c38fedb-f848-4fc6-96f0-8edb78d73ad6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786548488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_
tl_intg_err.786548488
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.983599785
Short name T1090
Test name
Test status
Simulation time 153894606 ps
CPU time 4.02 seconds
Started Mar 19 03:18:32 PM PDT 24
Finished Mar 19 03:18:37 PM PDT 24
Peak memory 216924 kb
Host smart-6ad45583-6a6d-4c66-9af4-7de7d37546ce
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983599785 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.983599785
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.1485396594
Short name T1097
Test name
Test status
Simulation time 29455042 ps
CPU time 1.93 seconds
Started Mar 19 03:18:31 PM PDT 24
Finished Mar 19 03:18:33 PM PDT 24
Peak memory 215460 kb
Host smart-68c54620-6dcc-4856-b6da-341c1463792c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485396594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.1
485396594
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.741078092
Short name T1017
Test name
Test status
Simulation time 17222868 ps
CPU time 0.74 seconds
Started Mar 19 03:18:27 PM PDT 24
Finished Mar 19 03:18:28 PM PDT 24
Peak memory 203688 kb
Host smart-6f8a2efa-39e5-4cbd-a787-92d56b9cd66c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741078092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.741078092
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.3939034705
Short name T1005
Test name
Test status
Simulation time 357078291 ps
CPU time 3 seconds
Started Mar 19 03:18:40 PM PDT 24
Finished Mar 19 03:18:44 PM PDT 24
Peak memory 215500 kb
Host smart-bebaa4ae-092f-4c34-991c-b833b3f187a2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939034705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.s
pi_device_same_csr_outstanding.3939034705
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.2270560484
Short name T1044
Test name
Test status
Simulation time 172756053 ps
CPU time 2.95 seconds
Started Mar 19 03:18:32 PM PDT 24
Finished Mar 19 03:18:35 PM PDT 24
Peak memory 217168 kb
Host smart-4109d188-1fa1-4d44-9403-d0427628ff59
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270560484 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.2270560484
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.3743812156
Short name T127
Test name
Test status
Simulation time 43143423 ps
CPU time 2.44 seconds
Started Mar 19 03:18:31 PM PDT 24
Finished Mar 19 03:18:34 PM PDT 24
Peak memory 215528 kb
Host smart-aa3c5795-1839-40f2-a622-958ddae69a64
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743812156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.3
743812156
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.597544704
Short name T1019
Test name
Test status
Simulation time 50881599 ps
CPU time 0.78 seconds
Started Mar 19 03:18:34 PM PDT 24
Finished Mar 19 03:18:35 PM PDT 24
Peak memory 203900 kb
Host smart-c4d4f340-ec01-468f-8853-bad20d1396e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597544704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.597544704
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.1521806955
Short name T991
Test name
Test status
Simulation time 110368708 ps
CPU time 1.85 seconds
Started Mar 19 03:18:31 PM PDT 24
Finished Mar 19 03:18:33 PM PDT 24
Peak memory 215512 kb
Host smart-c5620e57-3da6-4a78-8feb-e4dbbeb5835f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521806955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.s
pi_device_same_csr_outstanding.1521806955
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.2679490624
Short name T1098
Test name
Test status
Simulation time 62056355 ps
CPU time 4.39 seconds
Started Mar 19 03:18:28 PM PDT 24
Finished Mar 19 03:18:33 PM PDT 24
Peak memory 216800 kb
Host smart-fb753efb-4214-4e3a-a8a1-588925733d3f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679490624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.2
679490624
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.4077429759
Short name T150
Test name
Test status
Simulation time 3989124917 ps
CPU time 22.03 seconds
Started Mar 19 03:18:27 PM PDT 24
Finished Mar 19 03:18:49 PM PDT 24
Peak memory 215684 kb
Host smart-128f53e5-0d95-4a39-8638-450f157bd615
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077429759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device
_tl_intg_err.4077429759
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.2927408780
Short name T787
Test name
Test status
Simulation time 37927897 ps
CPU time 0.73 seconds
Started Mar 19 02:13:48 PM PDT 24
Finished Mar 19 02:13:49 PM PDT 24
Peak memory 205624 kb
Host smart-b8dea4cd-d8f1-46ea-b3a9-a22a04a35dff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927408780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.2
927408780
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.860105292
Short name T926
Test name
Test status
Simulation time 274724054 ps
CPU time 3.11 seconds
Started Mar 19 02:13:36 PM PDT 24
Finished Mar 19 02:13:39 PM PDT 24
Peak memory 218792 kb
Host smart-48f543c5-6228-45ec-a1a0-f6c668b66e13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=860105292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.860105292
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.3991862701
Short name T435
Test name
Test status
Simulation time 30315447 ps
CPU time 0.83 seconds
Started Mar 19 02:13:25 PM PDT 24
Finished Mar 19 02:13:26 PM PDT 24
Peak memory 206720 kb
Host smart-491c5d95-424f-4b0d-b27d-0399b1be8015
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3991862701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.3991862701
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.3360281126
Short name T271
Test name
Test status
Simulation time 9686959428 ps
CPU time 56.88 seconds
Started Mar 19 02:13:34 PM PDT 24
Finished Mar 19 02:14:32 PM PDT 24
Peak memory 249652 kb
Host smart-ba4b49a9-2018-4815-8178-927ab7e45bcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3360281126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.3360281126
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.534838948
Short name T21
Test name
Test status
Simulation time 9022267972 ps
CPU time 111.14 seconds
Started Mar 19 02:13:36 PM PDT 24
Finished Mar 19 02:15:27 PM PDT 24
Peak memory 267672 kb
Host smart-1ee9c15a-e8d5-408b-8400-e1187e7c750e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=534838948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.534838948
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.1922567267
Short name T28
Test name
Test status
Simulation time 66131695845 ps
CPU time 125.19 seconds
Started Mar 19 02:13:41 PM PDT 24
Finished Mar 19 02:15:47 PM PDT 24
Peak memory 239644 kb
Host smart-0cdfca07-b7a1-4cee-9e22-88c3d85be36e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1922567267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle
.1922567267
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.2351369813
Short name T971
Test name
Test status
Simulation time 1083313671 ps
CPU time 9.59 seconds
Started Mar 19 02:13:34 PM PDT 24
Finished Mar 19 02:13:44 PM PDT 24
Peak memory 235972 kb
Host smart-7193bc75-0125-4d11-afd4-5e0569247dbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2351369813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.2351369813
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_intercept.3711161652
Short name T565
Test name
Test status
Simulation time 3193057730 ps
CPU time 4.91 seconds
Started Mar 19 02:13:25 PM PDT 24
Finished Mar 19 02:13:30 PM PDT 24
Peak memory 235940 kb
Host smart-a03e987f-889c-453c-be21-17b4ec006d3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3711161652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.3711161652
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.499577391
Short name T328
Test name
Test status
Simulation time 29174484066 ps
CPU time 15.6 seconds
Started Mar 19 02:13:23 PM PDT 24
Finished Mar 19 02:13:39 PM PDT 24
Peak memory 243820 kb
Host smart-a9e0bec6-4160-4de6-9726-83498c129c2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=499577391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.499577391
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_mem_parity.1934200632
Short name T959
Test name
Test status
Simulation time 43484574 ps
CPU time 1.13 seconds
Started Mar 19 02:13:24 PM PDT 24
Finished Mar 19 02:13:26 PM PDT 24
Peak memory 216984 kb
Host smart-e698cce7-24d8-40ed-ae46-a49822077675
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934200632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 0.spi_device_mem_parity.1934200632
Directory /workspace/0.spi_device_mem_parity/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.3851636698
Short name T512
Test name
Test status
Simulation time 858755505 ps
CPU time 7.32 seconds
Started Mar 19 02:13:26 PM PDT 24
Finished Mar 19 02:13:34 PM PDT 24
Peak memory 227548 kb
Host smart-9cd4a1c1-ae90-4b0d-8c9d-53742ecb6294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3851636698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap
.3851636698
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.2041218494
Short name T835
Test name
Test status
Simulation time 2379304693 ps
CPU time 10.6 seconds
Started Mar 19 02:13:23 PM PDT 24
Finished Mar 19 02:13:34 PM PDT 24
Peak memory 234284 kb
Host smart-bfa6d43c-bb78-43ed-ba1c-b9e38e34952e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2041218494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.2041218494
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.1225606426
Short name T727
Test name
Test status
Simulation time 1735287694 ps
CPU time 7.68 seconds
Started Mar 19 02:13:33 PM PDT 24
Finished Mar 19 02:13:41 PM PDT 24
Peak memory 222564 kb
Host smart-6247c3ff-f28e-4752-b285-7e813eb7be62
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1225606426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.1225606426
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.3503440728
Short name T597
Test name
Test status
Simulation time 231989540 ps
CPU time 1.05 seconds
Started Mar 19 02:13:34 PM PDT 24
Finished Mar 19 02:13:35 PM PDT 24
Peak memory 205768 kb
Host smart-da02df1e-0cf7-4bb5-b619-b5b9efe9dbb8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503440728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stres
s_all.3503440728
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.179233100
Short name T864
Test name
Test status
Simulation time 19033404916 ps
CPU time 61.36 seconds
Started Mar 19 02:13:25 PM PDT 24
Finished Mar 19 02:14:27 PM PDT 24
Peak memory 216700 kb
Host smart-91acc204-9c69-4f7e-bc54-b9ed58c3c508
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=179233100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.179233100
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.981216489
Short name T922
Test name
Test status
Simulation time 724597963 ps
CPU time 2.74 seconds
Started Mar 19 02:13:24 PM PDT 24
Finished Mar 19 02:13:27 PM PDT 24
Peak memory 216248 kb
Host smart-d2d10f0d-ed73-4c44-a1e4-9da0f6a55bb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981216489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.981216489
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.987219588
Short name T162
Test name
Test status
Simulation time 677410858 ps
CPU time 4.05 seconds
Started Mar 19 02:13:23 PM PDT 24
Finished Mar 19 02:13:27 PM PDT 24
Peak memory 216748 kb
Host smart-49442a34-e7f9-4bf4-a699-ffd83bbc1752
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=987219588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.987219588
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.1936270586
Short name T394
Test name
Test status
Simulation time 134979678 ps
CPU time 1.02 seconds
Started Mar 19 02:13:25 PM PDT 24
Finished Mar 19 02:13:26 PM PDT 24
Peak memory 207036 kb
Host smart-4018c49c-fd09-4f23-873c-fb2da68d18e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1936270586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.1936270586
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.4271840521
Short name T869
Test name
Test status
Simulation time 3276416200 ps
CPU time 10.21 seconds
Started Mar 19 02:13:34 PM PDT 24
Finished Mar 19 02:13:45 PM PDT 24
Peak memory 219304 kb
Host smart-84af62c8-60e2-41f2-8343-4ee9c51dc021
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4271840521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.4271840521
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.2933757622
Short name T973
Test name
Test status
Simulation time 22104357 ps
CPU time 0.75 seconds
Started Mar 19 02:14:00 PM PDT 24
Finished Mar 19 02:14:02 PM PDT 24
Peak memory 205656 kb
Host smart-f988a9f3-763e-4176-9400-b91ab3389b98
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933757622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.2
933757622
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.299351242
Short name T222
Test name
Test status
Simulation time 685343176 ps
CPU time 2.47 seconds
Started Mar 19 02:13:59 PM PDT 24
Finished Mar 19 02:14:02 PM PDT 24
Peak memory 224816 kb
Host smart-3bbe4ba6-8931-4b94-a042-2609f21ae350
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=299351242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.299351242
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.2354851097
Short name T56
Test name
Test status
Simulation time 14927317 ps
CPU time 0.77 seconds
Started Mar 19 02:13:49 PM PDT 24
Finished Mar 19 02:13:50 PM PDT 24
Peak memory 206036 kb
Host smart-36a1b5ef-b14c-4d70-819d-c95d853c6e59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2354851097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.2354851097
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.2452438803
Short name T312
Test name
Test status
Simulation time 4345402782 ps
CPU time 22.94 seconds
Started Mar 19 02:14:01 PM PDT 24
Finished Mar 19 02:14:25 PM PDT 24
Peak memory 234872 kb
Host smart-1f0e00ed-e444-43ef-9a25-22055808fa8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452438803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.2452438803
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.396212424
Short name T252
Test name
Test status
Simulation time 117353987965 ps
CPU time 276.43 seconds
Started Mar 19 02:14:01 PM PDT 24
Finished Mar 19 02:18:39 PM PDT 24
Peak memory 249672 kb
Host smart-a782d095-b369-456b-90b4-b1ac68cd475d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=396212424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.396212424
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.3766396448
Short name T673
Test name
Test status
Simulation time 20427045958 ps
CPU time 32.14 seconds
Started Mar 19 02:13:58 PM PDT 24
Finished Mar 19 02:14:30 PM PDT 24
Peak memory 237048 kb
Host smart-60349c6f-3507-40dd-8850-08bc4ffe21e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766396448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.3766396448
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_intercept.562537928
Short name T31
Test name
Test status
Simulation time 198813534 ps
CPU time 2.77 seconds
Started Mar 19 02:14:01 PM PDT 24
Finished Mar 19 02:14:05 PM PDT 24
Peak memory 234020 kb
Host smart-c2cff52c-cab2-43bb-9e26-6013e649b13b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=562537928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.562537928
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.1830289618
Short name T191
Test name
Test status
Simulation time 7033770850 ps
CPU time 19.02 seconds
Started Mar 19 02:13:59 PM PDT 24
Finished Mar 19 02:14:19 PM PDT 24
Peak memory 234712 kb
Host smart-6e225e08-3b39-4b47-b410-0dc19573e0b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1830289618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.1830289618
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_mem_parity.149959900
Short name T855
Test name
Test status
Simulation time 128446116 ps
CPU time 1.03 seconds
Started Mar 19 02:13:47 PM PDT 24
Finished Mar 19 02:13:48 PM PDT 24
Peak memory 217040 kb
Host smart-38cd047c-e482-4dde-9ae6-defc64cc1e43
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149959900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.spi_device_mem_parity.149959900
Directory /workspace/1.spi_device_mem_parity/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.769032458
Short name T860
Test name
Test status
Simulation time 1130812402 ps
CPU time 8.04 seconds
Started Mar 19 02:14:02 PM PDT 24
Finished Mar 19 02:14:11 PM PDT 24
Peak memory 217336 kb
Host smart-dc9e76d5-3636-408d-9274-bbafe0ebb476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=769032458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap.
769032458
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.2953873245
Short name T360
Test name
Test status
Simulation time 675130801 ps
CPU time 4.09 seconds
Started Mar 19 02:13:49 PM PDT 24
Finished Mar 19 02:13:53 PM PDT 24
Peak memory 224916 kb
Host smart-58170eb6-17c6-4e85-a8ac-58b6c81c08bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2953873245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.2953873245
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_ram_cfg.628808338
Short name T954
Test name
Test status
Simulation time 45642393 ps
CPU time 0.75 seconds
Started Mar 19 02:13:49 PM PDT 24
Finished Mar 19 02:13:50 PM PDT 24
Peak memory 216456 kb
Host smart-006bd511-945d-4ba5-9c48-9d9555a2590d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628808338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_ram_cfg.628808338
Directory /workspace/1.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.543803269
Short name T988
Test name
Test status
Simulation time 1008102960 ps
CPU time 4.86 seconds
Started Mar 19 02:13:58 PM PDT 24
Finished Mar 19 02:14:03 PM PDT 24
Peak memory 223440 kb
Host smart-15198276-d8a6-4604-9718-1f899d6fb3ec
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=543803269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_direc
t.543803269
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.3309558014
Short name T76
Test name
Test status
Simulation time 61397001 ps
CPU time 1.11 seconds
Started Mar 19 02:14:01 PM PDT 24
Finished Mar 19 02:14:03 PM PDT 24
Peak memory 235892 kb
Host smart-b7eafde0-df66-444c-92ab-b676db7170a3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309558014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.3309558014
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.2709113181
Short name T571
Test name
Test status
Simulation time 101538976832 ps
CPU time 178 seconds
Started Mar 19 02:14:01 PM PDT 24
Finished Mar 19 02:17:00 PM PDT 24
Peak memory 250100 kb
Host smart-9089bd22-2208-4821-a888-e85f64bcafa7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709113181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stres
s_all.2709113181
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.8466533
Short name T590
Test name
Test status
Simulation time 10410808742 ps
CPU time 54 seconds
Started Mar 19 02:13:47 PM PDT 24
Finished Mar 19 02:14:41 PM PDT 24
Peak memory 216780 kb
Host smart-4ae47188-a46d-4243-b514-d3a88bbf6a3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8466533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.8466533
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.2412017732
Short name T306
Test name
Test status
Simulation time 7436842382 ps
CPU time 3.01 seconds
Started Mar 19 02:13:48 PM PDT 24
Finished Mar 19 02:13:51 PM PDT 24
Peak memory 216504 kb
Host smart-66b247fc-d652-4c87-9aa5-642024455be6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2412017732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.2412017732
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.3787045117
Short name T943
Test name
Test status
Simulation time 71037320 ps
CPU time 1.08 seconds
Started Mar 19 02:13:49 PM PDT 24
Finished Mar 19 02:13:50 PM PDT 24
Peak memory 206992 kb
Host smart-4c05bef3-3ee1-4510-8e61-1fe7ca3543ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3787045117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.3787045117
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.3793026266
Short name T664
Test name
Test status
Simulation time 149053539 ps
CPU time 0.84 seconds
Started Mar 19 02:13:49 PM PDT 24
Finished Mar 19 02:13:50 PM PDT 24
Peak memory 205852 kb
Host smart-96543e37-4ada-4393-b4ea-f178beeac1b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3793026266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.3793026266
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.2036678590
Short name T511
Test name
Test status
Simulation time 12284555120 ps
CPU time 37.82 seconds
Started Mar 19 02:14:01 PM PDT 24
Finished Mar 19 02:14:40 PM PDT 24
Peak memory 218276 kb
Host smart-5d7af4ff-9043-46c3-a7a7-84cbb1d870fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2036678590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.2036678590
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.1680514252
Short name T880
Test name
Test status
Simulation time 39285023 ps
CPU time 0.71 seconds
Started Mar 19 02:16:26 PM PDT 24
Finished Mar 19 02:16:27 PM PDT 24
Peak memory 205620 kb
Host smart-26b650e2-c509-4530-94a8-4c8c7753244f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680514252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.
1680514252
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.34499733
Short name T715
Test name
Test status
Simulation time 965295987 ps
CPU time 5.67 seconds
Started Mar 19 02:16:16 PM PDT 24
Finished Mar 19 02:16:21 PM PDT 24
Peak memory 220056 kb
Host smart-392e2ed5-0886-455f-9896-726fc21a6b70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34499733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.34499733
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.2634909242
Short name T57
Test name
Test status
Simulation time 39722211 ps
CPU time 0.77 seconds
Started Mar 19 02:16:16 PM PDT 24
Finished Mar 19 02:16:17 PM PDT 24
Peak memory 206624 kb
Host smart-166d1091-7ba3-4243-afd6-52f3636fbb37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2634909242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.2634909242
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.707720450
Short name T265
Test name
Test status
Simulation time 105985608081 ps
CPU time 136.1 seconds
Started Mar 19 02:16:15 PM PDT 24
Finished Mar 19 02:18:31 PM PDT 24
Peak memory 249628 kb
Host smart-18a4757b-c554-4e23-a9ae-b1d7472e3c85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707720450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.707720450
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.66683479
Short name T171
Test name
Test status
Simulation time 7107878386 ps
CPU time 44.47 seconds
Started Mar 19 02:16:16 PM PDT 24
Finished Mar 19 02:17:01 PM PDT 24
Peak memory 235476 kb
Host smart-5174a7de-8075-4600-82ec-5ae1e391eed8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66683479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.66683479
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.1322141811
Short name T53
Test name
Test status
Simulation time 209975418121 ps
CPU time 366.83 seconds
Started Mar 19 02:16:16 PM PDT 24
Finished Mar 19 02:22:23 PM PDT 24
Peak memory 265624 kb
Host smart-c4a70b1e-e33b-4901-8e72-462ed0415849
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1322141811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idl
e.1322141811
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.1278508030
Short name T631
Test name
Test status
Simulation time 5504630196 ps
CPU time 31.98 seconds
Started Mar 19 02:16:15 PM PDT 24
Finished Mar 19 02:16:47 PM PDT 24
Peak memory 233304 kb
Host smart-091cffd2-6ffa-4d68-8bf2-04ba31b29ece
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1278508030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.1278508030
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_intercept.3159855089
Short name T352
Test name
Test status
Simulation time 1172523689 ps
CPU time 3.39 seconds
Started Mar 19 02:16:18 PM PDT 24
Finished Mar 19 02:16:22 PM PDT 24
Peak memory 218924 kb
Host smart-4fa54ec8-c667-40ac-b428-5123b87f3e8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3159855089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.3159855089
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.498974417
Short name T2
Test name
Test status
Simulation time 21656130553 ps
CPU time 18.01 seconds
Started Mar 19 02:16:16 PM PDT 24
Finished Mar 19 02:16:34 PM PDT 24
Peak memory 234996 kb
Host smart-d5aa8b52-4d9d-4274-9718-d36f8ed3f97a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=498974417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.498974417
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.1254225385
Short name T553
Test name
Test status
Simulation time 546668021 ps
CPU time 5.64 seconds
Started Mar 19 02:16:15 PM PDT 24
Finished Mar 19 02:16:21 PM PDT 24
Peak memory 241276 kb
Host smart-e90a8c31-69b6-47ce-a742-b7ab029d391c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1254225385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swa
p.1254225385
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.365223226
Short name T481
Test name
Test status
Simulation time 8670565040 ps
CPU time 10.95 seconds
Started Mar 19 02:16:15 PM PDT 24
Finished Mar 19 02:16:26 PM PDT 24
Peak memory 235940 kb
Host smart-5a8f1a0d-01f1-4f4d-aa16-793bdbdcf476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365223226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.365223226
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_ram_cfg.3587218893
Short name T663
Test name
Test status
Simulation time 43056416 ps
CPU time 0.77 seconds
Started Mar 19 02:16:17 PM PDT 24
Finished Mar 19 02:16:18 PM PDT 24
Peak memory 216524 kb
Host smart-2ce10174-7977-4883-bdc6-6713fb475a0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3587218893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_ram_cfg.3587218893
Directory /workspace/10.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.2847139440
Short name T764
Test name
Test status
Simulation time 1372481786 ps
CPU time 5.14 seconds
Started Mar 19 02:16:18 PM PDT 24
Finished Mar 19 02:16:23 PM PDT 24
Peak memory 223148 kb
Host smart-881f1a9b-6894-47b4-a0db-b095326dee14
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2847139440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dir
ect.2847139440
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.2279603062
Short name T152
Test name
Test status
Simulation time 37205372690 ps
CPU time 75.4 seconds
Started Mar 19 02:16:27 PM PDT 24
Finished Mar 19 02:17:43 PM PDT 24
Peak memory 249768 kb
Host smart-4a816d8a-9df5-4868-8345-245aaf2fe7b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279603062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stre
ss_all.2279603062
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.1421753625
Short name T622
Test name
Test status
Simulation time 10328888555 ps
CPU time 16.01 seconds
Started Mar 19 02:16:18 PM PDT 24
Finished Mar 19 02:16:34 PM PDT 24
Peak memory 216688 kb
Host smart-e5b6cd94-748c-4d31-a718-e522be91e157
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1421753625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.1421753625
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.2260876789
Short name T409
Test name
Test status
Simulation time 467259983 ps
CPU time 4.04 seconds
Started Mar 19 02:16:15 PM PDT 24
Finished Mar 19 02:16:19 PM PDT 24
Peak memory 216684 kb
Host smart-ce6198b9-c8f3-4274-a28a-671a997eb4a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2260876789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.2260876789
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.2175068666
Short name T436
Test name
Test status
Simulation time 95065074 ps
CPU time 0.98 seconds
Started Mar 19 02:16:16 PM PDT 24
Finished Mar 19 02:16:18 PM PDT 24
Peak memory 205908 kb
Host smart-65b9f243-6b2f-4c0e-8a0e-2794ec93df6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2175068666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.2175068666
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.1377622547
Short name T729
Test name
Test status
Simulation time 4620778269 ps
CPU time 9.78 seconds
Started Mar 19 02:16:16 PM PDT 24
Finished Mar 19 02:16:26 PM PDT 24
Peak memory 235440 kb
Host smart-962ce4e5-3f9a-4633-8714-09d305f07e6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1377622547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.1377622547
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.628259828
Short name T493
Test name
Test status
Simulation time 16108419 ps
CPU time 0.75 seconds
Started Mar 19 02:16:26 PM PDT 24
Finished Mar 19 02:16:27 PM PDT 24
Peak memory 205104 kb
Host smart-e9004f3e-e4ad-4393-8b1f-77dbdcd976b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628259828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.628259828
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.3385070615
Short name T8
Test name
Test status
Simulation time 729279495 ps
CPU time 4.66 seconds
Started Mar 19 02:16:27 PM PDT 24
Finished Mar 19 02:16:32 PM PDT 24
Peak memory 234236 kb
Host smart-65878aab-ebc6-4634-a3fb-826e8c856e28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385070615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.3385070615
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.3904502007
Short name T319
Test name
Test status
Simulation time 16940385 ps
CPU time 0.75 seconds
Started Mar 19 02:16:27 PM PDT 24
Finished Mar 19 02:16:28 PM PDT 24
Peak memory 207048 kb
Host smart-33b45830-92cf-42f3-9adf-37d468bd80ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904502007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.3904502007
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.1551117496
Short name T330
Test name
Test status
Simulation time 10536967170 ps
CPU time 35.91 seconds
Started Mar 19 02:16:26 PM PDT 24
Finished Mar 19 02:17:03 PM PDT 24
Peak memory 245780 kb
Host smart-22e5af18-ff2e-4234-a6f9-bb28f1c7a4af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551117496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.1551117496
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.2574426676
Short name T710
Test name
Test status
Simulation time 6178424842 ps
CPU time 63.39 seconds
Started Mar 19 02:16:26 PM PDT 24
Finished Mar 19 02:17:29 PM PDT 24
Peak memory 251332 kb
Host smart-b7490dab-2f9d-4e19-b61a-35a052983e15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2574426676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.2574426676
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.1409046952
Short name T276
Test name
Test status
Simulation time 4513597493 ps
CPU time 14.43 seconds
Started Mar 19 02:16:28 PM PDT 24
Finished Mar 19 02:16:43 PM PDT 24
Peak memory 241296 kb
Host smart-bd135c0d-b109-478b-ad5e-c415cc6c040d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1409046952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.1409046952
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_intercept.1765199119
Short name T953
Test name
Test status
Simulation time 252485959 ps
CPU time 2.82 seconds
Started Mar 19 02:16:29 PM PDT 24
Finished Mar 19 02:16:32 PM PDT 24
Peak memory 233596 kb
Host smart-68e1bb2c-ed4f-49ef-8e1c-a18a2890bf23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1765199119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.1765199119
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.1252182479
Short name T793
Test name
Test status
Simulation time 14897648418 ps
CPU time 16.19 seconds
Started Mar 19 02:16:28 PM PDT 24
Finished Mar 19 02:16:45 PM PDT 24
Peak memory 241344 kb
Host smart-87b82400-5217-4bf3-ba46-f819f53e2481
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252182479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.1252182479
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_mem_parity.2243236381
Short name T680
Test name
Test status
Simulation time 14207560 ps
CPU time 1.07 seconds
Started Mar 19 02:16:28 PM PDT 24
Finished Mar 19 02:16:29 PM PDT 24
Peak memory 217060 kb
Host smart-5a327ce0-254f-4581-ad7d-2b53fa181281
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243236381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 11.spi_device_mem_parity.2243236381
Directory /workspace/11.spi_device_mem_parity/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.57233469
Short name T604
Test name
Test status
Simulation time 2205148229 ps
CPU time 3.87 seconds
Started Mar 19 02:16:28 PM PDT 24
Finished Mar 19 02:16:32 PM PDT 24
Peak memory 234140 kb
Host smart-bc17a4da-01cd-4e02-a432-15db7be47b3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57233469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swap.57233469
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.1452967740
Short name T219
Test name
Test status
Simulation time 3734510088 ps
CPU time 8.54 seconds
Started Mar 19 02:16:27 PM PDT 24
Finished Mar 19 02:16:36 PM PDT 24
Peak memory 224920 kb
Host smart-21f2be21-6021-4792-8023-6164d1400aac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1452967740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.1452967740
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_ram_cfg.3849789670
Short name T968
Test name
Test status
Simulation time 63985839 ps
CPU time 0.7 seconds
Started Mar 19 02:16:28 PM PDT 24
Finished Mar 19 02:16:29 PM PDT 24
Peak memory 216436 kb
Host smart-c65fd063-d925-4e23-8796-b828b9884ee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3849789670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_ram_cfg.3849789670
Directory /workspace/11.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.1650958620
Short name T753
Test name
Test status
Simulation time 3820393844 ps
CPU time 5.98 seconds
Started Mar 19 02:16:27 PM PDT 24
Finished Mar 19 02:16:34 PM PDT 24
Peak memory 223308 kb
Host smart-55f5a8fd-b62f-47a4-b81f-0ac69edf206f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1650958620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dir
ect.1650958620
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.2778719231
Short name T539
Test name
Test status
Simulation time 2898294740 ps
CPU time 17.09 seconds
Started Mar 19 02:16:28 PM PDT 24
Finished Mar 19 02:16:45 PM PDT 24
Peak memory 216832 kb
Host smart-bd0fca94-703f-4ee7-bd0d-7ecc9fb4540d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2778719231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.2778719231
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.3668629594
Short name T575
Test name
Test status
Simulation time 6945170309 ps
CPU time 18.49 seconds
Started Mar 19 02:16:26 PM PDT 24
Finished Mar 19 02:16:44 PM PDT 24
Peak memory 216748 kb
Host smart-57b96f38-0975-4569-bdb4-39172e518167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3668629594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.3668629594
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.2360838610
Short name T307
Test name
Test status
Simulation time 98777427 ps
CPU time 1.71 seconds
Started Mar 19 02:16:34 PM PDT 24
Finished Mar 19 02:16:36 PM PDT 24
Peak memory 208188 kb
Host smart-3b276166-7f72-4c1b-8457-8b660acf19e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2360838610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.2360838610
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.2132444879
Short name T718
Test name
Test status
Simulation time 233150653 ps
CPU time 0.87 seconds
Started Mar 19 02:16:26 PM PDT 24
Finished Mar 19 02:16:27 PM PDT 24
Peak memory 205944 kb
Host smart-faa5f5cd-5ce5-4d05-89ef-f8d6319001dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132444879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.2132444879
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.2647532288
Short name T899
Test name
Test status
Simulation time 15868297841 ps
CPU time 10.92 seconds
Started Mar 19 02:16:26 PM PDT 24
Finished Mar 19 02:16:37 PM PDT 24
Peak memory 222848 kb
Host smart-3ebceaf3-4a14-483c-bed3-16721085bba9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2647532288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.2647532288
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.4155934632
Short name T381
Test name
Test status
Simulation time 97696336 ps
CPU time 0.75 seconds
Started Mar 19 02:16:52 PM PDT 24
Finished Mar 19 02:16:53 PM PDT 24
Peak memory 205656 kb
Host smart-553bf75b-c33c-4042-9307-5d848847a3e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155934632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.
4155934632
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.4184477885
Short name T739
Test name
Test status
Simulation time 2105499497 ps
CPU time 6.1 seconds
Started Mar 19 02:16:42 PM PDT 24
Finished Mar 19 02:16:48 PM PDT 24
Peak memory 234272 kb
Host smart-4d2381e3-6d43-425e-b593-7ce6301d42ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4184477885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.4184477885
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.3116794095
Short name T849
Test name
Test status
Simulation time 32598238 ps
CPU time 0.75 seconds
Started Mar 19 02:16:34 PM PDT 24
Finished Mar 19 02:16:35 PM PDT 24
Peak memory 205640 kb
Host smart-622eb3d3-a67f-4aaa-967e-af066032ff4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116794095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.3116794095
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.2452740793
Short name T40
Test name
Test status
Simulation time 44163792613 ps
CPU time 246.93 seconds
Started Mar 19 02:16:53 PM PDT 24
Finished Mar 19 02:21:00 PM PDT 24
Peak memory 265932 kb
Host smart-cee513c0-12c9-4237-9ad3-882d3f566679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452740793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.2452740793
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.3501259142
Short name T185
Test name
Test status
Simulation time 44134697180 ps
CPU time 307.56 seconds
Started Mar 19 02:16:54 PM PDT 24
Finished Mar 19 02:22:02 PM PDT 24
Peak memory 252216 kb
Host smart-af6eea1c-f086-4b4d-be92-8166d2ab5917
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501259142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idl
e.3501259142
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.1062960357
Short name T61
Test name
Test status
Simulation time 1449471222 ps
CPU time 15.59 seconds
Started Mar 19 02:16:44 PM PDT 24
Finished Mar 19 02:16:59 PM PDT 24
Peak memory 247856 kb
Host smart-efb36a3f-dc04-47ce-bbfc-d2e2abffa32e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1062960357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.1062960357
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_intercept.3693200216
Short name T916
Test name
Test status
Simulation time 206015313 ps
CPU time 3.63 seconds
Started Mar 19 02:16:39 PM PDT 24
Finished Mar 19 02:16:43 PM PDT 24
Peak memory 234620 kb
Host smart-6a3ed8f9-83e4-4162-8b2a-90b96eabc432
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3693200216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.3693200216
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.2332702736
Short name T697
Test name
Test status
Simulation time 3790906142 ps
CPU time 8.74 seconds
Started Mar 19 02:16:43 PM PDT 24
Finished Mar 19 02:16:52 PM PDT 24
Peak memory 235700 kb
Host smart-1982129e-5780-4935-b071-55beee6e0bdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2332702736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.2332702736
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_mem_parity.2139839142
Short name T446
Test name
Test status
Simulation time 51567060 ps
CPU time 1.05 seconds
Started Mar 19 02:16:42 PM PDT 24
Finished Mar 19 02:16:44 PM PDT 24
Peak memory 218348 kb
Host smart-03aa3c61-26c0-4aca-9bea-543590c3821b
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139839142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 12.spi_device_mem_parity.2139839142
Directory /workspace/12.spi_device_mem_parity/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.893720759
Short name T777
Test name
Test status
Simulation time 1532807025 ps
CPU time 4.24 seconds
Started Mar 19 02:16:41 PM PDT 24
Finished Mar 19 02:16:45 PM PDT 24
Peak memory 233940 kb
Host smart-0ebf4fee-5fcd-4c62-9341-48cf9bfd8782
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=893720759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.893720759
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_ram_cfg.1315083186
Short name T74
Test name
Test status
Simulation time 33095424 ps
CPU time 0.75 seconds
Started Mar 19 02:16:40 PM PDT 24
Finished Mar 19 02:16:41 PM PDT 24
Peak memory 216500 kb
Host smart-f825c094-a5f5-4535-9011-408f5329ee7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1315083186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_ram_cfg.1315083186
Directory /workspace/12.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.3697418297
Short name T370
Test name
Test status
Simulation time 350580208 ps
CPU time 3.96 seconds
Started Mar 19 02:16:41 PM PDT 24
Finished Mar 19 02:16:45 PM PDT 24
Peak memory 223068 kb
Host smart-45f9ab20-5e4b-4378-9db7-ae9e717ea068
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3697418297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dir
ect.3697418297
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.3966588545
Short name T153
Test name
Test status
Simulation time 235922575310 ps
CPU time 242.2 seconds
Started Mar 19 02:16:53 PM PDT 24
Finished Mar 19 02:20:56 PM PDT 24
Peak memory 270080 kb
Host smart-b0d959ed-779c-40e8-9e96-36fdd6b794f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966588545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stre
ss_all.3966588545
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.1604538306
Short name T317
Test name
Test status
Simulation time 3057457116 ps
CPU time 6.06 seconds
Started Mar 19 02:16:42 PM PDT 24
Finished Mar 19 02:16:48 PM PDT 24
Peak memory 216676 kb
Host smart-ee001967-dc1e-424f-a567-a471f4502255
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604538306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.1604538306
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.1953087824
Short name T293
Test name
Test status
Simulation time 2063278761 ps
CPU time 3.73 seconds
Started Mar 19 02:16:42 PM PDT 24
Finished Mar 19 02:16:47 PM PDT 24
Peak memory 216356 kb
Host smart-310d4f8a-4cdd-4203-970a-9450f611f4e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1953087824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.1953087824
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.3136566870
Short name T439
Test name
Test status
Simulation time 35460966 ps
CPU time 1.06 seconds
Started Mar 19 02:16:41 PM PDT 24
Finished Mar 19 02:16:43 PM PDT 24
Peak memory 206976 kb
Host smart-f7c6b66d-8be9-4db5-885b-8e447d115190
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3136566870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.3136566870
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.3964390344
Short name T574
Test name
Test status
Simulation time 35074767 ps
CPU time 0.78 seconds
Started Mar 19 02:16:40 PM PDT 24
Finished Mar 19 02:16:41 PM PDT 24
Peak memory 205920 kb
Host smart-9bfb2725-0dc1-4b5c-9ada-f8391ae50a84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964390344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.3964390344
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.2330386855
Short name T36
Test name
Test status
Simulation time 3862829586 ps
CPU time 8.08 seconds
Started Mar 19 02:16:42 PM PDT 24
Finished Mar 19 02:16:50 PM PDT 24
Peak memory 241376 kb
Host smart-2c8a5ac3-8da8-4f6a-afc6-d65773a1d219
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2330386855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.2330386855
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.4131764739
Short name T696
Test name
Test status
Simulation time 618596608 ps
CPU time 3.78 seconds
Started Mar 19 02:16:55 PM PDT 24
Finished Mar 19 02:16:59 PM PDT 24
Peak memory 233712 kb
Host smart-080be506-e034-4363-a5f5-80d4e993ea4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4131764739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.4131764739
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.380465081
Short name T714
Test name
Test status
Simulation time 38154748 ps
CPU time 0.78 seconds
Started Mar 19 02:16:58 PM PDT 24
Finished Mar 19 02:16:59 PM PDT 24
Peak memory 207024 kb
Host smart-643675a5-68f1-429e-8197-44de22d78116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=380465081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.380465081
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.307986305
Short name T670
Test name
Test status
Simulation time 1865555668 ps
CPU time 11.62 seconds
Started Mar 19 02:16:53 PM PDT 24
Finished Mar 19 02:17:05 PM PDT 24
Peak memory 249844 kb
Host smart-e6c4c770-2647-4aaa-948f-1c3d89506edc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307986305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.307986305
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.4182666210
Short name T403
Test name
Test status
Simulation time 150289260114 ps
CPU time 282.26 seconds
Started Mar 19 02:16:53 PM PDT 24
Finished Mar 19 02:21:36 PM PDT 24
Peak memory 254696 kb
Host smart-abf48fa5-7449-4ef5-83b5-4b6f8c4af446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4182666210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.4182666210
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/13.spi_device_intercept.498425941
Short name T559
Test name
Test status
Simulation time 88852564 ps
CPU time 2.92 seconds
Started Mar 19 02:16:53 PM PDT 24
Finished Mar 19 02:16:57 PM PDT 24
Peak memory 224908 kb
Host smart-fe853bc7-aa23-4f92-96fb-ac1925458287
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=498425941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.498425941
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.1523166089
Short name T589
Test name
Test status
Simulation time 28441837610 ps
CPU time 32.14 seconds
Started Mar 19 02:16:53 PM PDT 24
Finished Mar 19 02:17:25 PM PDT 24
Peak memory 241264 kb
Host smart-be4363cc-11fd-4783-81ba-76f5859cc615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1523166089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.1523166089
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_mem_parity.393162730
Short name T893
Test name
Test status
Simulation time 25571056 ps
CPU time 1.09 seconds
Started Mar 19 02:16:54 PM PDT 24
Finished Mar 19 02:16:56 PM PDT 24
Peak memory 217100 kb
Host smart-7db2e15b-3276-4ed8-8220-3c1e651e562e
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393162730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.spi_device_mem_parity.393162730
Directory /workspace/13.spi_device_mem_parity/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.142547177
Short name T581
Test name
Test status
Simulation time 53927017 ps
CPU time 2.37 seconds
Started Mar 19 02:16:54 PM PDT 24
Finished Mar 19 02:16:57 PM PDT 24
Peak memory 233144 kb
Host smart-b4de3ebd-d30b-4c19-974d-3090f7642fe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=142547177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swap
.142547177
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.1441513384
Short name T471
Test name
Test status
Simulation time 20148982868 ps
CPU time 14.43 seconds
Started Mar 19 02:16:51 PM PDT 24
Finished Mar 19 02:17:05 PM PDT 24
Peak memory 237636 kb
Host smart-c1588052-a7e9-4f53-adba-18fed6538fe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1441513384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.1441513384
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_ram_cfg.1895962816
Short name T646
Test name
Test status
Simulation time 19637533 ps
CPU time 0.75 seconds
Started Mar 19 02:16:53 PM PDT 24
Finished Mar 19 02:16:55 PM PDT 24
Peak memory 216488 kb
Host smart-98877adb-7482-48f0-96d3-f11433bd3827
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1895962816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_ram_cfg.1895962816
Directory /workspace/13.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.880799550
Short name T322
Test name
Test status
Simulation time 139463130 ps
CPU time 3.41 seconds
Started Mar 19 02:16:53 PM PDT 24
Finished Mar 19 02:16:56 PM PDT 24
Peak memory 219080 kb
Host smart-febe6b2e-af24-43a3-9455-aabfd3d98045
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=880799550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dire
ct.880799550
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.1452992386
Short name T155
Test name
Test status
Simulation time 60007924246 ps
CPU time 96.69 seconds
Started Mar 19 02:16:54 PM PDT 24
Finished Mar 19 02:18:32 PM PDT 24
Peak memory 269520 kb
Host smart-f9847e89-ffc6-4a6f-b7d3-771f4d9526a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452992386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stre
ss_all.1452992386
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.3874439697
Short name T340
Test name
Test status
Simulation time 15897554966 ps
CPU time 22.04 seconds
Started Mar 19 02:16:53 PM PDT 24
Finished Mar 19 02:17:15 PM PDT 24
Peak memory 216740 kb
Host smart-257e7d10-9029-48b8-a10f-9c512b63c69e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874439697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.3874439697
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.179848962
Short name T483
Test name
Test status
Simulation time 8662008891 ps
CPU time 13.15 seconds
Started Mar 19 02:16:53 PM PDT 24
Finished Mar 19 02:17:06 PM PDT 24
Peak memory 216684 kb
Host smart-eb33447b-6051-4089-88c4-b538ba1bc927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=179848962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.179848962
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.2399864776
Short name T363
Test name
Test status
Simulation time 206459652 ps
CPU time 7.91 seconds
Started Mar 19 02:16:56 PM PDT 24
Finished Mar 19 02:17:05 PM PDT 24
Peak memory 216644 kb
Host smart-30134fcf-867b-4956-8b3f-7ca411a8fad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2399864776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.2399864776
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.1494693967
Short name T84
Test name
Test status
Simulation time 54665261 ps
CPU time 0.87 seconds
Started Mar 19 02:16:56 PM PDT 24
Finished Mar 19 02:16:57 PM PDT 24
Peak memory 205844 kb
Host smart-24087d70-ad69-4a55-9502-ac0e99c6e4a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1494693967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.1494693967
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.3306068311
Short name T633
Test name
Test status
Simulation time 574942790 ps
CPU time 8.73 seconds
Started Mar 19 02:16:52 PM PDT 24
Finished Mar 19 02:17:01 PM PDT 24
Peak memory 220316 kb
Host smart-2c74e3e3-c744-4e0d-99a6-1b1c10d32b68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306068311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.3306068311
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.3116928341
Short name T402
Test name
Test status
Simulation time 52655612 ps
CPU time 0.72 seconds
Started Mar 19 02:17:02 PM PDT 24
Finished Mar 19 02:17:03 PM PDT 24
Peak memory 206016 kb
Host smart-3cbff125-0453-4ae8-8275-506b62159533
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116928341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.
3116928341
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.3810432717
Short name T945
Test name
Test status
Simulation time 824406393 ps
CPU time 4.26 seconds
Started Mar 19 02:17:05 PM PDT 24
Finished Mar 19 02:17:09 PM PDT 24
Peak memory 217996 kb
Host smart-ac74a1c8-b68c-45b3-b248-0b3243ab8511
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3810432717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.3810432717
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.3366645254
Short name T515
Test name
Test status
Simulation time 39726667 ps
CPU time 0.83 seconds
Started Mar 19 02:16:57 PM PDT 24
Finished Mar 19 02:16:58 PM PDT 24
Peak memory 206936 kb
Host smart-d95135b7-0159-451d-a659-9d1f26cf46b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3366645254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.3366645254
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.1021638290
Short name T963
Test name
Test status
Simulation time 38811365381 ps
CPU time 69.46 seconds
Started Mar 19 02:17:01 PM PDT 24
Finished Mar 19 02:18:11 PM PDT 24
Peak memory 257836 kb
Host smart-c6eeee6b-6b93-4362-8f9d-644c586ecb87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1021638290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.1021638290
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.2021993225
Short name T466
Test name
Test status
Simulation time 43068624770 ps
CPU time 151.59 seconds
Started Mar 19 02:17:02 PM PDT 24
Finished Mar 19 02:19:33 PM PDT 24
Peak memory 251780 kb
Host smart-ddae37c2-8c76-4200-b70f-57b3cb8e00b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021993225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.2021993225
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.3790262245
Short name T239
Test name
Test status
Simulation time 16606733857 ps
CPU time 175.11 seconds
Started Mar 19 02:17:05 PM PDT 24
Finished Mar 19 02:20:00 PM PDT 24
Peak memory 269864 kb
Host smart-07ef4e80-8401-499e-88f3-011b96ea6a15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3790262245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idl
e.3790262245
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.3208276056
Short name T399
Test name
Test status
Simulation time 664395838 ps
CPU time 10.2 seconds
Started Mar 19 02:17:01 PM PDT 24
Finished Mar 19 02:17:11 PM PDT 24
Peak memory 241252 kb
Host smart-0389cfd1-114c-4746-84aa-a01f90c40d37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3208276056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.3208276056
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_intercept.2954024325
Short name T661
Test name
Test status
Simulation time 468483024 ps
CPU time 3.59 seconds
Started Mar 19 02:17:03 PM PDT 24
Finished Mar 19 02:17:07 PM PDT 24
Peak memory 234172 kb
Host smart-481863b7-b6e9-498e-bf4e-ff3e4a24ea34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954024325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.2954024325
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.4190381531
Short name T203
Test name
Test status
Simulation time 1838034282 ps
CPU time 8.53 seconds
Started Mar 19 02:17:02 PM PDT 24
Finished Mar 19 02:17:11 PM PDT 24
Peak memory 234920 kb
Host smart-b4893b5c-d89d-4654-8791-7ef303c8ff46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4190381531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.4190381531
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_mem_parity.389929503
Short name T625
Test name
Test status
Simulation time 55276201 ps
CPU time 1.06 seconds
Started Mar 19 02:16:53 PM PDT 24
Finished Mar 19 02:16:55 PM PDT 24
Peak memory 217040 kb
Host smart-cff4baf1-7d35-49cf-89c9-8c3563f6cf61
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389929503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.spi_device_mem_parity.389929503
Directory /workspace/14.spi_device_mem_parity/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.3573767177
Short name T610
Test name
Test status
Simulation time 89990546 ps
CPU time 2.34 seconds
Started Mar 19 02:17:03 PM PDT 24
Finished Mar 19 02:17:06 PM PDT 24
Peak memory 233688 kb
Host smart-73ccb563-7b04-4332-ab56-1df8b10105ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3573767177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swa
p.3573767177
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.3567384878
Short name T747
Test name
Test status
Simulation time 1515041885 ps
CPU time 5.2 seconds
Started Mar 19 02:17:03 PM PDT 24
Finished Mar 19 02:17:08 PM PDT 24
Peak memory 219608 kb
Host smart-50efbc53-487e-4cfa-a723-5c44eac8090b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567384878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.3567384878
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_ram_cfg.2918113136
Short name T692
Test name
Test status
Simulation time 82044413 ps
CPU time 0.75 seconds
Started Mar 19 02:16:52 PM PDT 24
Finished Mar 19 02:16:53 PM PDT 24
Peak memory 216448 kb
Host smart-20da9e3f-a6b3-4b95-b21b-9829b76cae0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2918113136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_ram_cfg.2918113136
Directory /workspace/14.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.1862837108
Short name T459
Test name
Test status
Simulation time 639572844 ps
CPU time 4.86 seconds
Started Mar 19 02:17:04 PM PDT 24
Finished Mar 19 02:17:08 PM PDT 24
Peak memory 220404 kb
Host smart-6293c980-ff85-4194-afa0-2a201681af16
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1862837108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dir
ect.1862837108
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.1884656031
Short name T158
Test name
Test status
Simulation time 25250998391 ps
CPU time 101.11 seconds
Started Mar 19 02:17:03 PM PDT 24
Finished Mar 19 02:18:44 PM PDT 24
Peak memory 255608 kb
Host smart-9e17e45c-2309-4859-8449-b15882761eba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884656031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stre
ss_all.1884656031
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.3129785165
Short name T282
Test name
Test status
Simulation time 6102874551 ps
CPU time 35.24 seconds
Started Mar 19 02:16:52 PM PDT 24
Finished Mar 19 02:17:28 PM PDT 24
Peak memory 216796 kb
Host smart-54535a46-b3a4-4b3d-a761-f160dea055f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3129785165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.3129785165
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.358149524
Short name T780
Test name
Test status
Simulation time 21299480053 ps
CPU time 16.01 seconds
Started Mar 19 02:16:53 PM PDT 24
Finished Mar 19 02:17:10 PM PDT 24
Peak memory 216724 kb
Host smart-e7922e95-b84c-4e1d-a807-2a307211881f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=358149524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.358149524
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.850842184
Short name T462
Test name
Test status
Simulation time 403202462 ps
CPU time 2.8 seconds
Started Mar 19 02:17:01 PM PDT 24
Finished Mar 19 02:17:04 PM PDT 24
Peak memory 216780 kb
Host smart-f563cec0-8855-467f-83bc-0a3626d6c4f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=850842184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.850842184
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.2721517511
Short name T640
Test name
Test status
Simulation time 105769321 ps
CPU time 1.21 seconds
Started Mar 19 02:17:02 PM PDT 24
Finished Mar 19 02:17:03 PM PDT 24
Peak memory 205908 kb
Host smart-c2d4f27a-cf00-4d36-9afd-6776d071d3d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2721517511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.2721517511
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.583133441
Short name T788
Test name
Test status
Simulation time 936748652 ps
CPU time 6.22 seconds
Started Mar 19 02:17:01 PM PDT 24
Finished Mar 19 02:17:08 PM PDT 24
Peak memory 219268 kb
Host smart-89bc79ed-fc4e-45a3-87b3-47f1c84703a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=583133441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.583133441
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.1110834700
Short name T448
Test name
Test status
Simulation time 11640001 ps
CPU time 0.74 seconds
Started Mar 19 02:17:13 PM PDT 24
Finished Mar 19 02:17:15 PM PDT 24
Peak memory 205676 kb
Host smart-94dffa9d-499f-495d-b385-008d6edcca43
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110834700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.
1110834700
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.3536048503
Short name T804
Test name
Test status
Simulation time 1475747366 ps
CPU time 6.89 seconds
Started Mar 19 02:17:13 PM PDT 24
Finished Mar 19 02:17:21 PM PDT 24
Peak memory 237628 kb
Host smart-cef39090-4f5a-4adf-9733-e833f8c569b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3536048503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.3536048503
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.3043535165
Short name T339
Test name
Test status
Simulation time 29583246 ps
CPU time 0.83 seconds
Started Mar 19 02:17:05 PM PDT 24
Finished Mar 19 02:17:06 PM PDT 24
Peak memory 205716 kb
Host smart-26bb9167-c28c-4fee-b93d-c07ac48f806a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3043535165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.3043535165
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.3914424716
Short name T659
Test name
Test status
Simulation time 14661215403 ps
CPU time 115.55 seconds
Started Mar 19 02:17:12 PM PDT 24
Finished Mar 19 02:19:08 PM PDT 24
Peak memory 256168 kb
Host smart-9d61dc1e-2bdc-4f6f-b11c-1a18400f83c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3914424716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.3914424716
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.3488315754
Short name T256
Test name
Test status
Simulation time 24912937718 ps
CPU time 163.98 seconds
Started Mar 19 02:17:15 PM PDT 24
Finished Mar 19 02:19:59 PM PDT 24
Peak memory 238140 kb
Host smart-8839d5cb-0eb0-4928-a948-8c64b367afc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3488315754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idl
e.3488315754
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.2345641821
Short name T437
Test name
Test status
Simulation time 6275472656 ps
CPU time 29.93 seconds
Started Mar 19 02:17:15 PM PDT 24
Finished Mar 19 02:17:45 PM PDT 24
Peak memory 240768 kb
Host smart-7ad7e6ed-1f3a-4a98-9fad-649ffde05a94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2345641821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.2345641821
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_intercept.3123997053
Short name T698
Test name
Test status
Simulation time 54097083 ps
CPU time 2.71 seconds
Started Mar 19 02:17:11 PM PDT 24
Finished Mar 19 02:17:14 PM PDT 24
Peak memory 233184 kb
Host smart-70cc6668-a298-4b2b-b0dc-18d147ee4259
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3123997053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.3123997053
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.3614599566
Short name T588
Test name
Test status
Simulation time 251442358 ps
CPU time 5.2 seconds
Started Mar 19 02:17:13 PM PDT 24
Finished Mar 19 02:17:18 PM PDT 24
Peak memory 235920 kb
Host smart-6659b2b6-9222-488f-8c53-6155a799fe95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3614599566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.3614599566
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_mem_parity.1333344256
Short name T26
Test name
Test status
Simulation time 49907026 ps
CPU time 1.1 seconds
Started Mar 19 02:17:04 PM PDT 24
Finished Mar 19 02:17:05 PM PDT 24
Peak memory 217100 kb
Host smart-573e0c78-7b64-4106-899e-59a59a63ea8c
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333344256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 15.spi_device_mem_parity.1333344256
Directory /workspace/15.spi_device_mem_parity/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.852608301
Short name T508
Test name
Test status
Simulation time 100630389 ps
CPU time 2.94 seconds
Started Mar 19 02:17:15 PM PDT 24
Finished Mar 19 02:17:18 PM PDT 24
Peak memory 224872 kb
Host smart-7a391d03-cafb-4f8c-8f23-3af01be39c3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=852608301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swap
.852608301
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.3426669657
Short name T226
Test name
Test status
Simulation time 1071877547 ps
CPU time 5.64 seconds
Started Mar 19 02:17:12 PM PDT 24
Finished Mar 19 02:17:18 PM PDT 24
Peak memory 241360 kb
Host smart-d24c52be-97d5-4ce8-8e0d-bd4e70c317a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3426669657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.3426669657
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_ram_cfg.158751792
Short name T927
Test name
Test status
Simulation time 18036174 ps
CPU time 0.76 seconds
Started Mar 19 02:17:02 PM PDT 24
Finished Mar 19 02:17:03 PM PDT 24
Peak memory 216544 kb
Host smart-e3773dc4-5a91-47d2-9552-6e5de993f65a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158751792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_ram_cfg.158751792
Directory /workspace/15.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.2156629977
Short name T58
Test name
Test status
Simulation time 5201459895 ps
CPU time 5.51 seconds
Started Mar 19 02:17:17 PM PDT 24
Finished Mar 19 02:17:22 PM PDT 24
Peak memory 220524 kb
Host smart-f4d0a968-cb99-4633-924d-b5e96c1ad020
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2156629977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir
ect.2156629977
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.3996789164
Short name T70
Test name
Test status
Simulation time 48528856 ps
CPU time 1.09 seconds
Started Mar 19 02:17:15 PM PDT 24
Finished Mar 19 02:17:16 PM PDT 24
Peak memory 206900 kb
Host smart-f2cef9a7-9dc0-4243-af4b-ab9c073b3ebd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996789164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stre
ss_all.3996789164
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.4124756121
Short name T756
Test name
Test status
Simulation time 2225877092 ps
CPU time 26.67 seconds
Started Mar 19 02:17:15 PM PDT 24
Finished Mar 19 02:17:42 PM PDT 24
Peak memory 216784 kb
Host smart-c4aa0c1e-6682-4a5d-9d44-1147d0b29057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124756121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.4124756121
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.835607691
Short name T713
Test name
Test status
Simulation time 256807386 ps
CPU time 1.32 seconds
Started Mar 19 02:17:11 PM PDT 24
Finished Mar 19 02:17:13 PM PDT 24
Peak memory 208192 kb
Host smart-1b103fbf-3ae3-4678-ae59-742dbecf67f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=835607691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.835607691
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.1845839275
Short name T770
Test name
Test status
Simulation time 393415364 ps
CPU time 1.68 seconds
Started Mar 19 02:17:13 PM PDT 24
Finished Mar 19 02:17:15 PM PDT 24
Peak memory 216836 kb
Host smart-9479ee59-46dd-408f-974a-cdf9dbf88d08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1845839275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.1845839275
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.3608841346
Short name T529
Test name
Test status
Simulation time 88426777 ps
CPU time 0.95 seconds
Started Mar 19 02:17:12 PM PDT 24
Finished Mar 19 02:17:14 PM PDT 24
Peak memory 205952 kb
Host smart-8bb18dec-fed2-4487-9fe7-01ca386af412
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3608841346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.3608841346
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.3575378575
Short name T205
Test name
Test status
Simulation time 4387915349 ps
CPU time 9.74 seconds
Started Mar 19 02:17:16 PM PDT 24
Finished Mar 19 02:17:26 PM PDT 24
Peak memory 230824 kb
Host smart-bbc66991-4015-4fea-abcb-f783e0f9875d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3575378575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.3575378575
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.2907426076
Short name T562
Test name
Test status
Simulation time 11565183 ps
CPU time 0.75 seconds
Started Mar 19 02:17:22 PM PDT 24
Finished Mar 19 02:17:23 PM PDT 24
Peak memory 205608 kb
Host smart-958524ab-7b0c-4fdd-92dc-1bdda8336001
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907426076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.
2907426076
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.2756927759
Short name T59
Test name
Test status
Simulation time 201715151 ps
CPU time 2.47 seconds
Started Mar 19 02:17:23 PM PDT 24
Finished Mar 19 02:17:26 PM PDT 24
Peak memory 224816 kb
Host smart-08ac8784-6a7b-4b66-9430-49a32ff508a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756927759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.2756927759
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.574513524
Short name T347
Test name
Test status
Simulation time 62534365 ps
CPU time 0.79 seconds
Started Mar 19 02:17:12 PM PDT 24
Finished Mar 19 02:17:13 PM PDT 24
Peak memory 206740 kb
Host smart-69aeae64-2c41-44a3-a798-ef036c473569
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=574513524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.574513524
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.2413725002
Short name T172
Test name
Test status
Simulation time 247645944721 ps
CPU time 71.69 seconds
Started Mar 19 02:17:27 PM PDT 24
Finished Mar 19 02:18:39 PM PDT 24
Peak memory 249664 kb
Host smart-95152099-bce3-4a80-b39a-003038d8aa12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2413725002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.2413725002
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.3291272246
Short name T726
Test name
Test status
Simulation time 74355563150 ps
CPU time 138.37 seconds
Started Mar 19 02:17:25 PM PDT 24
Finished Mar 19 02:19:43 PM PDT 24
Peak memory 242496 kb
Host smart-2cb1d4ae-4c17-4d68-8516-0742ddae2514
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3291272246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.3291272246
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.2077288801
Short name T49
Test name
Test status
Simulation time 8869857864 ps
CPU time 39.4 seconds
Started Mar 19 02:17:23 PM PDT 24
Finished Mar 19 02:18:03 PM PDT 24
Peak memory 239456 kb
Host smart-7e8d5be4-b07d-4d1f-b569-de68beb8a22a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077288801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idl
e.2077288801
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.373997096
Short name T975
Test name
Test status
Simulation time 1834306179 ps
CPU time 13.59 seconds
Started Mar 19 02:17:22 PM PDT 24
Finished Mar 19 02:17:36 PM PDT 24
Peak memory 234692 kb
Host smart-9aa4bb1a-30cc-45fc-9970-2395701c9ec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=373997096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.373997096
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_intercept.298021063
Short name T507
Test name
Test status
Simulation time 1439040865 ps
CPU time 4.96 seconds
Started Mar 19 02:17:22 PM PDT 24
Finished Mar 19 02:17:27 PM PDT 24
Peak memory 233728 kb
Host smart-fd51ba00-5550-4d50-826c-083c65cce1e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=298021063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.298021063
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.968494082
Short name T689
Test name
Test status
Simulation time 553664652 ps
CPU time 7.94 seconds
Started Mar 19 02:17:24 PM PDT 24
Finished Mar 19 02:17:32 PM PDT 24
Peak memory 241316 kb
Host smart-1069b728-0bbc-4d78-8951-f8468d7a5be2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=968494082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.968494082
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_mem_parity.1410005169
Short name T24
Test name
Test status
Simulation time 27444734 ps
CPU time 1.12 seconds
Started Mar 19 02:17:13 PM PDT 24
Finished Mar 19 02:17:14 PM PDT 24
Peak memory 217120 kb
Host smart-05ec3c81-4301-4d98-8654-8e66a26c5b7f
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410005169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 16.spi_device_mem_parity.1410005169
Directory /workspace/16.spi_device_mem_parity/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.3389493532
Short name T981
Test name
Test status
Simulation time 54753501935 ps
CPU time 38.2 seconds
Started Mar 19 02:17:24 PM PDT 24
Finished Mar 19 02:18:02 PM PDT 24
Peak memory 230308 kb
Host smart-4a61fd8b-799d-49d8-8217-8b5897385668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3389493532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.3389493532
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.2817583789
Short name T400
Test name
Test status
Simulation time 13725187685 ps
CPU time 17.21 seconds
Started Mar 19 02:17:22 PM PDT 24
Finished Mar 19 02:17:39 PM PDT 24
Peak memory 233260 kb
Host smart-f406057b-a664-4b09-b950-87fd60b69faa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2817583789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.2817583789
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_ram_cfg.1780816069
Short name T72
Test name
Test status
Simulation time 40678300 ps
CPU time 0.74 seconds
Started Mar 19 02:17:15 PM PDT 24
Finished Mar 19 02:17:16 PM PDT 24
Peak memory 216536 kb
Host smart-da8a223d-08ee-421d-bb2b-a2668169ca98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1780816069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_ram_cfg.1780816069
Directory /workspace/16.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.2804699390
Short name T606
Test name
Test status
Simulation time 556754930 ps
CPU time 4.82 seconds
Started Mar 19 02:17:25 PM PDT 24
Finished Mar 19 02:17:30 PM PDT 24
Peak memory 222472 kb
Host smart-cc3ed25c-6d9d-4bde-89f9-b99a7bf5c47a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2804699390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir
ect.2804699390
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.434634417
Short name T71
Test name
Test status
Simulation time 460526087 ps
CPU time 0.96 seconds
Started Mar 19 02:17:23 PM PDT 24
Finished Mar 19 02:17:24 PM PDT 24
Peak memory 205696 kb
Host smart-16fd7323-3802-4e10-8dbb-947d4fefe21b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434634417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stres
s_all.434634417
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.3708457580
Short name T441
Test name
Test status
Simulation time 8698788457 ps
CPU time 54.28 seconds
Started Mar 19 02:17:24 PM PDT 24
Finished Mar 19 02:18:19 PM PDT 24
Peak memory 216784 kb
Host smart-40ca034a-216b-482e-9a60-44a009490d0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708457580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.3708457580
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.2491695875
Short name T801
Test name
Test status
Simulation time 11120195157 ps
CPU time 8.49 seconds
Started Mar 19 02:17:24 PM PDT 24
Finished Mar 19 02:17:33 PM PDT 24
Peak memory 216716 kb
Host smart-2a4fdd75-e669-4396-a5c5-26dc48b410b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2491695875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.2491695875
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.4254251057
Short name T593
Test name
Test status
Simulation time 297338019 ps
CPU time 1.08 seconds
Started Mar 19 02:17:23 PM PDT 24
Finished Mar 19 02:17:24 PM PDT 24
Peak memory 207384 kb
Host smart-a32c3f20-4b0e-40d9-b96f-d892d58f09a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4254251057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.4254251057
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.1515415063
Short name T516
Test name
Test status
Simulation time 157778767 ps
CPU time 0.83 seconds
Started Mar 19 02:17:24 PM PDT 24
Finished Mar 19 02:17:25 PM PDT 24
Peak memory 205956 kb
Host smart-fb15cfbb-2065-41b6-b582-76667e228cb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1515415063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.1515415063
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.2794496728
Short name T642
Test name
Test status
Simulation time 4455012552 ps
CPU time 16.28 seconds
Started Mar 19 02:17:23 PM PDT 24
Finished Mar 19 02:17:39 PM PDT 24
Peak memory 235064 kb
Host smart-aba69d74-63e9-48ba-b447-d8ecb17e7886
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2794496728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.2794496728
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.849986459
Short name T426
Test name
Test status
Simulation time 12302375 ps
CPU time 0.73 seconds
Started Mar 19 02:17:39 PM PDT 24
Finished Mar 19 02:17:40 PM PDT 24
Peak memory 205556 kb
Host smart-687778d2-443f-40c4-b5e3-f94b837c4e26
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849986459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.849986459
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.2083172125
Short name T534
Test name
Test status
Simulation time 356805497 ps
CPU time 2.33 seconds
Started Mar 19 02:17:33 PM PDT 24
Finished Mar 19 02:17:36 PM PDT 24
Peak memory 224844 kb
Host smart-90ef894c-6833-40e6-9f65-5352309bc2fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083172125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.2083172125
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.4185110915
Short name T299
Test name
Test status
Simulation time 22588199 ps
CPU time 0.75 seconds
Started Mar 19 02:17:25 PM PDT 24
Finished Mar 19 02:17:25 PM PDT 24
Peak memory 206648 kb
Host smart-6cd029a1-4722-4f85-8685-55832c24e9b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4185110915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.4185110915
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.3165172711
Short name T380
Test name
Test status
Simulation time 9323656510 ps
CPU time 118.09 seconds
Started Mar 19 02:17:34 PM PDT 24
Finished Mar 19 02:19:32 PM PDT 24
Peak memory 251436 kb
Host smart-e561b157-2d15-4619-a190-a6a313e20d63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3165172711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.3165172711
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.1622605464
Short name T335
Test name
Test status
Simulation time 3422230276 ps
CPU time 76.62 seconds
Started Mar 19 02:17:34 PM PDT 24
Finished Mar 19 02:18:51 PM PDT 24
Peak memory 252844 kb
Host smart-e272a231-fed4-43c5-ba09-650fb0c91b98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1622605464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idl
e.1622605464
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.1583628359
Short name T822
Test name
Test status
Simulation time 4032453282 ps
CPU time 14.32 seconds
Started Mar 19 02:17:33 PM PDT 24
Finished Mar 19 02:17:48 PM PDT 24
Peak memory 256340 kb
Host smart-2e4d7d9b-ee91-46dc-a5eb-82a0e5ef2ae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1583628359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.1583628359
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_intercept.3506128696
Short name T582
Test name
Test status
Simulation time 2992728700 ps
CPU time 7.17 seconds
Started Mar 19 02:17:40 PM PDT 24
Finished Mar 19 02:17:48 PM PDT 24
Peak memory 234228 kb
Host smart-dd1215e4-da7a-40bf-942a-3e1d53204712
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3506128696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.3506128696
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.4280487408
Short name T956
Test name
Test status
Simulation time 1277809881 ps
CPU time 8.33 seconds
Started Mar 19 02:17:32 PM PDT 24
Finished Mar 19 02:17:41 PM PDT 24
Peak memory 224840 kb
Host smart-21f436d9-db35-4fd1-9866-dc63e899af4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4280487408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.4280487408
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_mem_parity.2704992371
Short name T420
Test name
Test status
Simulation time 32612416 ps
CPU time 1.07 seconds
Started Mar 19 02:17:25 PM PDT 24
Finished Mar 19 02:17:26 PM PDT 24
Peak memory 217036 kb
Host smart-498d8d2f-0824-47e9-a3a4-79f739612a1a
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704992371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 17.spi_device_mem_parity.2704992371
Directory /workspace/17.spi_device_mem_parity/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.389954692
Short name T461
Test name
Test status
Simulation time 8524598619 ps
CPU time 21.91 seconds
Started Mar 19 02:17:33 PM PDT 24
Finished Mar 19 02:17:55 PM PDT 24
Peak memory 229092 kb
Host smart-3b5b4cc6-ed8f-4735-a1e0-10b900e49f3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=389954692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swap
.389954692
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.3610207072
Short name T924
Test name
Test status
Simulation time 5964047852 ps
CPU time 10.89 seconds
Started Mar 19 02:17:41 PM PDT 24
Finished Mar 19 02:17:51 PM PDT 24
Peak memory 239004 kb
Host smart-fd385b3e-0590-46e9-9cc8-011ed5f8b7a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3610207072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.3610207072
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_ram_cfg.1290871903
Short name T738
Test name
Test status
Simulation time 16487338 ps
CPU time 0.8 seconds
Started Mar 19 02:17:23 PM PDT 24
Finished Mar 19 02:17:24 PM PDT 24
Peak memory 216456 kb
Host smart-b23ae9a9-7680-4a07-8ec1-dd12b7ec1609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1290871903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_ram_cfg.1290871903
Directory /workspace/17.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.1473665966
Short name T876
Test name
Test status
Simulation time 520859698 ps
CPU time 4.39 seconds
Started Mar 19 02:17:34 PM PDT 24
Finished Mar 19 02:17:38 PM PDT 24
Peak memory 223036 kb
Host smart-64d2affe-f70a-4879-aeda-5b7efe19bad4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1473665966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dir
ect.1473665966
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.3853456992
Short name T393
Test name
Test status
Simulation time 8125066288 ps
CPU time 85.4 seconds
Started Mar 19 02:17:32 PM PDT 24
Finished Mar 19 02:18:58 PM PDT 24
Peak memory 249752 kb
Host smart-b1f73f6d-3ace-469d-b47c-7103534e512f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853456992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stre
ss_all.3853456992
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.1909374178
Short name T404
Test name
Test status
Simulation time 7248531634 ps
CPU time 12.13 seconds
Started Mar 19 02:17:24 PM PDT 24
Finished Mar 19 02:17:36 PM PDT 24
Peak memory 216840 kb
Host smart-90661124-6156-41fd-a3be-b9b06aee79a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1909374178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.1909374178
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.1378087937
Short name T887
Test name
Test status
Simulation time 446352982 ps
CPU time 2.31 seconds
Started Mar 19 02:17:22 PM PDT 24
Finished Mar 19 02:17:25 PM PDT 24
Peak memory 216496 kb
Host smart-4b8adbed-e2cd-417d-93e6-76e3a2e2ae12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1378087937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.1378087937
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.2387760702
Short name T878
Test name
Test status
Simulation time 113214720 ps
CPU time 1.14 seconds
Started Mar 19 02:17:32 PM PDT 24
Finished Mar 19 02:17:34 PM PDT 24
Peak memory 208208 kb
Host smart-b522f21a-661b-4cb1-8c16-77590be8d2bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2387760702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.2387760702
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.3825335391
Short name T374
Test name
Test status
Simulation time 541359503 ps
CPU time 1.04 seconds
Started Mar 19 02:17:31 PM PDT 24
Finished Mar 19 02:17:32 PM PDT 24
Peak memory 206996 kb
Host smart-999c4cd3-4780-40f9-9a6b-8b555fa881d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3825335391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.3825335391
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.3731680711
Short name T248
Test name
Test status
Simulation time 1362231122 ps
CPU time 9.49 seconds
Started Mar 19 02:17:34 PM PDT 24
Finished Mar 19 02:17:44 PM PDT 24
Peak memory 227128 kb
Host smart-fe6a120c-764f-47f7-9fd7-6e822709c882
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3731680711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.3731680711
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.3496850971
Short name T650
Test name
Test status
Simulation time 208267359 ps
CPU time 0.71 seconds
Started Mar 19 02:17:46 PM PDT 24
Finished Mar 19 02:17:47 PM PDT 24
Peak memory 205976 kb
Host smart-3908f3dd-4b15-415c-a66c-d323fa7e6e90
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496850971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.
3496850971
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.4058022221
Short name T768
Test name
Test status
Simulation time 118887857 ps
CPU time 2.15 seconds
Started Mar 19 02:17:46 PM PDT 24
Finished Mar 19 02:17:48 PM PDT 24
Peak memory 218948 kb
Host smart-31ba783f-26cd-4f76-8b9a-fb7939604ae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4058022221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.4058022221
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.648766596
Short name T570
Test name
Test status
Simulation time 62334181 ps
CPU time 0.81 seconds
Started Mar 19 02:17:32 PM PDT 24
Finished Mar 19 02:17:33 PM PDT 24
Peak memory 206712 kb
Host smart-72781a17-ab90-4b27-89ad-9c6b10e51e69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=648766596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.648766596
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.2706783804
Short name T706
Test name
Test status
Simulation time 134356450345 ps
CPU time 66.88 seconds
Started Mar 19 02:17:48 PM PDT 24
Finished Mar 19 02:18:55 PM PDT 24
Peak memory 236312 kb
Host smart-f972eb1e-f9e8-4d17-a4bd-50466d8683f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2706783804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.2706783804
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.3060129519
Short name T189
Test name
Test status
Simulation time 52165971061 ps
CPU time 411.14 seconds
Started Mar 19 02:17:47 PM PDT 24
Finished Mar 19 02:24:39 PM PDT 24
Peak memory 249568 kb
Host smart-bdcf9977-f12c-473c-8ae9-34097b6bf9af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3060129519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.3060129519
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.2435025816
Short name T783
Test name
Test status
Simulation time 1054895204 ps
CPU time 14.06 seconds
Started Mar 19 02:17:46 PM PDT 24
Finished Mar 19 02:18:01 PM PDT 24
Peak memory 239472 kb
Host smart-a3ba8887-6c32-4b1a-9d8b-efc7802eab94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2435025816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.2435025816
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_intercept.2502085238
Short name T636
Test name
Test status
Simulation time 820332730 ps
CPU time 4.9 seconds
Started Mar 19 02:17:45 PM PDT 24
Finished Mar 19 02:17:50 PM PDT 24
Peak memory 218448 kb
Host smart-56109128-c0f5-4cf4-9c39-6a7b9ac15cf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2502085238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.2502085238
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.2029521896
Short name T791
Test name
Test status
Simulation time 12877807814 ps
CPU time 12.17 seconds
Started Mar 19 02:17:47 PM PDT 24
Finished Mar 19 02:17:59 PM PDT 24
Peak memory 238584 kb
Host smart-4ed9f49d-ff2d-4eb7-b5b9-d33740d08fab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2029521896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.2029521896
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_mem_parity.672085974
Short name T658
Test name
Test status
Simulation time 31965464 ps
CPU time 1.06 seconds
Started Mar 19 02:17:38 PM PDT 24
Finished Mar 19 02:17:39 PM PDT 24
Peak memory 217032 kb
Host smart-b0fa421a-f1c9-466d-9784-33ed5cd92feb
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672085974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.spi_device_mem_parity.672085974
Directory /workspace/18.spi_device_mem_parity/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.102759042
Short name T961
Test name
Test status
Simulation time 1697144604 ps
CPU time 5.72 seconds
Started Mar 19 02:17:46 PM PDT 24
Finished Mar 19 02:17:52 PM PDT 24
Peak memory 218236 kb
Host smart-53073aa1-c4d1-4bf4-8de7-ed0f8374c82c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102759042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swap
.102759042
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.2484921970
Short name T473
Test name
Test status
Simulation time 2369660454 ps
CPU time 5.34 seconds
Started Mar 19 02:17:44 PM PDT 24
Finished Mar 19 02:17:50 PM PDT 24
Peak memory 233844 kb
Host smart-6f1239b5-be88-492f-afbe-7ceb031ede1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2484921970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.2484921970
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_ram_cfg.1514600163
Short name T892
Test name
Test status
Simulation time 34749937 ps
CPU time 0.73 seconds
Started Mar 19 02:17:34 PM PDT 24
Finished Mar 19 02:17:35 PM PDT 24
Peak memory 216444 kb
Host smart-f27240c0-e9dc-45bd-9e18-1f4958036402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514600163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_ram_cfg.1514600163
Directory /workspace/18.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.3799929359
Short name T140
Test name
Test status
Simulation time 513436455 ps
CPU time 3.44 seconds
Started Mar 19 02:17:46 PM PDT 24
Finished Mar 19 02:17:49 PM PDT 24
Peak memory 220316 kb
Host smart-a6f4a5c2-9c14-4970-95f4-cceaa7bbaef2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3799929359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dir
ect.3799929359
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.1002696929
Short name T97
Test name
Test status
Simulation time 13135068557 ps
CPU time 45.65 seconds
Started Mar 19 02:17:45 PM PDT 24
Finished Mar 19 02:18:31 PM PDT 24
Peak memory 216896 kb
Host smart-7d67e6e3-35b7-4da5-87ed-4726136e5e9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1002696929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.1002696929
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.868004516
Short name T500
Test name
Test status
Simulation time 3552826404 ps
CPU time 14.27 seconds
Started Mar 19 02:17:47 PM PDT 24
Finished Mar 19 02:18:02 PM PDT 24
Peak memory 216792 kb
Host smart-96944486-a768-4e9b-9f51-81d2c6d2d8d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868004516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.868004516
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.3390894215
Short name T609
Test name
Test status
Simulation time 62465355 ps
CPU time 1.89 seconds
Started Mar 19 02:17:47 PM PDT 24
Finished Mar 19 02:17:49 PM PDT 24
Peak memory 216664 kb
Host smart-cef6eadb-a7e0-4a1a-9117-dbcf87a8898c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3390894215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.3390894215
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.4267670199
Short name T976
Test name
Test status
Simulation time 52528513 ps
CPU time 0.86 seconds
Started Mar 19 02:17:46 PM PDT 24
Finished Mar 19 02:17:47 PM PDT 24
Peak memory 205948 kb
Host smart-bae1ea01-c9fa-4100-a2b4-f74b89dca1e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4267670199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.4267670199
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.12515938
Short name T334
Test name
Test status
Simulation time 3242753307 ps
CPU time 4.94 seconds
Started Mar 19 02:17:48 PM PDT 24
Finished Mar 19 02:17:53 PM PDT 24
Peak memory 234692 kb
Host smart-a64fa724-f1f8-49a8-9eb4-41209f27c78a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12515938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.12515938
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.3798993921
Short name T395
Test name
Test status
Simulation time 19938798 ps
CPU time 0.72 seconds
Started Mar 19 02:17:57 PM PDT 24
Finished Mar 19 02:17:59 PM PDT 24
Peak memory 206008 kb
Host smart-8030b732-3e79-452b-9b4d-0fa14eeb284a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798993921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.
3798993921
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.249160755
Short name T874
Test name
Test status
Simulation time 693435462 ps
CPU time 3.1 seconds
Started Mar 19 02:18:01 PM PDT 24
Finished Mar 19 02:18:04 PM PDT 24
Peak memory 234384 kb
Host smart-fe7b461d-214f-4049-979b-f038435664db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=249160755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.249160755
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.3893581011
Short name T615
Test name
Test status
Simulation time 46855426 ps
CPU time 0.72 seconds
Started Mar 19 02:17:45 PM PDT 24
Finished Mar 19 02:17:46 PM PDT 24
Peak memory 206028 kb
Host smart-e7b51489-53b7-423f-a094-193a81ced4f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893581011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.3893581011
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.1915250171
Short name T275
Test name
Test status
Simulation time 6194959153 ps
CPU time 87.94 seconds
Started Mar 19 02:17:58 PM PDT 24
Finished Mar 19 02:19:26 PM PDT 24
Peak memory 263316 kb
Host smart-02ebe85e-69df-4a2f-a903-079fe2bc3073
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1915250171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.1915250171
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.3803218076
Short name T541
Test name
Test status
Simulation time 14633287996 ps
CPU time 122.48 seconds
Started Mar 19 02:17:58 PM PDT 24
Finished Mar 19 02:20:02 PM PDT 24
Peak memory 249632 kb
Host smart-cc2b41ab-1f08-4b2d-9cc8-a3d884701b16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3803218076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.3803218076
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.1811428799
Short name T27
Test name
Test status
Simulation time 4136745251 ps
CPU time 45.58 seconds
Started Mar 19 02:17:56 PM PDT 24
Finished Mar 19 02:18:42 PM PDT 24
Peak memory 255196 kb
Host smart-d82d97df-d1dc-43f8-bc38-a9358c357955
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811428799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idl
e.1811428799
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/19.spi_device_intercept.641266829
Short name T429
Test name
Test status
Simulation time 127828021 ps
CPU time 3.66 seconds
Started Mar 19 02:17:49 PM PDT 24
Finished Mar 19 02:17:53 PM PDT 24
Peak memory 233800 kb
Host smart-45e0bd71-0baa-45cc-a5dc-07d4776db619
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=641266829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.641266829
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.3984221924
Short name T517
Test name
Test status
Simulation time 18447247595 ps
CPU time 12.66 seconds
Started Mar 19 02:17:54 PM PDT 24
Finished Mar 19 02:18:07 PM PDT 24
Peak memory 248072 kb
Host smart-dd1bf5c1-b596-46b7-b6ad-d176960b3cff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3984221924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.3984221924
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_mem_parity.1504994705
Short name T628
Test name
Test status
Simulation time 110322548 ps
CPU time 1.01 seconds
Started Mar 19 02:17:45 PM PDT 24
Finished Mar 19 02:17:46 PM PDT 24
Peak memory 218276 kb
Host smart-4bff448f-4836-40c3-adde-fb29820a8da4
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504994705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 19.spi_device_mem_parity.1504994705
Directory /workspace/19.spi_device_mem_parity/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.4150834021
Short name T908
Test name
Test status
Simulation time 2950306309 ps
CPU time 5.75 seconds
Started Mar 19 02:17:46 PM PDT 24
Finished Mar 19 02:17:52 PM PDT 24
Peak memory 236444 kb
Host smart-389cb831-5651-42b0-84dc-106766d43f04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4150834021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swa
p.4150834021
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.2504884628
Short name T250
Test name
Test status
Simulation time 134879596 ps
CPU time 3.47 seconds
Started Mar 19 02:17:46 PM PDT 24
Finished Mar 19 02:17:50 PM PDT 24
Peak memory 234068 kb
Host smart-75f6500d-67c0-49d3-9b30-6a9f003b97b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2504884628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.2504884628
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_ram_cfg.3151220536
Short name T983
Test name
Test status
Simulation time 42649089 ps
CPU time 0.75 seconds
Started Mar 19 02:17:46 PM PDT 24
Finished Mar 19 02:17:47 PM PDT 24
Peak memory 216488 kb
Host smart-2c4b447e-5ceb-4414-affe-504fc9762cd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3151220536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_ram_cfg.3151220536
Directory /workspace/19.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.2158982609
Short name T433
Test name
Test status
Simulation time 2263931121 ps
CPU time 4.11 seconds
Started Mar 19 02:17:58 PM PDT 24
Finished Mar 19 02:18:03 PM PDT 24
Peak memory 219788 kb
Host smart-f7f8c2dd-78f3-4765-b382-aa5ea4cfb59b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2158982609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dir
ect.2158982609
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.1115754881
Short name T16
Test name
Test status
Simulation time 2659254107 ps
CPU time 16.99 seconds
Started Mar 19 02:17:49 PM PDT 24
Finished Mar 19 02:18:06 PM PDT 24
Peak memory 216712 kb
Host smart-777ec04b-1c24-4d5d-b642-46d64754c8d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115754881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.1115754881
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.3260137952
Short name T389
Test name
Test status
Simulation time 25115830 ps
CPU time 1.36 seconds
Started Mar 19 02:17:48 PM PDT 24
Finished Mar 19 02:17:50 PM PDT 24
Peak memory 216696 kb
Host smart-91b5ba81-a2dd-478e-b64b-7967172983f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260137952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.3260137952
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.470092143
Short name T444
Test name
Test status
Simulation time 23373448 ps
CPU time 0.84 seconds
Started Mar 19 02:17:45 PM PDT 24
Finished Mar 19 02:17:47 PM PDT 24
Peak memory 205860 kb
Host smart-4bc1540b-3f4c-49c2-ab82-a773905699dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=470092143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.470092143
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.2983105518
Short name T767
Test name
Test status
Simulation time 6316239596 ps
CPU time 12.09 seconds
Started Mar 19 02:17:56 PM PDT 24
Finished Mar 19 02:18:08 PM PDT 24
Peak memory 228436 kb
Host smart-c4c97049-59f5-4450-856f-ebc88fa8160c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983105518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.2983105518
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.1745520797
Short name T759
Test name
Test status
Simulation time 25884925 ps
CPU time 0.73 seconds
Started Mar 19 02:14:19 PM PDT 24
Finished Mar 19 02:14:20 PM PDT 24
Peak memory 205588 kb
Host smart-3e715d6b-3630-403c-805b-42f6731ddd0c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745520797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.1
745520797
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.932277435
Short name T923
Test name
Test status
Simulation time 82840559 ps
CPU time 2.39 seconds
Started Mar 19 02:14:20 PM PDT 24
Finished Mar 19 02:14:22 PM PDT 24
Peak memory 217196 kb
Host smart-ee61ce66-c63b-473d-8604-3ef50cc0230a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=932277435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.932277435
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.2182360509
Short name T873
Test name
Test status
Simulation time 27566437 ps
CPU time 0.76 seconds
Started Mar 19 02:14:12 PM PDT 24
Finished Mar 19 02:14:12 PM PDT 24
Peak memory 205752 kb
Host smart-bff9bdcf-8534-424a-9d31-51c6d3ff1660
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2182360509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.2182360509
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.3838629758
Short name T187
Test name
Test status
Simulation time 47891968284 ps
CPU time 266.19 seconds
Started Mar 19 02:14:19 PM PDT 24
Finished Mar 19 02:18:46 PM PDT 24
Peak memory 266720 kb
Host smart-f31c144d-ba39-4fe1-8e6a-203d372f9c2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3838629758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.3838629758
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.4272755610
Short name T728
Test name
Test status
Simulation time 10216939621 ps
CPU time 154.11 seconds
Started Mar 19 02:14:19 PM PDT 24
Finished Mar 19 02:16:53 PM PDT 24
Peak memory 266096 kb
Host smart-dd11f66a-0c4f-4dee-a01d-f603b9399692
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272755610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.4272755610
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.1797045682
Short name T136
Test name
Test status
Simulation time 27930402648 ps
CPU time 106.11 seconds
Started Mar 19 02:14:21 PM PDT 24
Finished Mar 19 02:16:07 PM PDT 24
Peak memory 255600 kb
Host smart-7b3f0f19-7b8e-404d-b1af-0826612fa0ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797045682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle
.1797045682
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.1440384005
Short name T751
Test name
Test status
Simulation time 6255545389 ps
CPU time 38.84 seconds
Started Mar 19 02:14:19 PM PDT 24
Finished Mar 19 02:14:58 PM PDT 24
Peak memory 241364 kb
Host smart-0a6e7c66-d403-4792-8f0a-b0992b34fe89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1440384005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.1440384005
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_intercept.3930491514
Short name T775
Test name
Test status
Simulation time 278938367 ps
CPU time 2.52 seconds
Started Mar 19 02:14:10 PM PDT 24
Finished Mar 19 02:14:12 PM PDT 24
Peak memory 233148 kb
Host smart-dd9d2272-1f1d-4248-9038-6508b5295f80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930491514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.3930491514
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.3988801753
Short name T617
Test name
Test status
Simulation time 3117811106 ps
CPU time 11.21 seconds
Started Mar 19 02:14:08 PM PDT 24
Finished Mar 19 02:14:19 PM PDT 24
Peak memory 241140 kb
Host smart-5fd27697-3bd7-45c2-b327-2e774bfd4f31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3988801753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.3988801753
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_mem_parity.4097990169
Short name T421
Test name
Test status
Simulation time 160382328 ps
CPU time 1.16 seconds
Started Mar 19 02:14:11 PM PDT 24
Finished Mar 19 02:14:13 PM PDT 24
Peak memory 217140 kb
Host smart-698204fc-e8c0-4e08-8f9b-ef8e133ebbf5
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097990169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 2.spi_device_mem_parity.4097990169
Directory /workspace/2.spi_device_mem_parity/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.143774666
Short name T750
Test name
Test status
Simulation time 3348870966 ps
CPU time 10.05 seconds
Started Mar 19 02:14:09 PM PDT 24
Finished Mar 19 02:14:19 PM PDT 24
Peak memory 225108 kb
Host smart-7c7afa95-4612-42d8-beee-e7bfca4d8ed1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143774666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap.
143774666
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.3416570791
Short name T194
Test name
Test status
Simulation time 5843287598 ps
CPU time 6.42 seconds
Started Mar 19 02:14:08 PM PDT 24
Finished Mar 19 02:14:15 PM PDT 24
Peak memory 235532 kb
Host smart-822f6b56-fe2b-4e65-8c68-af503e2f26df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3416570791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.3416570791
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_ram_cfg.1868645404
Short name T652
Test name
Test status
Simulation time 28465594 ps
CPU time 0.74 seconds
Started Mar 19 02:14:09 PM PDT 24
Finished Mar 19 02:14:10 PM PDT 24
Peak memory 216440 kb
Host smart-3445e2e2-2916-4962-9df9-949314a6098e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1868645404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_ram_cfg.1868645404
Directory /workspace/2.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.3906405988
Short name T616
Test name
Test status
Simulation time 2994504823 ps
CPU time 5.23 seconds
Started Mar 19 02:14:20 PM PDT 24
Finished Mar 19 02:14:25 PM PDT 24
Peak memory 223340 kb
Host smart-474a38c8-78c8-457c-8b27-f3162a27ddde
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3906405988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_dire
ct.3906405988
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.3665653881
Short name T79
Test name
Test status
Simulation time 33974867 ps
CPU time 1 seconds
Started Mar 19 02:14:19 PM PDT 24
Finished Mar 19 02:14:20 PM PDT 24
Peak memory 234568 kb
Host smart-c8ab2a1b-a91b-4872-a695-ddc46c898f60
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665653881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.3665653881
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.353984358
Short name T829
Test name
Test status
Simulation time 82804084127 ps
CPU time 159.2 seconds
Started Mar 19 02:14:21 PM PDT 24
Finished Mar 19 02:17:00 PM PDT 24
Peak memory 265996 kb
Host smart-85747ed0-289b-4579-a126-0c053433eb52
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353984358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stress
_all.353984358
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.4031873003
Short name T284
Test name
Test status
Simulation time 25703359797 ps
CPU time 33.57 seconds
Started Mar 19 02:14:09 PM PDT 24
Finished Mar 19 02:14:42 PM PDT 24
Peak memory 216848 kb
Host smart-96eebf06-1cb3-4b96-a1cd-b0ffe924f2cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4031873003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.4031873003
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.175558656
Short name T333
Test name
Test status
Simulation time 486286698 ps
CPU time 2.55 seconds
Started Mar 19 02:14:09 PM PDT 24
Finished Mar 19 02:14:12 PM PDT 24
Peak memory 216384 kb
Host smart-e18a684f-0b5f-4179-bdbf-23fa44a820a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=175558656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.175558656
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.3925963999
Short name T344
Test name
Test status
Simulation time 642664298 ps
CPU time 2.71 seconds
Started Mar 19 02:14:09 PM PDT 24
Finished Mar 19 02:14:12 PM PDT 24
Peak memory 216584 kb
Host smart-62052bea-6423-4243-8ac2-67c266da43cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3925963999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.3925963999
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.1913132393
Short name T580
Test name
Test status
Simulation time 27182648 ps
CPU time 0.82 seconds
Started Mar 19 02:14:10 PM PDT 24
Finished Mar 19 02:14:11 PM PDT 24
Peak memory 205932 kb
Host smart-6951c84f-3911-4824-a3a8-9c16cfc8da8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1913132393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.1913132393
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.2461589620
Short name T35
Test name
Test status
Simulation time 980720301 ps
CPU time 4.47 seconds
Started Mar 19 02:14:11 PM PDT 24
Finished Mar 19 02:14:16 PM PDT 24
Peak memory 219004 kb
Host smart-52b0bd14-c81f-4430-bac7-1706cdeeeb1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2461589620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.2461589620
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.3277478452
Short name T683
Test name
Test status
Simulation time 12302483 ps
CPU time 0.72 seconds
Started Mar 19 02:18:06 PM PDT 24
Finished Mar 19 02:18:07 PM PDT 24
Peak memory 205596 kb
Host smart-ef4db5c0-85fb-4bc7-bbf4-e33465099d7d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277478452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.
3277478452
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.3770664847
Short name T623
Test name
Test status
Simulation time 548700055 ps
CPU time 4.58 seconds
Started Mar 19 02:17:57 PM PDT 24
Finished Mar 19 02:18:02 PM PDT 24
Peak memory 234220 kb
Host smart-fa8bf085-0986-4e26-ae7c-bf3a662ced43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770664847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.3770664847
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.14240846
Short name T730
Test name
Test status
Simulation time 27138054 ps
CPU time 0.79 seconds
Started Mar 19 02:17:58 PM PDT 24
Finished Mar 19 02:18:00 PM PDT 24
Peak memory 207088 kb
Host smart-9114f51c-f57c-448c-af8e-a32a17fc494b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14240846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.14240846
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.2500448714
Short name T270
Test name
Test status
Simulation time 4496406814 ps
CPU time 22.84 seconds
Started Mar 19 02:18:09 PM PDT 24
Finished Mar 19 02:18:32 PM PDT 24
Peak memory 249640 kb
Host smart-6e61a311-ca7e-4292-b29b-8354f70afbeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2500448714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.2500448714
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.2983814140
Short name T15
Test name
Test status
Simulation time 6394978881 ps
CPU time 48.1 seconds
Started Mar 19 02:18:07 PM PDT 24
Finished Mar 19 02:18:56 PM PDT 24
Peak memory 241432 kb
Host smart-d684c10e-ff4d-4796-ab2b-09687ef2d485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983814140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.2983814140
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.2184257686
Short name T397
Test name
Test status
Simulation time 37315693950 ps
CPU time 65.38 seconds
Started Mar 19 02:18:09 PM PDT 24
Finished Mar 19 02:19:14 PM PDT 24
Peak memory 249604 kb
Host smart-dd5ca104-a9e6-49a1-8802-56671dfc19df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2184257686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idl
e.2184257686
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.51577785
Short name T883
Test name
Test status
Simulation time 5821189471 ps
CPU time 41.64 seconds
Started Mar 19 02:17:55 PM PDT 24
Finished Mar 19 02:18:36 PM PDT 24
Peak memory 239532 kb
Host smart-e68252b4-8b5f-4bc6-be7e-83d22445e86d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51577785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.51577785
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_intercept.159656154
Short name T627
Test name
Test status
Simulation time 1686921250 ps
CPU time 6.93 seconds
Started Mar 19 02:17:58 PM PDT 24
Finished Mar 19 02:18:05 PM PDT 24
Peak memory 218468 kb
Host smart-da1f5e56-ad42-443b-8989-87205d411202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=159656154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.159656154
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.2275367661
Short name T955
Test name
Test status
Simulation time 200778962 ps
CPU time 5.67 seconds
Started Mar 19 02:17:53 PM PDT 24
Finished Mar 19 02:17:59 PM PDT 24
Peak memory 236268 kb
Host smart-dde9c379-17bd-4781-878e-0bea62fb9873
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275367661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.2275367661
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.2929242340
Short name T269
Test name
Test status
Simulation time 4016302517 ps
CPU time 14.89 seconds
Started Mar 19 02:17:57 PM PDT 24
Finished Mar 19 02:18:12 PM PDT 24
Peak memory 234272 kb
Host smart-861c7867-129c-485d-a233-bd3eada2a7fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2929242340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swa
p.2929242340
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.3885705978
Short name T824
Test name
Test status
Simulation time 10265896341 ps
CPU time 16.22 seconds
Started Mar 19 02:17:55 PM PDT 24
Finished Mar 19 02:18:12 PM PDT 24
Peak memory 234776 kb
Host smart-2da52d66-3da6-41e9-aeac-0a87eb75bec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885705978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.3885705978
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.2586427723
Short name T141
Test name
Test status
Simulation time 684077324 ps
CPU time 3.53 seconds
Started Mar 19 02:18:00 PM PDT 24
Finished Mar 19 02:18:04 PM PDT 24
Peak memory 220708 kb
Host smart-2307e7be-ec9d-4023-9330-ab90276d76c4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2586427723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dir
ect.2586427723
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.1468966959
Short name T735
Test name
Test status
Simulation time 259620827 ps
CPU time 2.29 seconds
Started Mar 19 02:17:56 PM PDT 24
Finished Mar 19 02:17:59 PM PDT 24
Peak memory 216772 kb
Host smart-d4619ff1-d010-44cf-be31-d87d60371165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468966959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.1468966959
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.3002606599
Short name T503
Test name
Test status
Simulation time 563551753 ps
CPU time 4.42 seconds
Started Mar 19 02:17:56 PM PDT 24
Finished Mar 19 02:18:00 PM PDT 24
Peak memory 216548 kb
Host smart-5bd5cb45-5e2a-4408-ab03-ddcd97bd0535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3002606599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.3002606599
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.3477896059
Short name T540
Test name
Test status
Simulation time 320608938 ps
CPU time 2.55 seconds
Started Mar 19 02:17:56 PM PDT 24
Finished Mar 19 02:18:00 PM PDT 24
Peak memory 217128 kb
Host smart-7038e5dc-c81c-403b-b262-bba206b447f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477896059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.3477896059
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.1735865664
Short name T524
Test name
Test status
Simulation time 19594218 ps
CPU time 0.74 seconds
Started Mar 19 02:18:00 PM PDT 24
Finished Mar 19 02:18:01 PM PDT 24
Peak memory 205840 kb
Host smart-038ad551-fd59-4c8d-8e6f-dc491ad7c984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735865664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.1735865664
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.1082626241
Short name T601
Test name
Test status
Simulation time 1432070948 ps
CPU time 6.26 seconds
Started Mar 19 02:17:56 PM PDT 24
Finished Mar 19 02:18:03 PM PDT 24
Peak memory 234812 kb
Host smart-10af6f58-ac26-477f-b538-1adef50b308a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1082626241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.1082626241
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.3189415788
Short name T302
Test name
Test status
Simulation time 12962635 ps
CPU time 0.74 seconds
Started Mar 19 02:18:19 PM PDT 24
Finished Mar 19 02:18:20 PM PDT 24
Peak memory 205668 kb
Host smart-92381eb7-ce37-437b-8309-5ecd2bddfcb1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189415788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.
3189415788
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.923493419
Short name T558
Test name
Test status
Simulation time 86041626 ps
CPU time 2.57 seconds
Started Mar 19 02:18:10 PM PDT 24
Finished Mar 19 02:18:12 PM PDT 24
Peak memory 233756 kb
Host smart-bc183f76-8b1d-4f80-badb-507475bb67e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923493419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.923493419
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.32828352
Short name T572
Test name
Test status
Simulation time 35927468 ps
CPU time 0.76 seconds
Started Mar 19 02:18:05 PM PDT 24
Finished Mar 19 02:18:07 PM PDT 24
Peak memory 206676 kb
Host smart-69f86f37-973e-4c73-a0e6-8b3cab513238
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32828352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.32828352
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.3772547999
Short name T707
Test name
Test status
Simulation time 28585721063 ps
CPU time 165.87 seconds
Started Mar 19 02:18:08 PM PDT 24
Finished Mar 19 02:20:54 PM PDT 24
Peak memory 264132 kb
Host smart-cdbf8617-2801-445c-94a7-5cda27691055
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772547999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.3772547999
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.3463604062
Short name T195
Test name
Test status
Simulation time 13906672720 ps
CPU time 136.31 seconds
Started Mar 19 02:18:09 PM PDT 24
Finished Mar 19 02:20:26 PM PDT 24
Peak memory 264536 kb
Host smart-7b9e489f-88f8-454f-ac2e-5c66e1fbb5a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3463604062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.3463604062
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.4051148384
Short name T266
Test name
Test status
Simulation time 55050601165 ps
CPU time 152.42 seconds
Started Mar 19 02:18:17 PM PDT 24
Finished Mar 19 02:20:50 PM PDT 24
Peak memory 273152 kb
Host smart-3a0a989a-7c1b-4f96-a0d8-ba47ae777c52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4051148384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idl
e.4051148384
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.2366312320
Short name T579
Test name
Test status
Simulation time 6238810558 ps
CPU time 15.74 seconds
Started Mar 19 02:18:08 PM PDT 24
Finished Mar 19 02:18:24 PM PDT 24
Peak memory 256744 kb
Host smart-7f6b3b2f-01a9-419b-8627-0b14056113f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2366312320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.2366312320
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_intercept.2269126516
Short name T247
Test name
Test status
Simulation time 101785849 ps
CPU time 2.65 seconds
Started Mar 19 02:18:09 PM PDT 24
Finished Mar 19 02:18:12 PM PDT 24
Peak memory 233092 kb
Host smart-0a535293-ef84-4bf7-a966-db04ddbd5c86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2269126516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.2269126516
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.3835393729
Short name T799
Test name
Test status
Simulation time 82133062318 ps
CPU time 34.2 seconds
Started Mar 19 02:18:09 PM PDT 24
Finished Mar 19 02:18:43 PM PDT 24
Peak memory 227096 kb
Host smart-d4facbe2-18f8-465d-9f66-ad37e555f89a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3835393729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.3835393729
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.2320257770
Short name T859
Test name
Test status
Simulation time 546362467 ps
CPU time 8.13 seconds
Started Mar 19 02:18:07 PM PDT 24
Finished Mar 19 02:18:15 PM PDT 24
Peak memory 228568 kb
Host smart-64516b2f-4221-45f7-a2c1-03a11bafeb37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2320257770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swa
p.2320257770
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.475532188
Short name T969
Test name
Test status
Simulation time 8166203169 ps
CPU time 14.35 seconds
Started Mar 19 02:18:06 PM PDT 24
Finished Mar 19 02:18:21 PM PDT 24
Peak memory 241352 kb
Host smart-29002b90-a2a3-4ba3-b0ef-bd0c17751356
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=475532188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.475532188
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.396128780
Short name T338
Test name
Test status
Simulation time 223549525 ps
CPU time 3.69 seconds
Started Mar 19 02:18:06 PM PDT 24
Finished Mar 19 02:18:10 PM PDT 24
Peak memory 223120 kb
Host smart-ba8b822b-7271-4fe1-845a-83da1aa7c732
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=396128780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dire
ct.396128780
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.2841865722
Short name T156
Test name
Test status
Simulation time 119193835306 ps
CPU time 864.67 seconds
Started Mar 19 02:18:23 PM PDT 24
Finished Mar 19 02:32:48 PM PDT 24
Peak memory 274308 kb
Host smart-af32d003-94ca-452b-a1a4-9befe6145a4a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841865722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stre
ss_all.2841865722
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.2498244745
Short name T519
Test name
Test status
Simulation time 16388571126 ps
CPU time 85.37 seconds
Started Mar 19 02:18:09 PM PDT 24
Finished Mar 19 02:19:34 PM PDT 24
Peak memory 216832 kb
Host smart-f77fbd07-4ec9-4090-b617-9f02d19e2528
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2498244745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.2498244745
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.1097551756
Short name T776
Test name
Test status
Simulation time 7776708367 ps
CPU time 19.18 seconds
Started Mar 19 02:18:06 PM PDT 24
Finished Mar 19 02:18:26 PM PDT 24
Peak memory 216696 kb
Host smart-2c0efc13-9c25-4ebf-9c0d-b5ea65cbf7aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1097551756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.1097551756
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.856968443
Short name T772
Test name
Test status
Simulation time 1206024949 ps
CPU time 10.74 seconds
Started Mar 19 02:18:06 PM PDT 24
Finished Mar 19 02:18:17 PM PDT 24
Peak memory 216772 kb
Host smart-71399d0d-286f-41e1-8d6d-bf9efeaaf370
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=856968443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.856968443
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.3818789994
Short name T674
Test name
Test status
Simulation time 143704623 ps
CPU time 0.97 seconds
Started Mar 19 02:18:13 PM PDT 24
Finished Mar 19 02:18:14 PM PDT 24
Peak memory 206316 kb
Host smart-fa71f20e-b9a3-497d-8963-a9529b94346c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3818789994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.3818789994
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.1644633148
Short name T555
Test name
Test status
Simulation time 10292937124 ps
CPU time 31.6 seconds
Started Mar 19 02:18:07 PM PDT 24
Finished Mar 19 02:18:39 PM PDT 24
Peak memory 241436 kb
Host smart-14d82e45-4f92-4fa4-b53c-b5a25e257687
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644633148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.1644633148
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.4291278954
Short name T29
Test name
Test status
Simulation time 15587269 ps
CPU time 0.76 seconds
Started Mar 19 02:18:22 PM PDT 24
Finished Mar 19 02:18:23 PM PDT 24
Peak memory 205628 kb
Host smart-b51a7464-b067-4d6b-bd21-fc047b18936d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291278954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.
4291278954
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.3132028906
Short name T213
Test name
Test status
Simulation time 3221969105 ps
CPU time 7.19 seconds
Started Mar 19 02:18:17 PM PDT 24
Finished Mar 19 02:18:24 PM PDT 24
Peak memory 234412 kb
Host smart-ee83ef73-f8ba-4e54-bcf3-341a6846b4d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3132028906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.3132028906
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.2140010319
Short name T445
Test name
Test status
Simulation time 14387513 ps
CPU time 0.81 seconds
Started Mar 19 02:18:20 PM PDT 24
Finished Mar 19 02:18:21 PM PDT 24
Peak memory 206720 kb
Host smart-d38c8d03-e79b-46f0-b29b-25e1f1a1ae62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2140010319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.2140010319
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.1598202745
Short name T687
Test name
Test status
Simulation time 1669525492 ps
CPU time 15.65 seconds
Started Mar 19 02:18:21 PM PDT 24
Finished Mar 19 02:18:37 PM PDT 24
Peak memory 250956 kb
Host smart-4bce02bd-f808-4c52-ade8-f3b948307549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598202745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.1598202745
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.687439915
Short name T528
Test name
Test status
Simulation time 1939685222 ps
CPU time 44.15 seconds
Started Mar 19 02:18:38 PM PDT 24
Finished Mar 19 02:19:22 PM PDT 24
Peak memory 241328 kb
Host smart-e332e885-bbd8-48d8-a557-f50036c61490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687439915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.687439915
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.213248534
Short name T54
Test name
Test status
Simulation time 18948668113 ps
CPU time 108.69 seconds
Started Mar 19 02:18:24 PM PDT 24
Finished Mar 19 02:20:13 PM PDT 24
Peak memory 262024 kb
Host smart-1eb62805-4bd7-4d4a-8b06-df3ab74ae092
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=213248534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idle
.213248534
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.2558774955
Short name T592
Test name
Test status
Simulation time 1747081814 ps
CPU time 8.73 seconds
Started Mar 19 02:18:17 PM PDT 24
Finished Mar 19 02:18:26 PM PDT 24
Peak memory 233096 kb
Host smart-9ca71540-5704-4c94-adf0-a166a7b12a91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558774955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.2558774955
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_intercept.742293033
Short name T385
Test name
Test status
Simulation time 13586655577 ps
CPU time 9.75 seconds
Started Mar 19 02:18:17 PM PDT 24
Finished Mar 19 02:18:26 PM PDT 24
Peak memory 220956 kb
Host smart-173d277e-bde8-419a-98c0-41405dbe2e5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=742293033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.742293033
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.2490815710
Short name T850
Test name
Test status
Simulation time 3583144350 ps
CPU time 12.6 seconds
Started Mar 19 02:18:21 PM PDT 24
Finished Mar 19 02:18:34 PM PDT 24
Peak memory 233276 kb
Host smart-f23e0350-0fd1-4aee-9aab-642754a79228
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2490815710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.2490815710
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.3936591207
Short name T544
Test name
Test status
Simulation time 13065040586 ps
CPU time 15.9 seconds
Started Mar 19 02:18:16 PM PDT 24
Finished Mar 19 02:18:32 PM PDT 24
Peak memory 233952 kb
Host smart-bcc441b9-be5e-459f-82cc-27106fec226e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936591207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.3936591207
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.341303174
Short name T55
Test name
Test status
Simulation time 6170336147 ps
CPU time 6.47 seconds
Started Mar 19 02:18:17 PM PDT 24
Finished Mar 19 02:18:24 PM PDT 24
Peak memory 220284 kb
Host smart-917db77c-ccee-4633-a7bd-eebd2f7f6b1e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=341303174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dire
ct.341303174
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.3004984745
Short name T94
Test name
Test status
Simulation time 183868313661 ps
CPU time 357.03 seconds
Started Mar 19 02:18:17 PM PDT 24
Finished Mar 19 02:24:14 PM PDT 24
Peak memory 282328 kb
Host smart-baddc96d-b106-4923-9fbf-a29fcc8982c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004984745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stre
ss_all.3004984745
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.4294642434
Short name T856
Test name
Test status
Simulation time 15412708342 ps
CPU time 79.58 seconds
Started Mar 19 02:18:18 PM PDT 24
Finished Mar 19 02:19:37 PM PDT 24
Peak memory 216824 kb
Host smart-85b92f34-fe0f-4cf3-8645-5abc7bb9c1dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4294642434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.4294642434
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.429880789
Short name T410
Test name
Test status
Simulation time 31726103068 ps
CPU time 24.48 seconds
Started Mar 19 02:18:19 PM PDT 24
Finished Mar 19 02:18:44 PM PDT 24
Peak memory 216756 kb
Host smart-c9ac7adc-1f72-404f-b55a-6dd8dd36c472
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=429880789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.429880789
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.2012120200
Short name T320
Test name
Test status
Simulation time 453338381 ps
CPU time 9.36 seconds
Started Mar 19 02:18:17 PM PDT 24
Finished Mar 19 02:18:26 PM PDT 24
Peak memory 216824 kb
Host smart-a471497e-8f14-4fbd-acc5-a02f6b8885aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012120200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.2012120200
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.3428580266
Short name T704
Test name
Test status
Simulation time 290686176 ps
CPU time 1.01 seconds
Started Mar 19 02:18:17 PM PDT 24
Finished Mar 19 02:18:18 PM PDT 24
Peak memory 206972 kb
Host smart-6b8bfa39-571b-4814-b3de-2fe8be9c2f56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3428580266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.3428580266
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.4256552115
Short name T160
Test name
Test status
Simulation time 3142332192 ps
CPU time 13.38 seconds
Started Mar 19 02:18:19 PM PDT 24
Finished Mar 19 02:18:32 PM PDT 24
Peak memory 234060 kb
Host smart-ef2c91e8-1932-475e-86b0-c887b6fb911b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4256552115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.4256552115
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.703983932
Short name T648
Test name
Test status
Simulation time 35876713 ps
CPU time 0.75 seconds
Started Mar 19 02:18:32 PM PDT 24
Finished Mar 19 02:18:33 PM PDT 24
Peak memory 205912 kb
Host smart-a1a6a578-76dd-4e30-8713-eb8eeb7e32c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703983932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.703983932
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.2407130836
Short name T224
Test name
Test status
Simulation time 513860723 ps
CPU time 2.89 seconds
Started Mar 19 02:18:24 PM PDT 24
Finished Mar 19 02:18:27 PM PDT 24
Peak memory 224940 kb
Host smart-9ada68ce-912a-40d2-a8f0-41d11568bc45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2407130836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.2407130836
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.1198163222
Short name T290
Test name
Test status
Simulation time 39794322 ps
CPU time 0.86 seconds
Started Mar 19 02:18:17 PM PDT 24
Finished Mar 19 02:18:18 PM PDT 24
Peak memory 206676 kb
Host smart-8d9c2dad-583a-49a4-a644-f64fa44e01a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1198163222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.1198163222
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.3398192746
Short name T693
Test name
Test status
Simulation time 9456926297 ps
CPU time 47.26 seconds
Started Mar 19 02:18:32 PM PDT 24
Finished Mar 19 02:19:20 PM PDT 24
Peak memory 256324 kb
Host smart-1719a0bc-ef41-4ac5-b37a-acdb1815bd58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3398192746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.3398192746
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.2306667367
Short name T647
Test name
Test status
Simulation time 53237055550 ps
CPU time 37.64 seconds
Started Mar 19 02:18:28 PM PDT 24
Finished Mar 19 02:19:06 PM PDT 24
Peak memory 222264 kb
Host smart-32190c41-e292-4514-8f0a-a8fb24eeb655
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2306667367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idl
e.2306667367
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.292735853
Short name T279
Test name
Test status
Simulation time 34590057993 ps
CPU time 47.46 seconds
Started Mar 19 02:18:27 PM PDT 24
Finished Mar 19 02:19:15 PM PDT 24
Peak memory 233784 kb
Host smart-bd6295e8-9990-446a-ad56-bbeef79199e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292735853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.292735853
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_intercept.2136684711
Short name T931
Test name
Test status
Simulation time 1119132723 ps
CPU time 5.15 seconds
Started Mar 19 02:18:17 PM PDT 24
Finished Mar 19 02:18:23 PM PDT 24
Peak memory 225012 kb
Host smart-92373cf4-f1c6-49d4-a0c9-46f1fd137480
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2136684711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.2136684711
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.158412918
Short name T221
Test name
Test status
Simulation time 26423136506 ps
CPU time 24.31 seconds
Started Mar 19 02:18:17 PM PDT 24
Finished Mar 19 02:18:42 PM PDT 24
Peak memory 235780 kb
Host smart-0dd995d3-549e-485c-8f6e-12201c7f9b57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158412918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.158412918
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.3004727609
Short name T836
Test name
Test status
Simulation time 4580166058 ps
CPU time 14.68 seconds
Started Mar 19 02:18:20 PM PDT 24
Finished Mar 19 02:18:36 PM PDT 24
Peak memory 241364 kb
Host smart-556255ef-5470-4adc-a611-1c64c76df89a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3004727609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swa
p.3004727609
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.1990369635
Short name T748
Test name
Test status
Simulation time 5330493639 ps
CPU time 14.21 seconds
Started Mar 19 02:18:22 PM PDT 24
Finished Mar 19 02:18:36 PM PDT 24
Peak memory 225080 kb
Host smart-1e1b2973-046e-4fe3-bee7-7dcd178bf4db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990369635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.1990369635
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.3991332678
Short name T424
Test name
Test status
Simulation time 419191665 ps
CPU time 3.61 seconds
Started Mar 19 02:18:35 PM PDT 24
Finished Mar 19 02:18:40 PM PDT 24
Peak memory 223256 kb
Host smart-abd7cb89-15e0-42ea-a254-873153ffb784
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3991332678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dir
ect.3991332678
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.3666601055
Short name T201
Test name
Test status
Simulation time 57861372716 ps
CPU time 232.96 seconds
Started Mar 19 02:18:32 PM PDT 24
Finished Mar 19 02:22:25 PM PDT 24
Peak memory 260576 kb
Host smart-d6ca3ae4-7ab1-4580-81ce-d6267f881923
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666601055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stre
ss_all.3666601055
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.4262562038
Short name T585
Test name
Test status
Simulation time 42050233376 ps
CPU time 54.85 seconds
Started Mar 19 02:18:19 PM PDT 24
Finished Mar 19 02:19:14 PM PDT 24
Peak memory 216796 kb
Host smart-6ce64190-db7e-427f-a820-5729ea25ab6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4262562038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.4262562038
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.1895868576
Short name T11
Test name
Test status
Simulation time 14158152184 ps
CPU time 24.07 seconds
Started Mar 19 02:18:18 PM PDT 24
Finished Mar 19 02:18:42 PM PDT 24
Peak memory 216644 kb
Host smart-d17b1d01-c490-4dfc-a474-cd5fb6caa77a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1895868576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.1895868576
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.1511944726
Short name T576
Test name
Test status
Simulation time 846560137 ps
CPU time 5.55 seconds
Started Mar 19 02:18:24 PM PDT 24
Finished Mar 19 02:18:30 PM PDT 24
Peak memory 216708 kb
Host smart-a10252d4-7757-45a2-82c6-4b158ff5e72a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511944726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.1511944726
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.1132275569
Short name T653
Test name
Test status
Simulation time 643615597 ps
CPU time 0.91 seconds
Started Mar 19 02:18:18 PM PDT 24
Finished Mar 19 02:18:19 PM PDT 24
Peak memory 205872 kb
Host smart-12a545e8-8fbb-4dbe-9988-cc3c4feac6db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1132275569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.1132275569
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.1445508497
Short name T81
Test name
Test status
Simulation time 2850353879 ps
CPU time 13.43 seconds
Started Mar 19 02:18:20 PM PDT 24
Finished Mar 19 02:18:34 PM PDT 24
Peak memory 219620 kb
Host smart-1c2af75e-fcfc-4a46-84dc-15c2086592e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1445508497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.1445508497
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.2528904483
Short name T392
Test name
Test status
Simulation time 13588362 ps
CPU time 0.73 seconds
Started Mar 19 02:18:31 PM PDT 24
Finished Mar 19 02:18:32 PM PDT 24
Peak memory 205072 kb
Host smart-8bb76bfe-b58e-43e8-ba2d-9618c7218afd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528904483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.
2528904483
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.2984084460
Short name T826
Test name
Test status
Simulation time 1228992540 ps
CPU time 5.92 seconds
Started Mar 19 02:18:29 PM PDT 24
Finished Mar 19 02:18:35 PM PDT 24
Peak memory 233760 kb
Host smart-cdea099b-13ec-494a-a5a8-baf9c107c385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2984084460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.2984084460
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.148695237
Short name T603
Test name
Test status
Simulation time 75072175 ps
CPU time 0.81 seconds
Started Mar 19 02:18:28 PM PDT 24
Finished Mar 19 02:18:29 PM PDT 24
Peak memory 206724 kb
Host smart-53409c98-7de5-446d-81bd-168532ba626f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=148695237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.148695237
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.67752518
Short name T133
Test name
Test status
Simulation time 14105285337 ps
CPU time 124.77 seconds
Started Mar 19 02:18:32 PM PDT 24
Finished Mar 19 02:20:37 PM PDT 24
Peak memory 259484 kb
Host smart-e29cdcff-49a3-450a-9f9b-4ba807cd0ea8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67752518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.67752518
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.2478765559
Short name T842
Test name
Test status
Simulation time 100579846369 ps
CPU time 258.1 seconds
Started Mar 19 02:18:30 PM PDT 24
Finished Mar 19 02:22:49 PM PDT 24
Peak memory 257776 kb
Host smart-dd34fea2-a34c-4b83-ba79-0252001fce94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2478765559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idl
e.2478765559
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.96774918
Short name T357
Test name
Test status
Simulation time 23711440308 ps
CPU time 38.26 seconds
Started Mar 19 02:18:25 PM PDT 24
Finished Mar 19 02:19:03 PM PDT 24
Peak memory 249416 kb
Host smart-c384f825-a24f-4a1e-b01d-92b53c563e97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96774918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.96774918
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_intercept.2109211786
Short name T356
Test name
Test status
Simulation time 346005168 ps
CPU time 4.09 seconds
Started Mar 19 02:18:28 PM PDT 24
Finished Mar 19 02:18:32 PM PDT 24
Peak memory 234092 kb
Host smart-20c405a3-9040-457a-839b-4b3f741ff297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2109211786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.2109211786
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.3797993704
Short name T630
Test name
Test status
Simulation time 11047644512 ps
CPU time 15.12 seconds
Started Mar 19 02:18:26 PM PDT 24
Finished Mar 19 02:18:41 PM PDT 24
Peak memory 233236 kb
Host smart-eef35cc8-1217-4901-94f2-f0fbdf88f610
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3797993704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.3797993704
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.3657607401
Short name T234
Test name
Test status
Simulation time 89262006 ps
CPU time 2.91 seconds
Started Mar 19 02:18:26 PM PDT 24
Finished Mar 19 02:18:30 PM PDT 24
Peak memory 234104 kb
Host smart-3755a4fe-c847-44ba-bfeb-a8257ef2c563
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3657607401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swa
p.3657607401
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.3966437440
Short name T7
Test name
Test status
Simulation time 10355703453 ps
CPU time 6.94 seconds
Started Mar 19 02:18:30 PM PDT 24
Finished Mar 19 02:18:37 PM PDT 24
Peak memory 221416 kb
Host smart-55abab2f-1888-4d96-8856-8d9a6ee73867
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966437440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.3966437440
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.2466767236
Short name T43
Test name
Test status
Simulation time 172562312 ps
CPU time 3.77 seconds
Started Mar 19 02:18:26 PM PDT 24
Finished Mar 19 02:18:31 PM PDT 24
Peak memory 223392 kb
Host smart-a3e06693-20ce-4c8d-8b2c-51dc69080704
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2466767236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dir
ect.2466767236
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.555527592
Short name T157
Test name
Test status
Simulation time 158210807242 ps
CPU time 240.08 seconds
Started Mar 19 02:18:27 PM PDT 24
Finished Mar 19 02:22:28 PM PDT 24
Peak memory 255504 kb
Host smart-8c9b2fdb-1396-4bfd-8f33-3c2f16ebf0d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555527592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stres
s_all.555527592
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.2422645542
Short name T164
Test name
Test status
Simulation time 20663283550 ps
CPU time 43.46 seconds
Started Mar 19 02:18:27 PM PDT 24
Finished Mar 19 02:19:10 PM PDT 24
Peak memory 216708 kb
Host smart-18e4f966-d5bb-4f5b-9aa8-fbd749d56145
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422645542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.2422645542
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.3479341781
Short name T620
Test name
Test status
Simulation time 6324963988 ps
CPU time 10.66 seconds
Started Mar 19 02:18:27 PM PDT 24
Finished Mar 19 02:18:38 PM PDT 24
Peak memory 216772 kb
Host smart-bbcd63f2-9df1-4b69-b80b-00451dbe3828
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479341781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.3479341781
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.3969392082
Short name T325
Test name
Test status
Simulation time 309380244 ps
CPU time 14.76 seconds
Started Mar 19 02:18:26 PM PDT 24
Finished Mar 19 02:18:41 PM PDT 24
Peak memory 216620 kb
Host smart-123537fd-4e6c-4345-a229-c4b14d403f28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3969392082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.3969392082
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.574354483
Short name T313
Test name
Test status
Simulation time 64121041 ps
CPU time 0.92 seconds
Started Mar 19 02:18:23 PM PDT 24
Finished Mar 19 02:18:24 PM PDT 24
Peak memory 205952 kb
Host smart-abc68cff-ed9b-4714-8e4b-a34698bf2084
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=574354483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.574354483
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.2058127368
Short name T364
Test name
Test status
Simulation time 581513058 ps
CPU time 2.99 seconds
Started Mar 19 02:18:29 PM PDT 24
Finished Mar 19 02:18:32 PM PDT 24
Peak memory 225000 kb
Host smart-1577cdb1-2b55-4e35-b4a6-a4c28fbc92d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2058127368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.2058127368
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.3032705626
Short name T527
Test name
Test status
Simulation time 13096380 ps
CPU time 0.69 seconds
Started Mar 19 02:18:40 PM PDT 24
Finished Mar 19 02:18:41 PM PDT 24
Peak memory 205672 kb
Host smart-934592ec-7f3a-40a6-9125-73794ffc9945
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032705626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.
3032705626
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.3937715235
Short name T811
Test name
Test status
Simulation time 125165313 ps
CPU time 3.58 seconds
Started Mar 19 02:18:39 PM PDT 24
Finished Mar 19 02:18:42 PM PDT 24
Peak memory 224912 kb
Host smart-95691ada-b57e-4d4e-b954-7d611633d41c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937715235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.3937715235
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.2314454929
Short name T13
Test name
Test status
Simulation time 15122403 ps
CPU time 0.78 seconds
Started Mar 19 02:18:32 PM PDT 24
Finished Mar 19 02:18:33 PM PDT 24
Peak memory 206668 kb
Host smart-06cb71b8-323b-48bb-920c-9742f48ee486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2314454929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.2314454929
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.765244633
Short name T193
Test name
Test status
Simulation time 79602898300 ps
CPU time 357.33 seconds
Started Mar 19 02:18:35 PM PDT 24
Finished Mar 19 02:24:33 PM PDT 24
Peak memory 257172 kb
Host smart-cbe207b6-432b-43ec-9a1a-ca9527bd2f06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=765244633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.765244633
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.3836713826
Short name T240
Test name
Test status
Simulation time 22235703698 ps
CPU time 206.7 seconds
Started Mar 19 02:18:39 PM PDT 24
Finished Mar 19 02:22:06 PM PDT 24
Peak memory 251792 kb
Host smart-7e19ffe0-c39e-41f1-8e5f-64266c50d323
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3836713826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.3836713826
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.2065085897
Short name T64
Test name
Test status
Simulation time 1966740303 ps
CPU time 38.72 seconds
Started Mar 19 02:18:38 PM PDT 24
Finished Mar 19 02:19:17 PM PDT 24
Peak memory 239696 kb
Host smart-81a13c17-7a79-4e16-9828-194612ccc64e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065085897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idl
e.2065085897
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.3584397268
Short name T525
Test name
Test status
Simulation time 6635811490 ps
CPU time 36.78 seconds
Started Mar 19 02:18:39 PM PDT 24
Finished Mar 19 02:19:16 PM PDT 24
Peak memory 249140 kb
Host smart-cb8aabbe-db4c-4302-b5f0-a0312f2d7355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584397268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.3584397268
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_intercept.797108240
Short name T672
Test name
Test status
Simulation time 7128111923 ps
CPU time 9.62 seconds
Started Mar 19 02:18:37 PM PDT 24
Finished Mar 19 02:18:47 PM PDT 24
Peak memory 225084 kb
Host smart-c2d51aa7-fe65-4488-a9d0-e126d37366be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=797108240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.797108240
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.3158134427
Short name T32
Test name
Test status
Simulation time 876624227 ps
CPU time 5.23 seconds
Started Mar 19 02:18:38 PM PDT 24
Finished Mar 19 02:18:43 PM PDT 24
Peak memory 217836 kb
Host smart-a97d0fbb-7616-48a2-816d-073a00c4ef8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158134427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.3158134427
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.2712883990
Short name T96
Test name
Test status
Simulation time 4701745179 ps
CPU time 15.83 seconds
Started Mar 19 02:18:36 PM PDT 24
Finished Mar 19 02:18:52 PM PDT 24
Peak memory 234228 kb
Host smart-cdb75c00-a007-45f3-9e13-1f07ce28e9a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712883990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swa
p.2712883990
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.3781141281
Short name T398
Test name
Test status
Simulation time 8000465636 ps
CPU time 26.47 seconds
Started Mar 19 02:18:38 PM PDT 24
Finished Mar 19 02:19:04 PM PDT 24
Peak memory 248220 kb
Host smart-e98cd6f0-e92f-4311-8cd6-ccf23a1dedf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3781141281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.3781141281
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.3117001425
Short name T456
Test name
Test status
Simulation time 3472539940 ps
CPU time 6.94 seconds
Started Mar 19 02:18:40 PM PDT 24
Finished Mar 19 02:18:47 PM PDT 24
Peak memory 223392 kb
Host smart-1b681e26-8992-43ab-91d3-c4212faacf55
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3117001425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dir
ect.3117001425
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.605200041
Short name T522
Test name
Test status
Simulation time 257271583 ps
CPU time 0.95 seconds
Started Mar 19 02:18:38 PM PDT 24
Finished Mar 19 02:18:39 PM PDT 24
Peak memory 206736 kb
Host smart-92412b0d-15e3-4d5d-9b4d-b3d93b03b9e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605200041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stres
s_all.605200041
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.981390345
Short name T949
Test name
Test status
Simulation time 4795355120 ps
CPU time 38.2 seconds
Started Mar 19 02:18:38 PM PDT 24
Finished Mar 19 02:19:16 PM PDT 24
Peak memory 215708 kb
Host smart-3e0c246e-59b8-48f5-b486-1f078511da74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981390345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.981390345
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.4073929695
Short name T286
Test name
Test status
Simulation time 3319830667 ps
CPU time 15.66 seconds
Started Mar 19 02:18:37 PM PDT 24
Finished Mar 19 02:18:53 PM PDT 24
Peak memory 216688 kb
Host smart-4e4f35b5-c94c-4671-a8c4-fdd135bef184
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4073929695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.4073929695
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.692196799
Short name T296
Test name
Test status
Simulation time 105544748 ps
CPU time 3.77 seconds
Started Mar 19 02:18:38 PM PDT 24
Finished Mar 19 02:18:42 PM PDT 24
Peak memory 216644 kb
Host smart-60553605-92e8-446c-b48b-6c153ac6a53a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692196799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.692196799
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.1500644860
Short name T348
Test name
Test status
Simulation time 41480606 ps
CPU time 0.9 seconds
Started Mar 19 02:18:39 PM PDT 24
Finished Mar 19 02:18:40 PM PDT 24
Peak memory 206196 kb
Host smart-8ed76e25-d77d-4c25-8794-0d0975be28ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1500644860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.1500644860
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.3365979835
Short name T591
Test name
Test status
Simulation time 10070687097 ps
CPU time 33.75 seconds
Started Mar 19 02:18:36 PM PDT 24
Finished Mar 19 02:19:10 PM PDT 24
Peak memory 247340 kb
Host smart-451cdeb0-30fe-4267-89d6-8e4544b412a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3365979835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.3365979835
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.4124365494
Short name T881
Test name
Test status
Simulation time 16670136 ps
CPU time 0.7 seconds
Started Mar 19 02:18:51 PM PDT 24
Finished Mar 19 02:18:52 PM PDT 24
Peak memory 205604 kb
Host smart-d0ecfde3-1c5d-4c13-959e-3b2a9f34da3c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124365494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.
4124365494
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.2502473297
Short name T372
Test name
Test status
Simulation time 761960975 ps
CPU time 4.69 seconds
Started Mar 19 02:18:47 PM PDT 24
Finished Mar 19 02:18:52 PM PDT 24
Peak memory 234724 kb
Host smart-e3fd9ebf-6c2d-44d3-9632-9efc86ff8f65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2502473297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.2502473297
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.3726250731
Short name T952
Test name
Test status
Simulation time 19727910 ps
CPU time 0.78 seconds
Started Mar 19 02:18:37 PM PDT 24
Finished Mar 19 02:18:38 PM PDT 24
Peak memory 207092 kb
Host smart-7983ea54-e94c-4d76-9141-45b8d160bbb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3726250731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.3726250731
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.3815848581
Short name T231
Test name
Test status
Simulation time 72394041729 ps
CPU time 93.07 seconds
Started Mar 19 02:18:48 PM PDT 24
Finished Mar 19 02:20:22 PM PDT 24
Peak memory 238332 kb
Host smart-eee62dbb-abf6-4f33-bb98-49cb14d6f196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815848581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.3815848581
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.2124801258
Short name T858
Test name
Test status
Simulation time 12728841795 ps
CPU time 58.27 seconds
Started Mar 19 02:18:47 PM PDT 24
Finished Mar 19 02:19:46 PM PDT 24
Peak memory 259848 kb
Host smart-ee614a45-0748-4c45-b396-7b2ddd45978b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2124801258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.2124801258
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.640414347
Short name T259
Test name
Test status
Simulation time 15415035419 ps
CPU time 109.9 seconds
Started Mar 19 02:18:49 PM PDT 24
Finished Mar 19 02:20:39 PM PDT 24
Peak memory 249676 kb
Host smart-ffbe5ba1-c50c-4d52-9991-28727bdc9c67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=640414347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idle
.640414347
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.2811325111
Short name T723
Test name
Test status
Simulation time 3992364181 ps
CPU time 31.07 seconds
Started Mar 19 02:18:48 PM PDT 24
Finished Mar 19 02:19:20 PM PDT 24
Peak memory 246604 kb
Host smart-a7b46553-90f8-4ee5-9f8f-4a7591fab8bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2811325111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.2811325111
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_intercept.681294089
Short name T928
Test name
Test status
Simulation time 1416976269 ps
CPU time 6.05 seconds
Started Mar 19 02:18:47 PM PDT 24
Finished Mar 19 02:18:53 PM PDT 24
Peak memory 219904 kb
Host smart-9752978f-28a4-4360-bc10-f6fd983f39b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=681294089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.681294089
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.3620419422
Short name T657
Test name
Test status
Simulation time 745293261 ps
CPU time 6.81 seconds
Started Mar 19 02:18:51 PM PDT 24
Finished Mar 19 02:18:58 PM PDT 24
Peak memory 232696 kb
Host smart-cab8480e-5033-4177-b0d2-f2b8d18b4588
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3620419422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.3620419422
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.1704682534
Short name T785
Test name
Test status
Simulation time 7570281446 ps
CPU time 11.99 seconds
Started Mar 19 02:18:48 PM PDT 24
Finished Mar 19 02:19:00 PM PDT 24
Peak memory 234300 kb
Host smart-df1b3e73-219a-44af-a47b-8b06e46a1bdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1704682534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swa
p.1704682534
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.945396305
Short name T654
Test name
Test status
Simulation time 1078114770 ps
CPU time 10.13 seconds
Started Mar 19 02:18:45 PM PDT 24
Finished Mar 19 02:18:56 PM PDT 24
Peak memory 240432 kb
Host smart-6c7ec29e-051a-49c0-ae42-4184f4187fd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=945396305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.945396305
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.1571250501
Short name T690
Test name
Test status
Simulation time 415694222 ps
CPU time 3.08 seconds
Started Mar 19 02:18:47 PM PDT 24
Finished Mar 19 02:18:50 PM PDT 24
Peak memory 219132 kb
Host smart-ae18f9fc-edac-4ba9-9bdb-9f025bbce4f9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1571250501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dir
ect.1571250501
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.2653673650
Short name T154
Test name
Test status
Simulation time 50614935 ps
CPU time 0.87 seconds
Started Mar 19 02:18:51 PM PDT 24
Finished Mar 19 02:18:52 PM PDT 24
Peak memory 205644 kb
Host smart-3d04b858-5abf-466e-a232-6a6da28ac37e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653673650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stre
ss_all.2653673650
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.600927066
Short name T14
Test name
Test status
Simulation time 4129837594 ps
CPU time 24.92 seconds
Started Mar 19 02:18:48 PM PDT 24
Finished Mar 19 02:19:14 PM PDT 24
Peak memory 216764 kb
Host smart-dbcfb78f-9650-469e-b8ee-98747def61a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600927066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.600927066
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.3418498769
Short name T434
Test name
Test status
Simulation time 3673562897 ps
CPU time 10.73 seconds
Started Mar 19 02:18:37 PM PDT 24
Finished Mar 19 02:18:48 PM PDT 24
Peak memory 216796 kb
Host smart-47ebb8ad-8541-404f-b4b9-d92b286dfb75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3418498769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.3418498769
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.3835702856
Short name T451
Test name
Test status
Simulation time 18588377 ps
CPU time 0.92 seconds
Started Mar 19 02:18:47 PM PDT 24
Finished Mar 19 02:18:48 PM PDT 24
Peak memory 206588 kb
Host smart-2db74352-b059-4581-9ba4-83a9216ab3f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3835702856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.3835702856
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.845547188
Short name T336
Test name
Test status
Simulation time 41089494 ps
CPU time 0.74 seconds
Started Mar 19 02:18:48 PM PDT 24
Finished Mar 19 02:18:49 PM PDT 24
Peak memory 205896 kb
Host smart-2f8229ab-bb23-4aab-8ab3-306b5d66c3e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=845547188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.845547188
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.1835276368
Short name T354
Test name
Test status
Simulation time 2575792728 ps
CPU time 9.49 seconds
Started Mar 19 02:18:48 PM PDT 24
Finished Mar 19 02:18:58 PM PDT 24
Peak memory 231316 kb
Host smart-33a89734-5e84-4b66-809d-edb5aa8cf2cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835276368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.1835276368
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.4062706724
Short name T449
Test name
Test status
Simulation time 45330860 ps
CPU time 0.79 seconds
Started Mar 19 02:19:03 PM PDT 24
Finished Mar 19 02:19:04 PM PDT 24
Peak memory 205588 kb
Host smart-2dd5ea99-bcee-4653-b9eb-f1f134ff9d4e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062706724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.
4062706724
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.3073646465
Short name T587
Test name
Test status
Simulation time 1433179831 ps
CPU time 4.06 seconds
Started Mar 19 02:19:02 PM PDT 24
Finished Mar 19 02:19:06 PM PDT 24
Peak memory 220384 kb
Host smart-a5351fd6-caca-4e93-bee0-d99226eb24b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073646465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.3073646465
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.742981857
Short name T734
Test name
Test status
Simulation time 20786279 ps
CPU time 0.81 seconds
Started Mar 19 02:18:47 PM PDT 24
Finished Mar 19 02:18:48 PM PDT 24
Peak memory 205708 kb
Host smart-25885958-8e38-42a3-bd29-d23dda423df4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=742981857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.742981857
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.1883109336
Short name T685
Test name
Test status
Simulation time 6951553984 ps
CPU time 49.89 seconds
Started Mar 19 02:18:59 PM PDT 24
Finished Mar 19 02:19:49 PM PDT 24
Peak memory 235332 kb
Host smart-94d8c140-dcb6-44a1-b3c5-1488b0638347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1883109336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.1883109336
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.1342090159
Short name T199
Test name
Test status
Simulation time 328026935357 ps
CPU time 166.47 seconds
Started Mar 19 02:19:01 PM PDT 24
Finished Mar 19 02:21:47 PM PDT 24
Peak memory 224188 kb
Host smart-91e999d7-374b-4f35-97bf-a5ead0ef5b9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342090159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.1342090159
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.2079146267
Short name T600
Test name
Test status
Simulation time 19671041031 ps
CPU time 123.43 seconds
Started Mar 19 02:19:01 PM PDT 24
Finished Mar 19 02:21:04 PM PDT 24
Peak memory 234772 kb
Host smart-2f34d392-8880-445e-bd96-2967ffae9c50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2079146267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idl
e.2079146267
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.2130885251
Short name T359
Test name
Test status
Simulation time 35704347636 ps
CPU time 16.59 seconds
Started Mar 19 02:19:00 PM PDT 24
Finished Mar 19 02:19:17 PM PDT 24
Peak memory 224976 kb
Host smart-334285b4-053a-4101-a897-d23db9c3674e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130885251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.2130885251
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_intercept.1589811105
Short name T669
Test name
Test status
Simulation time 2269671887 ps
CPU time 5.36 seconds
Started Mar 19 02:19:00 PM PDT 24
Finished Mar 19 02:19:06 PM PDT 24
Peak memory 219492 kb
Host smart-052062f5-f963-4e83-8882-0a9ab569d7c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589811105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.1589811105
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.2887128481
Short name T599
Test name
Test status
Simulation time 9684590123 ps
CPU time 18.08 seconds
Started Mar 19 02:19:01 PM PDT 24
Finished Mar 19 02:19:20 PM PDT 24
Peak memory 250104 kb
Host smart-cb0849e2-bfde-4b19-9ab9-5976f5764e1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2887128481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.2887128481
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.2034544688
Short name T778
Test name
Test status
Simulation time 4200146999 ps
CPU time 21.43 seconds
Started Mar 19 02:18:49 PM PDT 24
Finished Mar 19 02:19:11 PM PDT 24
Peak memory 245760 kb
Host smart-fbe01ff6-a91d-4fe0-860b-b37278eeda9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2034544688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swa
p.2034544688
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.2568818780
Short name T904
Test name
Test status
Simulation time 275623168 ps
CPU time 3.14 seconds
Started Mar 19 02:18:50 PM PDT 24
Finished Mar 19 02:18:53 PM PDT 24
Peak memory 219384 kb
Host smart-dd5aeceb-7606-40ba-8c78-53b34e6031cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2568818780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.2568818780
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.1098754669
Short name T350
Test name
Test status
Simulation time 74357018 ps
CPU time 3.3 seconds
Started Mar 19 02:19:01 PM PDT 24
Finished Mar 19 02:19:04 PM PDT 24
Peak memory 219640 kb
Host smart-68d1b56c-8601-46df-8053-13c2b6c35001
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1098754669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dir
ect.1098754669
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.1126358116
Short name T549
Test name
Test status
Simulation time 5392987481 ps
CPU time 22.72 seconds
Started Mar 19 02:18:48 PM PDT 24
Finished Mar 19 02:19:11 PM PDT 24
Peak memory 219748 kb
Host smart-7e89437e-bd91-4f20-b86b-c10e770c2d84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1126358116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.1126358116
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.3388926635
Short name T566
Test name
Test status
Simulation time 1124628279 ps
CPU time 1.96 seconds
Started Mar 19 02:18:50 PM PDT 24
Finished Mar 19 02:18:52 PM PDT 24
Peak memory 207084 kb
Host smart-31d429ac-f71f-48ab-b98e-5bfad90fd7dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3388926635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.3388926635
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.2355043351
Short name T962
Test name
Test status
Simulation time 816989628 ps
CPU time 5.64 seconds
Started Mar 19 02:18:48 PM PDT 24
Finished Mar 19 02:18:54 PM PDT 24
Peak memory 216716 kb
Host smart-898bb42b-2677-4180-be6a-fec7c2049863
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355043351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.2355043351
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.713213097
Short name T292
Test name
Test status
Simulation time 1222756423 ps
CPU time 1.18 seconds
Started Mar 19 02:18:51 PM PDT 24
Finished Mar 19 02:18:52 PM PDT 24
Peak memory 206976 kb
Host smart-c6186723-41f9-4a9d-9489-f843c4bbe416
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=713213097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.713213097
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.2932897846
Short name T545
Test name
Test status
Simulation time 14123505448 ps
CPU time 30.84 seconds
Started Mar 19 02:19:00 PM PDT 24
Finished Mar 19 02:19:31 PM PDT 24
Peak memory 247276 kb
Host smart-875fc1d9-d2e0-4cbf-8f82-8d7ea2b875f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2932897846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.2932897846
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.3806868567
Short name T656
Test name
Test status
Simulation time 72678585 ps
CPU time 0.7 seconds
Started Mar 19 02:19:11 PM PDT 24
Finished Mar 19 02:19:12 PM PDT 24
Peak memory 205004 kb
Host smart-a8b48f80-b082-4929-801b-14cb2134b10f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806868567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.
3806868567
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.882906674
Short name T711
Test name
Test status
Simulation time 206684724 ps
CPU time 2.58 seconds
Started Mar 19 02:19:11 PM PDT 24
Finished Mar 19 02:19:14 PM PDT 24
Peak memory 218876 kb
Host smart-08be5a4d-c4ee-4023-8417-21ba1bce1189
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=882906674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.882906674
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.3693313529
Short name T537
Test name
Test status
Simulation time 16842323 ps
CPU time 0.84 seconds
Started Mar 19 02:19:02 PM PDT 24
Finished Mar 19 02:19:03 PM PDT 24
Peak memory 206720 kb
Host smart-d8348e7c-6f07-44f3-81ec-70bace102339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3693313529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.3693313529
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.1121204351
Short name T820
Test name
Test status
Simulation time 34295061643 ps
CPU time 155.26 seconds
Started Mar 19 02:19:10 PM PDT 24
Finished Mar 19 02:21:45 PM PDT 24
Peak memory 254708 kb
Host smart-00a7df17-c3d3-466a-bd6a-873cb12cbeef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1121204351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.1121204351
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.1932784188
Short name T260
Test name
Test status
Simulation time 1006591216618 ps
CPU time 584.06 seconds
Started Mar 19 02:19:09 PM PDT 24
Finished Mar 19 02:28:54 PM PDT 24
Peak memory 269696 kb
Host smart-4507109e-cdac-41d5-b1ae-2d59b1c1fc2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1932784188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.1932784188
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.1437786301
Short name T496
Test name
Test status
Simulation time 3926239147 ps
CPU time 53.26 seconds
Started Mar 19 02:19:11 PM PDT 24
Finished Mar 19 02:20:04 PM PDT 24
Peak memory 250084 kb
Host smart-6af71049-60d7-494b-acda-d804556f3477
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1437786301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idl
e.1437786301
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.1355444883
Short name T280
Test name
Test status
Simulation time 188004537 ps
CPU time 7.96 seconds
Started Mar 19 02:19:12 PM PDT 24
Finished Mar 19 02:19:21 PM PDT 24
Peak memory 240848 kb
Host smart-85de2f42-a5c6-43f0-b137-7a080b6a1ee9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355444883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.1355444883
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_intercept.3286271912
Short name T460
Test name
Test status
Simulation time 319997310 ps
CPU time 4.76 seconds
Started Mar 19 02:19:12 PM PDT 24
Finished Mar 19 02:19:16 PM PDT 24
Peak memory 234008 kb
Host smart-ce033850-185a-4e75-add8-391d85c73708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3286271912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.3286271912
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.506678626
Short name T533
Test name
Test status
Simulation time 3486370577 ps
CPU time 11.64 seconds
Started Mar 19 02:19:10 PM PDT 24
Finished Mar 19 02:19:22 PM PDT 24
Peak memory 218820 kb
Host smart-84f393f5-ba5b-4a4d-b815-ea4fd969ad5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=506678626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.506678626
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.3948258012
Short name T38
Test name
Test status
Simulation time 3139507242 ps
CPU time 9.69 seconds
Started Mar 19 02:19:02 PM PDT 24
Finished Mar 19 02:19:12 PM PDT 24
Peak memory 225068 kb
Host smart-a6139f16-a03b-4324-8475-5e00fd6e2704
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3948258012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swa
p.3948258012
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.693257249
Short name T660
Test name
Test status
Simulation time 5195055853 ps
CPU time 18.45 seconds
Started Mar 19 02:19:01 PM PDT 24
Finished Mar 19 02:19:20 PM PDT 24
Peak memory 234232 kb
Host smart-ef2614a2-610d-4a0b-b5e5-fe8a4291b42e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=693257249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.693257249
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.3407168999
Short name T479
Test name
Test status
Simulation time 2798001498 ps
CPU time 6.35 seconds
Started Mar 19 02:19:10 PM PDT 24
Finished Mar 19 02:19:17 PM PDT 24
Peak memory 219188 kb
Host smart-a3f0571f-135b-43da-916b-e43a326f8e9e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3407168999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dir
ect.3407168999
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.181300295
Short name T165
Test name
Test status
Simulation time 17321401816 ps
CPU time 170.88 seconds
Started Mar 19 02:19:10 PM PDT 24
Finished Mar 19 02:22:01 PM PDT 24
Peak memory 266044 kb
Host smart-4af27e4c-a8bf-4b42-b513-cd3e2b53c3b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181300295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stres
s_all.181300295
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.150002432
Short name T326
Test name
Test status
Simulation time 2931170822 ps
CPU time 16.51 seconds
Started Mar 19 02:19:02 PM PDT 24
Finished Mar 19 02:19:19 PM PDT 24
Peak memory 216800 kb
Host smart-c037c4af-8b5c-4930-b567-e66c59d0c14d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=150002432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.150002432
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.2239703480
Short name T794
Test name
Test status
Simulation time 1427453132 ps
CPU time 9.16 seconds
Started Mar 19 02:19:01 PM PDT 24
Finished Mar 19 02:19:11 PM PDT 24
Peak memory 216544 kb
Host smart-d0104bc1-3189-4ecf-b6fb-d75777e5c1c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239703480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.2239703480
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.658020728
Short name T341
Test name
Test status
Simulation time 659737240 ps
CPU time 3.56 seconds
Started Mar 19 02:19:03 PM PDT 24
Finished Mar 19 02:19:07 PM PDT 24
Peak memory 218292 kb
Host smart-053bee18-3eb6-4a6a-a581-ce3a8978b6bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658020728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.658020728
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.2036289090
Short name T295
Test name
Test status
Simulation time 41088016 ps
CPU time 0.86 seconds
Started Mar 19 02:19:02 PM PDT 24
Finished Mar 19 02:19:03 PM PDT 24
Peak memory 205840 kb
Host smart-7acd296e-b2d2-4deb-8ff8-332b804f81db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2036289090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.2036289090
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.3550761072
Short name T358
Test name
Test status
Simulation time 81028490358 ps
CPU time 47.67 seconds
Started Mar 19 02:19:10 PM PDT 24
Finished Mar 19 02:19:58 PM PDT 24
Peak memory 235096 kb
Host smart-bf3abc7b-b7b6-412f-a3e1-b3a689a102c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3550761072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.3550761072
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.1665835634
Short name T766
Test name
Test status
Simulation time 34793593 ps
CPU time 0.67 seconds
Started Mar 19 02:19:29 PM PDT 24
Finished Mar 19 02:19:30 PM PDT 24
Peak memory 204936 kb
Host smart-01b83de6-7c39-4cc3-97eb-b79befe73470
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665835634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.
1665835634
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.1546682189
Short name T230
Test name
Test status
Simulation time 2063250859 ps
CPU time 6.59 seconds
Started Mar 19 02:19:23 PM PDT 24
Finished Mar 19 02:19:30 PM PDT 24
Peak memory 234160 kb
Host smart-dc301459-6486-49f6-87fe-67b35d5917a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1546682189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.1546682189
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.3494146812
Short name T464
Test name
Test status
Simulation time 29944615 ps
CPU time 0.77 seconds
Started Mar 19 02:19:14 PM PDT 24
Finished Mar 19 02:19:15 PM PDT 24
Peak memory 205716 kb
Host smart-7fce0e0f-c5cf-4612-84dc-a2f125333e92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3494146812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.3494146812
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.3109947521
Short name T681
Test name
Test status
Simulation time 29714080638 ps
CPU time 78.72 seconds
Started Mar 19 02:19:24 PM PDT 24
Finished Mar 19 02:20:43 PM PDT 24
Peak memory 255708 kb
Host smart-8cbc9984-6e01-4302-9469-83047d638716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3109947521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.3109947521
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.365497172
Short name T763
Test name
Test status
Simulation time 35507591118 ps
CPU time 28.96 seconds
Started Mar 19 02:19:21 PM PDT 24
Finished Mar 19 02:19:50 PM PDT 24
Peak memory 238448 kb
Host smart-779ca1d0-740f-4d23-b86e-ec1f59ba2a1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365497172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.365497172
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.38616161
Short name T48
Test name
Test status
Simulation time 145737552167 ps
CPU time 505.08 seconds
Started Mar 19 02:19:22 PM PDT 24
Finished Mar 19 02:27:47 PM PDT 24
Peak memory 254680 kb
Host smart-ca9cf211-2146-470f-a6c7-21d39410645d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38616161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idle.38616161
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.770307599
Short name T853
Test name
Test status
Simulation time 2091519940 ps
CPU time 19.68 seconds
Started Mar 19 02:19:21 PM PDT 24
Finished Mar 19 02:19:41 PM PDT 24
Peak memory 243348 kb
Host smart-6d6a502d-8603-4e6c-83d9-c1172d6e5d07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=770307599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.770307599
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_intercept.157958467
Short name T501
Test name
Test status
Simulation time 968901306 ps
CPU time 6.95 seconds
Started Mar 19 02:19:11 PM PDT 24
Finished Mar 19 02:19:18 PM PDT 24
Peak memory 235572 kb
Host smart-d83427d6-987c-4375-9893-188fe45f93cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157958467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.157958467
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.1425545665
Short name T882
Test name
Test status
Simulation time 5939760621 ps
CPU time 6.22 seconds
Started Mar 19 02:19:11 PM PDT 24
Finished Mar 19 02:19:17 PM PDT 24
Peak memory 219056 kb
Host smart-dd3ab753-0d9e-49c5-bc72-872026041bfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425545665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.1425545665
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.667490274
Short name T546
Test name
Test status
Simulation time 10168007152 ps
CPU time 29.91 seconds
Started Mar 19 02:19:10 PM PDT 24
Finished Mar 19 02:19:41 PM PDT 24
Peak memory 233316 kb
Host smart-4bb9a276-201e-425a-8685-069dcba4f2a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=667490274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swap
.667490274
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.4185627605
Short name T977
Test name
Test status
Simulation time 773116463 ps
CPU time 5.19 seconds
Started Mar 19 02:19:11 PM PDT 24
Finished Mar 19 02:19:16 PM PDT 24
Peak memory 233560 kb
Host smart-e2a4c542-acce-4b1b-81ab-fd59b80893c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4185627605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.4185627605
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.57172290
Short name T598
Test name
Test status
Simulation time 1021317004 ps
CPU time 5.97 seconds
Started Mar 19 02:19:21 PM PDT 24
Finished Mar 19 02:19:27 PM PDT 24
Peak memory 222824 kb
Host smart-62ec6845-769b-4638-ad48-3883f5310d2d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=57172290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_direc
t.57172290
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.1679054483
Short name T666
Test name
Test status
Simulation time 1054430770 ps
CPU time 14.82 seconds
Started Mar 19 02:19:22 PM PDT 24
Finished Mar 19 02:19:37 PM PDT 24
Peak memory 224592 kb
Host smart-f106c2dd-28a8-4bb7-9820-54c9aecd4702
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679054483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stre
ss_all.1679054483
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.1451567675
Short name T396
Test name
Test status
Simulation time 18514082272 ps
CPU time 32.7 seconds
Started Mar 19 02:19:12 PM PDT 24
Finished Mar 19 02:19:45 PM PDT 24
Peak memory 216868 kb
Host smart-661d88fb-4260-4bf2-a466-ad6813a0b7e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1451567675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.1451567675
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.3594546684
Short name T470
Test name
Test status
Simulation time 12892893750 ps
CPU time 9.64 seconds
Started Mar 19 02:19:14 PM PDT 24
Finished Mar 19 02:19:24 PM PDT 24
Peak memory 216676 kb
Host smart-afdf409a-00e1-4651-a365-5dd70dc2760e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3594546684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.3594546684
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.2767888875
Short name T814
Test name
Test status
Simulation time 41300196 ps
CPU time 1.29 seconds
Started Mar 19 02:19:11 PM PDT 24
Finished Mar 19 02:19:12 PM PDT 24
Peak memory 216652 kb
Host smart-cb730482-4b6a-43c6-b0b7-0af66032fa7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2767888875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.2767888875
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.2882187884
Short name T982
Test name
Test status
Simulation time 68114500 ps
CPU time 0.8 seconds
Started Mar 19 02:19:11 PM PDT 24
Finished Mar 19 02:19:12 PM PDT 24
Peak memory 205932 kb
Host smart-db45d91e-0963-4bb9-a516-43c82f5f694b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882187884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.2882187884
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.4257251243
Short name T200
Test name
Test status
Simulation time 4821322755 ps
CPU time 7.99 seconds
Started Mar 19 02:19:10 PM PDT 24
Finished Mar 19 02:19:19 PM PDT 24
Peak memory 238916 kb
Host smart-39eb001d-339f-45c8-b751-c24c5d3cd208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4257251243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.4257251243
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.1647401761
Short name T67
Test name
Test status
Simulation time 15008313 ps
CPU time 0.71 seconds
Started Mar 19 02:14:40 PM PDT 24
Finished Mar 19 02:14:40 PM PDT 24
Peak memory 205668 kb
Host smart-096f9276-4303-492d-91e1-70ab69e14a2e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647401761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.1
647401761
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.3803174433
Short name T523
Test name
Test status
Simulation time 941193399 ps
CPU time 3.16 seconds
Started Mar 19 02:14:29 PM PDT 24
Finished Mar 19 02:14:33 PM PDT 24
Peak memory 234116 kb
Host smart-236f1b48-80a7-4668-8843-ee113403d149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3803174433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.3803174433
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.2498233327
Short name T289
Test name
Test status
Simulation time 27108858 ps
CPU time 0.83 seconds
Started Mar 19 02:14:19 PM PDT 24
Finished Mar 19 02:14:19 PM PDT 24
Peak memory 206784 kb
Host smart-6c9fb950-72a6-4a84-a768-6bd567da0e0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2498233327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.2498233327
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.868728859
Short name T875
Test name
Test status
Simulation time 10186524905 ps
CPU time 96.6 seconds
Started Mar 19 02:14:29 PM PDT 24
Finished Mar 19 02:16:06 PM PDT 24
Peak memory 254268 kb
Host smart-a414b800-3eed-47a2-adb6-a71964fa8ec8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868728859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.868728859
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.738655908
Short name T379
Test name
Test status
Simulation time 23532996786 ps
CPU time 165.13 seconds
Started Mar 19 02:14:31 PM PDT 24
Finished Mar 19 02:17:16 PM PDT 24
Peak memory 257964 kb
Host smart-5652847d-3f54-463e-aa41-df6660c0c2a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=738655908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.738655908
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.1648953675
Short name T214
Test name
Test status
Simulation time 37652839963 ps
CPU time 232.73 seconds
Started Mar 19 02:14:30 PM PDT 24
Finished Mar 19 02:18:23 PM PDT 24
Peak memory 253320 kb
Host smart-1659ca0b-2863-4c2b-a117-a4bf5c9fb129
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1648953675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle
.1648953675
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.1240534401
Short name T368
Test name
Test status
Simulation time 3308422296 ps
CPU time 20.03 seconds
Started Mar 19 02:14:30 PM PDT 24
Finished Mar 19 02:14:51 PM PDT 24
Peak memory 233216 kb
Host smart-622b074d-128d-491b-9092-acc2bd101e7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1240534401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.1240534401
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_intercept.2442619433
Short name T925
Test name
Test status
Simulation time 1972705141 ps
CPU time 6.98 seconds
Started Mar 19 02:14:31 PM PDT 24
Finished Mar 19 02:14:38 PM PDT 24
Peak memory 234096 kb
Host smart-14121c52-8a98-405b-8321-7363ade9d9bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2442619433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.2442619433
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.1200703008
Short name T390
Test name
Test status
Simulation time 3236401353 ps
CPU time 9.45 seconds
Started Mar 19 02:14:30 PM PDT 24
Finished Mar 19 02:14:39 PM PDT 24
Peak memory 219860 kb
Host smart-0f282c9c-3ab6-4e1a-821b-ec81f9463cb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1200703008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.1200703008
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_mem_parity.2678124592
Short name T467
Test name
Test status
Simulation time 18618258 ps
CPU time 1.06 seconds
Started Mar 19 02:14:20 PM PDT 24
Finished Mar 19 02:14:21 PM PDT 24
Peak memory 217080 kb
Host smart-24036705-0b7d-45e9-b1b7-19c41f7fe8fd
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678124592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 3.spi_device_mem_parity.2678124592
Directory /workspace/3.spi_device_mem_parity/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.3109852407
Short name T644
Test name
Test status
Simulation time 3229841111 ps
CPU time 12.37 seconds
Started Mar 19 02:14:29 PM PDT 24
Finished Mar 19 02:14:42 PM PDT 24
Peak memory 236016 kb
Host smart-24fa9784-57ee-4352-b6fd-05e5dd40af54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3109852407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap
.3109852407
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.2032542566
Short name T866
Test name
Test status
Simulation time 7950643171 ps
CPU time 20.15 seconds
Started Mar 19 02:14:30 PM PDT 24
Finished Mar 19 02:14:50 PM PDT 24
Peak memory 225060 kb
Host smart-08f2e93b-654f-4904-94e5-b6e221647e52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032542566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.2032542566
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_ram_cfg.2558542679
Short name T929
Test name
Test status
Simulation time 18454820 ps
CPU time 0.77 seconds
Started Mar 19 02:14:19 PM PDT 24
Finished Mar 19 02:14:20 PM PDT 24
Peak memory 216504 kb
Host smart-a8d35aad-98d2-471f-a28b-cb145aa82c4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558542679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_ram_cfg.2558542679
Directory /workspace/3.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.1657486527
Short name T138
Test name
Test status
Simulation time 767933408 ps
CPU time 4.74 seconds
Started Mar 19 02:14:29 PM PDT 24
Finished Mar 19 02:14:34 PM PDT 24
Peak memory 222632 kb
Host smart-5d2d2446-902c-4519-b83e-ea509b14e652
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1657486527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_dire
ct.1657486527
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.3781715794
Short name T77
Test name
Test status
Simulation time 33264982 ps
CPU time 0.97 seconds
Started Mar 19 02:14:40 PM PDT 24
Finished Mar 19 02:14:41 PM PDT 24
Peak memory 235124 kb
Host smart-8c39ad36-fd35-46d3-ac5e-ffa626f85477
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781715794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.3781715794
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.1112910765
Short name T808
Test name
Test status
Simulation time 25833692696 ps
CPU time 36.92 seconds
Started Mar 19 02:14:30 PM PDT 24
Finished Mar 19 02:15:07 PM PDT 24
Peak memory 216712 kb
Host smart-a549882b-f6f9-4167-bf30-fd6c62b56800
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1112910765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.1112910765
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.767686232
Short name T300
Test name
Test status
Simulation time 17483384106 ps
CPU time 8.38 seconds
Started Mar 19 02:14:20 PM PDT 24
Finished Mar 19 02:14:29 PM PDT 24
Peak memory 216736 kb
Host smart-1fe2e799-c4ea-4c12-8e5a-178984f1167f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767686232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.767686232
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.902504428
Short name T972
Test name
Test status
Simulation time 574875567 ps
CPU time 3.12 seconds
Started Mar 19 02:14:31 PM PDT 24
Finished Mar 19 02:14:34 PM PDT 24
Peak memory 216628 kb
Host smart-14bcbe6c-10b8-4568-aa3f-9ad4905ae7af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902504428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.902504428
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.3026459077
Short name T641
Test name
Test status
Simulation time 36397128 ps
CPU time 0.79 seconds
Started Mar 19 02:14:30 PM PDT 24
Finished Mar 19 02:14:31 PM PDT 24
Peak memory 205900 kb
Host smart-82310644-3fe9-4587-af7e-61f289500feb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026459077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.3026459077
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.3971728566
Short name T934
Test name
Test status
Simulation time 353902920 ps
CPU time 4.28 seconds
Started Mar 19 02:14:31 PM PDT 24
Finished Mar 19 02:14:36 PM PDT 24
Peak memory 235716 kb
Host smart-127c50cd-7acb-4ebb-9ff0-4f09e0eb6d22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3971728566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.3971728566
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.103171833
Short name T499
Test name
Test status
Simulation time 74691282 ps
CPU time 0.77 seconds
Started Mar 19 02:19:24 PM PDT 24
Finished Mar 19 02:19:25 PM PDT 24
Peak memory 205084 kb
Host smart-9b7c4b57-ca2a-4feb-b485-121b790a54b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103171833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.103171833
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.1430583647
Short name T477
Test name
Test status
Simulation time 591791271 ps
CPU time 2.53 seconds
Started Mar 19 02:19:22 PM PDT 24
Finished Mar 19 02:19:24 PM PDT 24
Peak memory 218192 kb
Host smart-3f0b4da9-9327-4897-a667-7686a7447e9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1430583647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.1430583647
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.130038626
Short name T430
Test name
Test status
Simulation time 13571682 ps
CPU time 0.74 seconds
Started Mar 19 02:19:21 PM PDT 24
Finished Mar 19 02:19:22 PM PDT 24
Peak memory 205724 kb
Host smart-0bfbfd83-30c9-44f8-97e8-1d1f0bc0653d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=130038626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.130038626
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.4068162695
Short name T365
Test name
Test status
Simulation time 12014689250 ps
CPU time 54.34 seconds
Started Mar 19 02:19:23 PM PDT 24
Finished Mar 19 02:20:17 PM PDT 24
Peak memory 262724 kb
Host smart-ef7c1db5-8773-4d0b-ae0d-c692d7b1a330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4068162695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.4068162695
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.2476297466
Short name T812
Test name
Test status
Simulation time 16178772964 ps
CPU time 26.49 seconds
Started Mar 19 02:19:22 PM PDT 24
Finished Mar 19 02:19:49 PM PDT 24
Peak memory 234456 kb
Host smart-228c2466-ea0b-453d-9486-eee7baeedaf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476297466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.2476297466
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.1829275754
Short name T255
Test name
Test status
Simulation time 25971328317 ps
CPU time 113.42 seconds
Started Mar 19 02:19:29 PM PDT 24
Finished Mar 19 02:21:23 PM PDT 24
Peak memory 262700 kb
Host smart-cdb4c406-9d3c-48eb-b1b6-6a648e98342d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1829275754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idl
e.1829275754
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.3545477563
Short name T432
Test name
Test status
Simulation time 16089967181 ps
CPU time 27.3 seconds
Started Mar 19 02:19:21 PM PDT 24
Finished Mar 19 02:19:49 PM PDT 24
Peak memory 240996 kb
Host smart-8912dd03-0c2e-470e-9894-880bd059a463
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3545477563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.3545477563
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_intercept.1380501166
Short name T474
Test name
Test status
Simulation time 5144724882 ps
CPU time 6.09 seconds
Started Mar 19 02:19:22 PM PDT 24
Finished Mar 19 02:19:28 PM PDT 24
Peak memory 224980 kb
Host smart-c58b56a4-3dbb-4d6d-8c96-ef5498d76f2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380501166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.1380501166
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.3038387022
Short name T440
Test name
Test status
Simulation time 10551831564 ps
CPU time 11.87 seconds
Started Mar 19 02:19:24 PM PDT 24
Finished Mar 19 02:19:37 PM PDT 24
Peak memory 235824 kb
Host smart-00b6d066-e823-4e4a-8322-a490b7619244
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3038387022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.3038387022
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.2300307737
Short name T857
Test name
Test status
Simulation time 3317163980 ps
CPU time 6.99 seconds
Started Mar 19 02:19:29 PM PDT 24
Finished Mar 19 02:19:37 PM PDT 24
Peak memory 239012 kb
Host smart-a6ab75e9-6ca9-49d2-a1b4-1fd0d1c189e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300307737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swa
p.2300307737
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.504037995
Short name T87
Test name
Test status
Simulation time 1558171887 ps
CPU time 6.65 seconds
Started Mar 19 02:19:22 PM PDT 24
Finished Mar 19 02:19:29 PM PDT 24
Peak memory 233984 kb
Host smart-268310a6-9a58-4ad4-82f0-d5cc931193c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=504037995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.504037995
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.3421430751
Short name T490
Test name
Test status
Simulation time 2488958766 ps
CPU time 5.16 seconds
Started Mar 19 02:19:23 PM PDT 24
Finished Mar 19 02:19:28 PM PDT 24
Peak memory 223676 kb
Host smart-b3b57d9c-5751-480e-88e9-2b03ad558f89
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3421430751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dir
ect.3421430751
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.259674843
Short name T897
Test name
Test status
Simulation time 205001168373 ps
CPU time 383.89 seconds
Started Mar 19 02:19:21 PM PDT 24
Finished Mar 19 02:25:45 PM PDT 24
Peak memory 253348 kb
Host smart-1901dcfe-bbb4-433a-89e8-569611652516
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259674843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stres
s_all.259674843
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.2458059331
Short name T679
Test name
Test status
Simulation time 203882336 ps
CPU time 2.35 seconds
Started Mar 19 02:19:23 PM PDT 24
Finished Mar 19 02:19:26 PM PDT 24
Peak memory 216652 kb
Host smart-92946a37-ad9c-47e9-b743-e9f14e8d95fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2458059331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.2458059331
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.2557733386
Short name T608
Test name
Test status
Simulation time 9795194811 ps
CPU time 32.92 seconds
Started Mar 19 02:19:20 PM PDT 24
Finished Mar 19 02:19:53 PM PDT 24
Peak memory 216684 kb
Host smart-84e1e9b4-d6de-40e8-870c-688608399d0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2557733386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.2557733386
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.933082213
Short name T175
Test name
Test status
Simulation time 330909532 ps
CPU time 1.74 seconds
Started Mar 19 02:19:21 PM PDT 24
Finished Mar 19 02:19:23 PM PDT 24
Peak memory 216592 kb
Host smart-96d43f65-22ad-4b8e-ac98-26af383d0243
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=933082213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.933082213
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.3389912148
Short name T911
Test name
Test status
Simulation time 372928277 ps
CPU time 1.04 seconds
Started Mar 19 02:19:24 PM PDT 24
Finished Mar 19 02:19:26 PM PDT 24
Peak memory 205908 kb
Host smart-14d5a3e6-8e74-4716-8484-5947a5b20f57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3389912148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.3389912148
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.2785042272
Short name T732
Test name
Test status
Simulation time 888081045 ps
CPU time 7.41 seconds
Started Mar 19 02:19:21 PM PDT 24
Finished Mar 19 02:19:28 PM PDT 24
Peak memory 230772 kb
Host smart-b685de9e-84f2-4867-a003-8b19bcf95fab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2785042272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.2785042272
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.3476861888
Short name T476
Test name
Test status
Simulation time 12858798 ps
CPU time 0.7 seconds
Started Mar 19 02:19:33 PM PDT 24
Finished Mar 19 02:19:34 PM PDT 24
Peak memory 205592 kb
Host smart-b701349b-a4eb-4ee8-8d74-4466ec606756
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476861888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.
3476861888
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.2721881444
Short name T725
Test name
Test status
Simulation time 396647311 ps
CPU time 4.97 seconds
Started Mar 19 02:19:31 PM PDT 24
Finished Mar 19 02:19:36 PM PDT 24
Peak memory 233904 kb
Host smart-be4f9bbf-23f5-49e2-8e71-90107194eb1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2721881444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.2721881444
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.951129702
Short name T863
Test name
Test status
Simulation time 68928282 ps
CPU time 0.82 seconds
Started Mar 19 02:19:21 PM PDT 24
Finished Mar 19 02:19:22 PM PDT 24
Peak memory 206692 kb
Host smart-ba3f6ccc-6be7-4c82-9ba1-9d7aa69a4355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951129702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.951129702
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.3654068826
Short name T867
Test name
Test status
Simulation time 1653703913 ps
CPU time 26.65 seconds
Started Mar 19 02:19:32 PM PDT 24
Finished Mar 19 02:19:59 PM PDT 24
Peak memory 249500 kb
Host smart-ec431f4c-c604-4f30-96bb-019fe68eb827
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3654068826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.3654068826
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.275185680
Short name T940
Test name
Test status
Simulation time 5125735724 ps
CPU time 55.33 seconds
Started Mar 19 02:19:47 PM PDT 24
Finished Mar 19 02:20:43 PM PDT 24
Peak memory 266032 kb
Host smart-3be83ca9-5f46-4d49-952e-7edbc0959e50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275185680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.275185680
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.189774475
Short name T272
Test name
Test status
Simulation time 31945057516 ps
CPU time 189.41 seconds
Started Mar 19 02:19:33 PM PDT 24
Finished Mar 19 02:22:43 PM PDT 24
Peak memory 250816 kb
Host smart-c6ae3738-64fc-49e9-b301-023817dacc1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=189774475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idle
.189774475
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.285008761
Short name T865
Test name
Test status
Simulation time 14955917457 ps
CPU time 18.96 seconds
Started Mar 19 02:19:32 PM PDT 24
Finished Mar 19 02:19:52 PM PDT 24
Peak memory 247856 kb
Host smart-a47daf25-9c73-4002-8250-0c7882e31ac6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=285008761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.285008761
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_intercept.2020815801
Short name T938
Test name
Test status
Simulation time 71534747 ps
CPU time 2.83 seconds
Started Mar 19 02:19:21 PM PDT 24
Finished Mar 19 02:19:24 PM PDT 24
Peak memory 234284 kb
Host smart-50b1eb27-6299-4c75-a95f-22e05cfca8fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2020815801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.2020815801
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.912860771
Short name T489
Test name
Test status
Simulation time 1342299169 ps
CPU time 7.5 seconds
Started Mar 19 02:19:23 PM PDT 24
Finished Mar 19 02:19:30 PM PDT 24
Peak memory 218948 kb
Host smart-07aed7b8-4dde-4478-a073-62ae384f0af8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912860771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.912860771
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.4140099660
Short name T986
Test name
Test status
Simulation time 4335926070 ps
CPU time 14.35 seconds
Started Mar 19 02:19:23 PM PDT 24
Finished Mar 19 02:19:37 PM PDT 24
Peak memory 234060 kb
Host smart-24a3b001-7f7f-4f99-b4aa-4e0f54ac1610
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4140099660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swa
p.4140099660
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.3643496415
Short name T98
Test name
Test status
Simulation time 988423051 ps
CPU time 6.27 seconds
Started Mar 19 02:19:22 PM PDT 24
Finished Mar 19 02:19:28 PM PDT 24
Peak memory 221976 kb
Host smart-becb3208-359d-4a25-b4e3-3c10a77f4546
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3643496415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.3643496415
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.3683321096
Short name T667
Test name
Test status
Simulation time 2429885593 ps
CPU time 6.11 seconds
Started Mar 19 02:19:33 PM PDT 24
Finished Mar 19 02:19:40 PM PDT 24
Peak memory 222820 kb
Host smart-80f010e8-25a5-4f7f-b765-a2554b07017a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3683321096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dir
ect.3683321096
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.2138862927
Short name T933
Test name
Test status
Simulation time 794456450 ps
CPU time 4.72 seconds
Started Mar 19 02:19:25 PM PDT 24
Finished Mar 19 02:19:30 PM PDT 24
Peak memory 216760 kb
Host smart-19eab784-402a-4623-a21c-78cfdd774bb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138862927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.2138862927
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.221747669
Short name T957
Test name
Test status
Simulation time 15086223939 ps
CPU time 10.53 seconds
Started Mar 19 02:19:21 PM PDT 24
Finished Mar 19 02:19:32 PM PDT 24
Peak memory 216728 kb
Host smart-f006106d-463b-4a38-aa9c-2299650545b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221747669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.221747669
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.2746819799
Short name T304
Test name
Test status
Simulation time 59337283 ps
CPU time 1.39 seconds
Started Mar 19 02:19:23 PM PDT 24
Finished Mar 19 02:19:24 PM PDT 24
Peak memory 216596 kb
Host smart-7d815d91-cc79-42e5-8cda-174391ac2ebf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2746819799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.2746819799
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.389323188
Short name T321
Test name
Test status
Simulation time 31131469 ps
CPU time 0.8 seconds
Started Mar 19 02:19:21 PM PDT 24
Finished Mar 19 02:19:22 PM PDT 24
Peak memory 205880 kb
Host smart-044c13ec-e658-4e11-bae2-d0cf46ad5590
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=389323188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.389323188
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.3678424636
Short name T202
Test name
Test status
Simulation time 1011270084 ps
CPU time 9.45 seconds
Started Mar 19 02:19:31 PM PDT 24
Finished Mar 19 02:19:41 PM PDT 24
Peak memory 219044 kb
Host smart-d44d5569-46c9-45bb-ba98-c88976001cb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3678424636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.3678424636
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.1399346423
Short name T586
Test name
Test status
Simulation time 17174288 ps
CPU time 0.75 seconds
Started Mar 19 02:19:41 PM PDT 24
Finished Mar 19 02:19:42 PM PDT 24
Peak memory 205640 kb
Host smart-ec08f882-ca48-46c6-8a13-7a3a1b406677
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399346423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.
1399346423
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.3372557575
Short name T373
Test name
Test status
Simulation time 100196171 ps
CPU time 3.28 seconds
Started Mar 19 02:19:34 PM PDT 24
Finished Mar 19 02:19:37 PM PDT 24
Peak memory 234668 kb
Host smart-0b4bddb9-9b1c-4160-9424-223e31059e29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372557575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.3372557575
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.2256640661
Short name T901
Test name
Test status
Simulation time 42200436 ps
CPU time 0.79 seconds
Started Mar 19 02:19:48 PM PDT 24
Finished Mar 19 02:19:49 PM PDT 24
Peak memory 206984 kb
Host smart-c140811d-285e-4b4d-b166-c81ffbca0fd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256640661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.2256640661
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.2242030133
Short name T46
Test name
Test status
Simulation time 493940721 ps
CPU time 4.59 seconds
Started Mar 19 02:19:33 PM PDT 24
Finished Mar 19 02:19:38 PM PDT 24
Peak memory 221072 kb
Host smart-34da7dbb-3c18-4081-ba38-6b314d14b0c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2242030133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.2242030133
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.2195590157
Short name T42
Test name
Test status
Simulation time 3589363894 ps
CPU time 41.69 seconds
Started Mar 19 02:19:43 PM PDT 24
Finished Mar 19 02:20:25 PM PDT 24
Peak memory 249716 kb
Host smart-9e6b1b83-ef03-4b99-9edd-a4b5ba6edd46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2195590157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.2195590157
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.3599040989
Short name T868
Test name
Test status
Simulation time 1689766592 ps
CPU time 11.2 seconds
Started Mar 19 02:19:41 PM PDT 24
Finished Mar 19 02:19:52 PM PDT 24
Peak memory 233104 kb
Host smart-76e88da2-9843-4f77-83fb-82d36e650138
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3599040989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.3599040989
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_intercept.371077991
Short name T937
Test name
Test status
Simulation time 1323567186 ps
CPU time 3.42 seconds
Started Mar 19 02:19:33 PM PDT 24
Finished Mar 19 02:19:37 PM PDT 24
Peak memory 218184 kb
Host smart-8c42f6d6-6dec-46bb-97db-19ba79faf541
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371077991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.371077991
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.1584335124
Short name T651
Test name
Test status
Simulation time 11564142521 ps
CPU time 31.77 seconds
Started Mar 19 02:19:32 PM PDT 24
Finished Mar 19 02:20:04 PM PDT 24
Peak memory 232456 kb
Host smart-b3118c51-6876-4735-817f-bb696b8781eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584335124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.1584335124
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.4227323373
Short name T619
Test name
Test status
Simulation time 160474454 ps
CPU time 2.69 seconds
Started Mar 19 02:19:40 PM PDT 24
Finished Mar 19 02:19:43 PM PDT 24
Peak memory 224852 kb
Host smart-d849b094-d0d0-40fd-8990-95c847475fc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4227323373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swa
p.4227323373
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.304554178
Short name T401
Test name
Test status
Simulation time 38296520181 ps
CPU time 20.82 seconds
Started Mar 19 02:19:37 PM PDT 24
Finished Mar 19 02:19:59 PM PDT 24
Peak memory 240316 kb
Host smart-f3ed10c0-18d2-46b7-bed9-3136d207c486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304554178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.304554178
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.46628728
Short name T828
Test name
Test status
Simulation time 467617295 ps
CPU time 3.38 seconds
Started Mar 19 02:19:46 PM PDT 24
Finished Mar 19 02:19:50 PM PDT 24
Peak memory 220184 kb
Host smart-d0e699aa-d656-423a-a5ee-8a24822d4dac
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=46628728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_direc
t.46628728
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.446359273
Short name T816
Test name
Test status
Simulation time 157108345 ps
CPU time 0.91 seconds
Started Mar 19 02:19:48 PM PDT 24
Finished Mar 19 02:19:49 PM PDT 24
Peak memory 206996 kb
Host smart-b142fd57-5420-4831-a509-f973bcd12e9b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446359273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stres
s_all.446359273
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.2156189346
Short name T950
Test name
Test status
Simulation time 2651353714 ps
CPU time 40.39 seconds
Started Mar 19 02:19:32 PM PDT 24
Finished Mar 19 02:20:12 PM PDT 24
Peak memory 216796 kb
Host smart-1900f0aa-e1a5-49d4-9cfd-fae54af48e6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2156189346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.2156189346
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.375723304
Short name T724
Test name
Test status
Simulation time 81028616 ps
CPU time 1.06 seconds
Started Mar 19 02:19:32 PM PDT 24
Finished Mar 19 02:19:33 PM PDT 24
Peak memory 205956 kb
Host smart-d0d38955-0d13-4643-b4ab-4d6dc872cd98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375723304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.375723304
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.3982725278
Short name T315
Test name
Test status
Simulation time 90897497 ps
CPU time 1.57 seconds
Started Mar 19 02:19:33 PM PDT 24
Finished Mar 19 02:19:34 PM PDT 24
Peak memory 208440 kb
Host smart-7e73a57e-c9f6-4fcb-a993-4a8009dd98f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982725278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.3982725278
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.3211625559
Short name T741
Test name
Test status
Simulation time 108566981 ps
CPU time 1.09 seconds
Started Mar 19 02:19:32 PM PDT 24
Finished Mar 19 02:19:33 PM PDT 24
Peak memory 206932 kb
Host smart-70fedf58-7589-4ff7-9460-faf1393eb093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211625559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.3211625559
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.2386448143
Short name T342
Test name
Test status
Simulation time 419398327 ps
CPU time 6.61 seconds
Started Mar 19 02:19:40 PM PDT 24
Finished Mar 19 02:19:47 PM PDT 24
Peak memory 236932 kb
Host smart-ef1cddc2-6cde-44b9-9c2f-1c27ae230eca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386448143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.2386448143
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.525537120
Short name T345
Test name
Test status
Simulation time 37559277 ps
CPU time 0.72 seconds
Started Mar 19 02:19:47 PM PDT 24
Finished Mar 19 02:19:48 PM PDT 24
Peak memory 205976 kb
Host smart-ad8a0b25-ffcd-43ab-aa6f-a60bceccb8fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525537120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.525537120
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.414794962
Short name T846
Test name
Test status
Simulation time 1994520638 ps
CPU time 5.79 seconds
Started Mar 19 02:19:42 PM PDT 24
Finished Mar 19 02:19:48 PM PDT 24
Peak memory 224920 kb
Host smart-564c2d43-4276-49f2-b014-eef5198f34a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=414794962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.414794962
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.1916756826
Short name T906
Test name
Test status
Simulation time 73157088 ps
CPU time 0.76 seconds
Started Mar 19 02:19:46 PM PDT 24
Finished Mar 19 02:19:47 PM PDT 24
Peak memory 205648 kb
Host smart-b9e9e4c4-dc3c-4aea-bdf5-f190017b84a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1916756826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.1916756826
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.1708171000
Short name T895
Test name
Test status
Simulation time 50263951410 ps
CPU time 92.31 seconds
Started Mar 19 02:19:47 PM PDT 24
Finished Mar 19 02:21:20 PM PDT 24
Peak memory 259892 kb
Host smart-fd80d0c6-3071-472c-85fb-f64845dd85a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1708171000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.1708171000
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.2585895220
Short name T760
Test name
Test status
Simulation time 11345108637 ps
CPU time 50.5 seconds
Started Mar 19 02:19:43 PM PDT 24
Finished Mar 19 02:20:34 PM PDT 24
Peak memory 257904 kb
Host smart-381ae8b3-6785-42d7-9325-2e7f5cec65a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2585895220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.2585895220
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.2901662982
Short name T813
Test name
Test status
Simulation time 7012349110 ps
CPU time 56.72 seconds
Started Mar 19 02:19:41 PM PDT 24
Finished Mar 19 02:20:38 PM PDT 24
Peak memory 239428 kb
Host smart-9b1feba0-9fec-4192-953e-2d99a3df4a5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2901662982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idl
e.2901662982
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.2386480892
Short name T668
Test name
Test status
Simulation time 3446943882 ps
CPU time 14.99 seconds
Started Mar 19 02:19:43 PM PDT 24
Finished Mar 19 02:19:58 PM PDT 24
Peak memory 246340 kb
Host smart-11be151d-9318-4d14-ba58-c8a8b10d5715
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386480892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.2386480892
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_intercept.1227426479
Short name T223
Test name
Test status
Simulation time 504488718 ps
CPU time 4.83 seconds
Started Mar 19 02:19:42 PM PDT 24
Finished Mar 19 02:19:48 PM PDT 24
Peak memory 220972 kb
Host smart-9754fff8-dd2f-4f29-935f-6d4cc813f7ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1227426479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.1227426479
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.2390934072
Short name T561
Test name
Test status
Simulation time 2308260613 ps
CPU time 9.19 seconds
Started Mar 19 02:19:43 PM PDT 24
Finished Mar 19 02:19:53 PM PDT 24
Peak memory 241392 kb
Host smart-3f8a09de-b587-45d6-a761-1941b5d6c4dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2390934072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.2390934072
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.3956031731
Short name T789
Test name
Test status
Simulation time 2518262126 ps
CPU time 3.39 seconds
Started Mar 19 02:19:42 PM PDT 24
Finished Mar 19 02:19:46 PM PDT 24
Peak memory 234208 kb
Host smart-8f3c58c2-ca8b-4d80-bdb0-aea8aee0c28f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3956031731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swa
p.3956031731
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.2502352983
Short name T174
Test name
Test status
Simulation time 7276101569 ps
CPU time 23.68 seconds
Started Mar 19 02:19:42 PM PDT 24
Finished Mar 19 02:20:06 PM PDT 24
Peak memory 241420 kb
Host smart-6422a8b1-6293-4dbb-a4bf-2b0c5d19a6a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2502352983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.2502352983
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.21997529
Short name T425
Test name
Test status
Simulation time 2908599598 ps
CPU time 5.99 seconds
Started Mar 19 02:19:42 PM PDT 24
Finished Mar 19 02:19:49 PM PDT 24
Peak memory 221296 kb
Host smart-06afa17f-aaf7-4f92-adbd-a68823498f96
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=21997529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_direc
t.21997529
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.1319783918
Short name T69
Test name
Test status
Simulation time 46076122 ps
CPU time 1.12 seconds
Started Mar 19 02:19:43 PM PDT 24
Finished Mar 19 02:19:45 PM PDT 24
Peak memory 207088 kb
Host smart-272bee08-81d7-4668-b6fa-49eae023bd8e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319783918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stre
ss_all.1319783918
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.436552730
Short name T675
Test name
Test status
Simulation time 8263132238 ps
CPU time 12.93 seconds
Started Mar 19 02:19:41 PM PDT 24
Finished Mar 19 02:19:54 PM PDT 24
Peak memory 216768 kb
Host smart-7e8ffa06-7ba2-443e-aeba-c87de28ac956
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436552730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.436552730
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.2854896686
Short name T731
Test name
Test status
Simulation time 5839087027 ps
CPU time 19.14 seconds
Started Mar 19 02:19:33 PM PDT 24
Finished Mar 19 02:19:53 PM PDT 24
Peak memory 216648 kb
Host smart-e8a0b666-37f0-4119-946b-0025594663d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2854896686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.2854896686
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.1937145067
Short name T311
Test name
Test status
Simulation time 35910866 ps
CPU time 0.95 seconds
Started Mar 19 02:19:45 PM PDT 24
Finished Mar 19 02:19:46 PM PDT 24
Peak memory 207048 kb
Host smart-f3e444ee-6f03-47bb-a8a3-20c2db9c01fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937145067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.1937145067
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.1754284021
Short name T848
Test name
Test status
Simulation time 131156526 ps
CPU time 0.91 seconds
Started Mar 19 02:19:32 PM PDT 24
Finished Mar 19 02:19:33 PM PDT 24
Peak memory 205912 kb
Host smart-931e08d7-f474-440c-a700-04927d9c716f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1754284021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.1754284021
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.2575353965
Short name T740
Test name
Test status
Simulation time 19252494444 ps
CPU time 27.21 seconds
Started Mar 19 02:19:44 PM PDT 24
Finished Mar 19 02:20:11 PM PDT 24
Peak memory 250852 kb
Host smart-341346dc-799b-4376-a0d4-b70a87783f94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2575353965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.2575353965
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.920956701
Short name T790
Test name
Test status
Simulation time 12162780 ps
CPU time 0.69 seconds
Started Mar 19 02:19:54 PM PDT 24
Finished Mar 19 02:19:54 PM PDT 24
Peak memory 205512 kb
Host smart-23b4b025-af41-4a11-9a0d-2ff9010040e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920956701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.920956701
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.2213303097
Short name T951
Test name
Test status
Simulation time 1607323370 ps
CPU time 2.88 seconds
Started Mar 19 02:19:56 PM PDT 24
Finished Mar 19 02:19:59 PM PDT 24
Peak memory 219016 kb
Host smart-5ff75a46-6bd0-4a20-8f1b-68204ebeb6a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2213303097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.2213303097
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.2764333587
Short name T505
Test name
Test status
Simulation time 17594809 ps
CPU time 0.79 seconds
Started Mar 19 02:19:52 PM PDT 24
Finished Mar 19 02:19:52 PM PDT 24
Peak memory 206036 kb
Host smart-82d90e7d-77b5-4da5-a882-ae3011094154
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2764333587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.2764333587
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.3188803429
Short name T497
Test name
Test status
Simulation time 16840229684 ps
CPU time 130.58 seconds
Started Mar 19 02:19:54 PM PDT 24
Finished Mar 19 02:22:04 PM PDT 24
Peak memory 251632 kb
Host smart-4660ef25-4d44-4d70-ae74-848b881a1ee0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188803429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.3188803429
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.2971648322
Short name T415
Test name
Test status
Simulation time 11967237583 ps
CPU time 79.46 seconds
Started Mar 19 02:19:56 PM PDT 24
Finished Mar 19 02:21:15 PM PDT 24
Peak memory 237116 kb
Host smart-e7cbdb70-145d-45d1-af35-aa110c89d6cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971648322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.2971648322
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.550187065
Short name T218
Test name
Test status
Simulation time 510944408779 ps
CPU time 240.21 seconds
Started Mar 19 02:19:53 PM PDT 24
Finished Mar 19 02:23:54 PM PDT 24
Peak memory 239660 kb
Host smart-fb55efbb-c9b9-4e4d-aa7c-b2696259b303
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=550187065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idle
.550187065
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.1660907571
Short name T746
Test name
Test status
Simulation time 402332431 ps
CPU time 7.88 seconds
Started Mar 19 02:19:53 PM PDT 24
Finished Mar 19 02:20:01 PM PDT 24
Peak memory 238860 kb
Host smart-21548b22-a0bd-431c-99de-610daab3b93a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1660907571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.1660907571
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_intercept.3851825572
Short name T173
Test name
Test status
Simulation time 1363229684 ps
CPU time 6.8 seconds
Started Mar 19 02:19:54 PM PDT 24
Finished Mar 19 02:20:00 PM PDT 24
Peak memory 235140 kb
Host smart-5229fbe0-e734-42de-8f8b-1e24922a3f1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3851825572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.3851825572
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.738876976
Short name T526
Test name
Test status
Simulation time 38118337073 ps
CPU time 33.16 seconds
Started Mar 19 02:19:53 PM PDT 24
Finished Mar 19 02:20:26 PM PDT 24
Peak memory 246380 kb
Host smart-38007fe0-512e-42d2-9848-7b1c0ff39850
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=738876976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.738876976
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.827660536
Short name T241
Test name
Test status
Simulation time 37825292383 ps
CPU time 17 seconds
Started Mar 19 02:19:55 PM PDT 24
Finished Mar 19 02:20:12 PM PDT 24
Peak memory 225008 kb
Host smart-e059d7ad-4ff2-469c-b767-0f01bd6e1ccf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=827660536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swap
.827660536
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.3292650166
Short name T584
Test name
Test status
Simulation time 3605786336 ps
CPU time 8.65 seconds
Started Mar 19 02:19:55 PM PDT 24
Finished Mar 19 02:20:04 PM PDT 24
Peak memory 219020 kb
Host smart-59616be5-a42d-4165-a834-da0338526563
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3292650166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.3292650166
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.3480483182
Short name T142
Test name
Test status
Simulation time 1375777373 ps
CPU time 5.6 seconds
Started Mar 19 02:19:55 PM PDT 24
Finished Mar 19 02:20:00 PM PDT 24
Peak memory 222544 kb
Host smart-bf25b62f-68e2-4f6f-9127-2015a2cf8077
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3480483182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dir
ect.3480483182
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.3471857347
Short name T210
Test name
Test status
Simulation time 155001177431 ps
CPU time 285.26 seconds
Started Mar 19 02:19:52 PM PDT 24
Finished Mar 19 02:24:38 PM PDT 24
Peak memory 257924 kb
Host smart-9bcb91a5-309b-4524-93ab-3e2b05db3b3b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471857347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stre
ss_all.3471857347
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.483880493
Short name T800
Test name
Test status
Simulation time 40429993041 ps
CPU time 49.2 seconds
Started Mar 19 02:19:52 PM PDT 24
Finished Mar 19 02:20:41 PM PDT 24
Peak memory 216784 kb
Host smart-9b149c64-2a25-4d81-8ec6-a14b951cf67c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=483880493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.483880493
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.3113256069
Short name T518
Test name
Test status
Simulation time 11549644778 ps
CPU time 13.2 seconds
Started Mar 19 02:19:53 PM PDT 24
Finished Mar 19 02:20:06 PM PDT 24
Peak memory 216792 kb
Host smart-64782164-a6fe-4f4c-9204-32b9ed1db0ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3113256069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.3113256069
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.4044212463
Short name T337
Test name
Test status
Simulation time 191603940 ps
CPU time 1.98 seconds
Started Mar 19 02:19:56 PM PDT 24
Finished Mar 19 02:19:58 PM PDT 24
Peak memory 216736 kb
Host smart-72365501-9e6d-45b1-a0b5-00b88d0f9dbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4044212463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.4044212463
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.556538854
Short name T854
Test name
Test status
Simulation time 159064432 ps
CPU time 0.82 seconds
Started Mar 19 02:19:54 PM PDT 24
Finished Mar 19 02:19:55 PM PDT 24
Peak memory 205920 kb
Host smart-91817e13-1eea-49c6-813d-882defe2f658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556538854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.556538854
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.4063803651
Short name T621
Test name
Test status
Simulation time 4101688193 ps
CPU time 7.07 seconds
Started Mar 19 02:19:54 PM PDT 24
Finished Mar 19 02:20:01 PM PDT 24
Peak memory 235184 kb
Host smart-154631b0-0a73-4312-af5b-31fcf892e755
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4063803651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.4063803651
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.381166656
Short name T323
Test name
Test status
Simulation time 33294644 ps
CPU time 0.72 seconds
Started Mar 19 02:20:06 PM PDT 24
Finished Mar 19 02:20:07 PM PDT 24
Peak memory 205956 kb
Host smart-13f589ec-b4b5-438d-a6ce-f3d3af4a9ca2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381166656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.381166656
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.3929749821
Short name T960
Test name
Test status
Simulation time 1326630517 ps
CPU time 3.45 seconds
Started Mar 19 02:19:54 PM PDT 24
Finished Mar 19 02:19:58 PM PDT 24
Peak memory 236012 kb
Host smart-ca64792f-14ef-4c89-a4da-6eb006a9c6c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929749821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.3929749821
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.3522397378
Short name T845
Test name
Test status
Simulation time 263336738 ps
CPU time 0.75 seconds
Started Mar 19 02:19:56 PM PDT 24
Finished Mar 19 02:19:57 PM PDT 24
Peak memory 207072 kb
Host smart-77f6fdd2-5c94-4072-9d03-c79b36e1d7a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522397378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.3522397378
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.1412704792
Short name T797
Test name
Test status
Simulation time 14208638295 ps
CPU time 70.69 seconds
Started Mar 19 02:20:06 PM PDT 24
Finished Mar 19 02:21:17 PM PDT 24
Peak memory 238376 kb
Host smart-6e5451f1-8884-4711-944b-5d57923a4206
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1412704792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.1412704792
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.2213099896
Short name T209
Test name
Test status
Simulation time 26218595073 ps
CPU time 64.92 seconds
Started Mar 19 02:20:05 PM PDT 24
Finished Mar 19 02:21:10 PM PDT 24
Peak memory 250724 kb
Host smart-8af8c5c9-ee1a-45d1-841a-0bd35088cbd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2213099896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.2213099896
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.158070093
Short name T543
Test name
Test status
Simulation time 29440207493 ps
CPU time 79.14 seconds
Started Mar 19 02:20:06 PM PDT 24
Finished Mar 19 02:21:25 PM PDT 24
Peak memory 241220 kb
Host smart-d1fa0272-50e3-4016-a289-371de93becdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158070093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idle
.158070093
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.252127163
Short name T677
Test name
Test status
Simulation time 6911274773 ps
CPU time 22.08 seconds
Started Mar 19 02:20:05 PM PDT 24
Finished Mar 19 02:20:27 PM PDT 24
Peak memory 241316 kb
Host smart-4eb7a8e0-d85e-4ceb-99b0-cdeedfef6bf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=252127163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.252127163
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_intercept.97905575
Short name T121
Test name
Test status
Simulation time 10407333227 ps
CPU time 10.21 seconds
Started Mar 19 02:19:54 PM PDT 24
Finished Mar 19 02:20:04 PM PDT 24
Peak memory 238572 kb
Host smart-3e888f1a-7999-4e25-9458-32dc02ddb680
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97905575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.97905575
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.4209043891
Short name T535
Test name
Test status
Simulation time 13037325205 ps
CPU time 11.5 seconds
Started Mar 19 02:19:56 PM PDT 24
Finished Mar 19 02:20:08 PM PDT 24
Peak memory 233200 kb
Host smart-9e48299b-b599-4ff3-a5fe-72a964f5e546
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4209043891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.4209043891
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.3858724280
Short name T762
Test name
Test status
Simulation time 446471606 ps
CPU time 5.72 seconds
Started Mar 19 02:19:54 PM PDT 24
Finished Mar 19 02:20:00 PM PDT 24
Peak memory 233460 kb
Host smart-efd5e130-3bf7-4bd0-b311-63cea2e48ccb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3858724280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swa
p.3858724280
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.3021690788
Short name T792
Test name
Test status
Simulation time 774634299 ps
CPU time 3.38 seconds
Started Mar 19 02:19:54 PM PDT 24
Finished Mar 19 02:19:57 PM PDT 24
Peak memory 233528 kb
Host smart-d2725b91-c601-48e4-b5a0-116ffefba2eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021690788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.3021690788
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.2775163367
Short name T478
Test name
Test status
Simulation time 3014287162 ps
CPU time 7 seconds
Started Mar 19 02:20:05 PM PDT 24
Finished Mar 19 02:20:12 PM PDT 24
Peak memory 223468 kb
Host smart-3312bce4-56b2-4aa1-ace4-1c221661f3bd
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2775163367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dir
ect.2775163367
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.1113030195
Short name T50
Test name
Test status
Simulation time 61590833768 ps
CPU time 523.61 seconds
Started Mar 19 02:20:05 PM PDT 24
Finished Mar 19 02:28:49 PM PDT 24
Peak memory 282264 kb
Host smart-39b6e699-af65-471d-b90e-d219414c62fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113030195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stre
ss_all.1113030195
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.415242757
Short name T717
Test name
Test status
Simulation time 2370725723 ps
CPU time 30.74 seconds
Started Mar 19 02:19:58 PM PDT 24
Finished Mar 19 02:20:29 PM PDT 24
Peak memory 216704 kb
Host smart-369ce2cb-0742-4712-a156-6cb7f21db3e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415242757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.415242757
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.895950489
Short name T454
Test name
Test status
Simulation time 2346177991 ps
CPU time 7.4 seconds
Started Mar 19 02:19:55 PM PDT 24
Finished Mar 19 02:20:03 PM PDT 24
Peak memory 216736 kb
Host smart-dc1764fe-f80c-428a-8254-0a8098db88b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=895950489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.895950489
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.1780228991
Short name T577
Test name
Test status
Simulation time 649388010 ps
CPU time 5.49 seconds
Started Mar 19 02:19:54 PM PDT 24
Finished Mar 19 02:20:00 PM PDT 24
Peak memory 216784 kb
Host smart-b0d1dba3-117c-444f-93a8-fa1ae0cd6a4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1780228991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.1780228991
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.4091737974
Short name T530
Test name
Test status
Simulation time 194391865 ps
CPU time 1.24 seconds
Started Mar 19 02:19:54 PM PDT 24
Finished Mar 19 02:19:55 PM PDT 24
Peak memory 205860 kb
Host smart-7162a9a2-8fc8-4ebb-af15-1bc1ff497ce1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4091737974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.4091737974
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.446463506
Short name T755
Test name
Test status
Simulation time 1950474885 ps
CPU time 11.22 seconds
Started Mar 19 02:19:56 PM PDT 24
Finished Mar 19 02:20:08 PM PDT 24
Peak memory 230460 kb
Host smart-af187fb9-2193-4c41-b0b9-b594bf99c6b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=446463506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.446463506
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.84571319
Short name T695
Test name
Test status
Simulation time 14143972 ps
CPU time 0.75 seconds
Started Mar 19 02:20:07 PM PDT 24
Finished Mar 19 02:20:07 PM PDT 24
Peak memory 205580 kb
Host smart-de1f0f18-5b9f-4788-baaf-c718ed4b32f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84571319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.84571319
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.1204924654
Short name T418
Test name
Test status
Simulation time 693417751 ps
CPU time 3.61 seconds
Started Mar 19 02:20:08 PM PDT 24
Finished Mar 19 02:20:12 PM PDT 24
Peak memory 235756 kb
Host smart-eb2e9b59-3c97-4cb7-bee6-9a627863e9c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204924654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.1204924654
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.1507133591
Short name T618
Test name
Test status
Simulation time 21885954 ps
CPU time 0.8 seconds
Started Mar 19 02:20:06 PM PDT 24
Finished Mar 19 02:20:07 PM PDT 24
Peak memory 206712 kb
Host smart-776c7986-ca34-4c67-b917-5f7dde731d6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1507133591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.1507133591
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.2157014628
Short name T273
Test name
Test status
Simulation time 45309969280 ps
CPU time 241.17 seconds
Started Mar 19 02:20:07 PM PDT 24
Finished Mar 19 02:24:08 PM PDT 24
Peak memory 241268 kb
Host smart-db1a9c26-d51c-4d92-8ef7-4e735f5af2ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157014628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.2157014628
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.653181657
Short name T137
Test name
Test status
Simulation time 9605253583 ps
CPU time 118.97 seconds
Started Mar 19 02:20:08 PM PDT 24
Finished Mar 19 02:22:07 PM PDT 24
Peak memory 254576 kb
Host smart-9956386e-4ae4-4908-a740-c3e2e082f1fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653181657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.653181657
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.436422144
Short name T769
Test name
Test status
Simulation time 51361164326 ps
CPU time 81.01 seconds
Started Mar 19 02:20:08 PM PDT 24
Finished Mar 19 02:21:29 PM PDT 24
Peak memory 266096 kb
Host smart-fcdb2ebe-4750-45fc-ab36-cdf298317bd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436422144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idle
.436422144
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.2999589203
Short name T890
Test name
Test status
Simulation time 10440848634 ps
CPU time 19.85 seconds
Started Mar 19 02:20:05 PM PDT 24
Finished Mar 19 02:20:25 PM PDT 24
Peak memory 244480 kb
Host smart-1de88a47-006a-4ef1-8142-97398832b830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999589203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.2999589203
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_intercept.120343993
Short name T5
Test name
Test status
Simulation time 214228502 ps
CPU time 2.46 seconds
Started Mar 19 02:20:06 PM PDT 24
Finished Mar 19 02:20:09 PM PDT 24
Peak memory 217100 kb
Host smart-017c8171-a0a5-4601-b362-428fadf8fa0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=120343993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.120343993
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.3014552963
Short name T682
Test name
Test status
Simulation time 7567282479 ps
CPU time 29.82 seconds
Started Mar 19 02:20:06 PM PDT 24
Finished Mar 19 02:20:36 PM PDT 24
Peak memory 240968 kb
Host smart-9a482f31-0d25-43a4-9c3b-d63a98122e19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014552963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.3014552963
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.881853731
Short name T910
Test name
Test status
Simulation time 972111164 ps
CPU time 4.19 seconds
Started Mar 19 02:20:08 PM PDT 24
Finished Mar 19 02:20:12 PM PDT 24
Peak memory 222928 kb
Host smart-a7a87aa0-0c6c-4b4f-bfeb-dc4c292977c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881853731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swap
.881853731
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.938445520
Short name T557
Test name
Test status
Simulation time 8284528199 ps
CPU time 13.1 seconds
Started Mar 19 02:20:06 PM PDT 24
Finished Mar 19 02:20:19 PM PDT 24
Peak memory 234168 kb
Host smart-0ad9eb4a-4223-4631-9f8f-d1b17e67bab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938445520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.938445520
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.1606746393
Short name T613
Test name
Test status
Simulation time 172341921 ps
CPU time 3.83 seconds
Started Mar 19 02:20:08 PM PDT 24
Finished Mar 19 02:20:12 PM PDT 24
Peak memory 222688 kb
Host smart-f52bff6c-b1f6-4f78-ac09-797239fa2485
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1606746393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dir
ect.1606746393
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.946476170
Short name T754
Test name
Test status
Simulation time 3330718634 ps
CPU time 73.1 seconds
Started Mar 19 02:20:08 PM PDT 24
Finished Mar 19 02:21:21 PM PDT 24
Peak memory 257896 kb
Host smart-25db3724-011b-4a1b-8077-325637e8bcae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946476170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stres
s_all.946476170
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.2844529295
Short name T920
Test name
Test status
Simulation time 27049162798 ps
CPU time 72.27 seconds
Started Mar 19 02:20:03 PM PDT 24
Finished Mar 19 02:21:16 PM PDT 24
Peak memory 216884 kb
Host smart-4ff9556e-dfa7-45b5-8a31-6bed392c0963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2844529295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.2844529295
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.1644057299
Short name T309
Test name
Test status
Simulation time 1642280163 ps
CPU time 7 seconds
Started Mar 19 02:20:04 PM PDT 24
Finished Mar 19 02:20:11 PM PDT 24
Peak memory 216644 kb
Host smart-ab2a651a-c3f3-4600-8f86-055ce792429e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644057299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.1644057299
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.2306109901
Short name T297
Test name
Test status
Simulation time 33348279 ps
CPU time 1.12 seconds
Started Mar 19 02:20:05 PM PDT 24
Finished Mar 19 02:20:07 PM PDT 24
Peak memory 207460 kb
Host smart-b801ab59-c54a-47b4-920e-c9c11575b897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2306109901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.2306109901
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.3088422966
Short name T902
Test name
Test status
Simulation time 39176822 ps
CPU time 0.97 seconds
Started Mar 19 02:20:05 PM PDT 24
Finished Mar 19 02:20:06 PM PDT 24
Peak memory 206932 kb
Host smart-2c4472ac-2566-4ce6-8041-dba0344036b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3088422966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.3088422966
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.1915164260
Short name T232
Test name
Test status
Simulation time 718983916 ps
CPU time 8.78 seconds
Started Mar 19 02:20:06 PM PDT 24
Finished Mar 19 02:20:15 PM PDT 24
Peak memory 220536 kb
Host smart-9dd17b4b-2bae-49b2-bc4b-aa885fb28ec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1915164260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.1915164260
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.1371516171
Short name T936
Test name
Test status
Simulation time 15677392 ps
CPU time 0.76 seconds
Started Mar 19 02:20:23 PM PDT 24
Finished Mar 19 02:20:23 PM PDT 24
Peak memory 205632 kb
Host smart-c6b8cd79-cefe-4f21-b4ad-9e07f4fe86b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371516171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.
1371516171
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.557297754
Short name T721
Test name
Test status
Simulation time 126958703 ps
CPU time 2.87 seconds
Started Mar 19 02:20:08 PM PDT 24
Finished Mar 19 02:20:11 PM PDT 24
Peak memory 233964 kb
Host smart-7bdfdc35-508f-4254-890a-647c9dbe5cc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=557297754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.557297754
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.2986470488
Short name T930
Test name
Test status
Simulation time 15900707 ps
CPU time 0.76 seconds
Started Mar 19 02:20:07 PM PDT 24
Finished Mar 19 02:20:08 PM PDT 24
Peak memory 205960 kb
Host smart-87d173ef-eca0-4189-b080-234d139dfa18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986470488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.2986470488
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.613762630
Short name T204
Test name
Test status
Simulation time 126180801383 ps
CPU time 140.2 seconds
Started Mar 19 02:20:23 PM PDT 24
Finished Mar 19 02:22:43 PM PDT 24
Peak memory 253376 kb
Host smart-78afd1ec-25a5-4fa5-afc8-e3ab7a801c87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613762630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.613762630
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.2791687130
Short name T595
Test name
Test status
Simulation time 136069853355 ps
CPU time 208.92 seconds
Started Mar 19 02:20:21 PM PDT 24
Finished Mar 19 02:23:50 PM PDT 24
Peak memory 237792 kb
Host smart-fa7e69b7-08fa-42fb-bd54-718a9903fef5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2791687130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.2791687130
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.3922204657
Short name T709
Test name
Test status
Simulation time 38650233610 ps
CPU time 123.27 seconds
Started Mar 19 02:20:21 PM PDT 24
Finished Mar 19 02:22:25 PM PDT 24
Peak memory 249748 kb
Host smart-124c728b-272b-4fc2-95ed-bf7b30681300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3922204657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idl
e.3922204657
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.1205047016
Short name T521
Test name
Test status
Simulation time 1283058546 ps
CPU time 9.17 seconds
Started Mar 19 02:20:22 PM PDT 24
Finished Mar 19 02:20:31 PM PDT 24
Peak memory 243760 kb
Host smart-a4995823-6fee-4891-92b7-985d2e2cbf11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1205047016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.1205047016
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_intercept.2492560207
Short name T686
Test name
Test status
Simulation time 9343329022 ps
CPU time 10.19 seconds
Started Mar 19 02:20:06 PM PDT 24
Finished Mar 19 02:20:16 PM PDT 24
Peak memory 221100 kb
Host smart-43a45690-0e2a-4f1d-8eea-0ad2f3ee0840
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492560207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.2492560207
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.2602665344
Short name T353
Test name
Test status
Simulation time 1668828166 ps
CPU time 7.93 seconds
Started Mar 19 02:20:06 PM PDT 24
Finished Mar 19 02:20:14 PM PDT 24
Peak memory 240856 kb
Host smart-591bf756-f7b7-4f5b-8a11-8a96ffbaad7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2602665344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.2602665344
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.560473651
Short name T694
Test name
Test status
Simulation time 29512903 ps
CPU time 2.11 seconds
Started Mar 19 02:20:06 PM PDT 24
Finished Mar 19 02:20:08 PM PDT 24
Peak memory 224848 kb
Host smart-7d661a2d-f106-4d70-84d2-ced0be4ba56a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=560473651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swap
.560473651
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.1184625404
Short name T217
Test name
Test status
Simulation time 679492960 ps
CPU time 9.96 seconds
Started Mar 19 02:20:06 PM PDT 24
Finished Mar 19 02:20:16 PM PDT 24
Peak memory 233948 kb
Host smart-98c90deb-6ec7-41a7-894b-cd5d97ccebfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1184625404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.1184625404
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.1159117652
Short name T144
Test name
Test status
Simulation time 20869905098 ps
CPU time 6.74 seconds
Started Mar 19 02:20:24 PM PDT 24
Finished Mar 19 02:20:31 PM PDT 24
Peak memory 219528 kb
Host smart-9d67e8f8-3eed-47ba-b828-2200aeeecae4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1159117652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir
ect.1159117652
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.3379666239
Short name T264
Test name
Test status
Simulation time 27010443581 ps
CPU time 267.65 seconds
Started Mar 19 02:20:22 PM PDT 24
Finished Mar 19 02:24:50 PM PDT 24
Peak memory 267156 kb
Host smart-1a62a2f0-ecf8-49a3-b9cf-1c7f0ec93340
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379666239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stre
ss_all.3379666239
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.810728797
Short name T423
Test name
Test status
Simulation time 23115835546 ps
CPU time 69.03 seconds
Started Mar 19 02:20:07 PM PDT 24
Finished Mar 19 02:21:16 PM PDT 24
Peak memory 216840 kb
Host smart-aa1f55c5-7599-4062-88e8-e82518960ae1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810728797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.810728797
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.3733226336
Short name T798
Test name
Test status
Simulation time 3563113625 ps
CPU time 15.08 seconds
Started Mar 19 02:20:08 PM PDT 24
Finished Mar 19 02:20:23 PM PDT 24
Peak memory 216732 kb
Host smart-181c1bbb-5bb4-4752-8467-f5bde299bf83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3733226336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.3733226336
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.3410290249
Short name T841
Test name
Test status
Simulation time 48458514 ps
CPU time 1.38 seconds
Started Mar 19 02:20:08 PM PDT 24
Finished Mar 19 02:20:10 PM PDT 24
Peak memory 216604 kb
Host smart-1c8f60fb-28be-4aba-b37a-77684e4cd990
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3410290249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.3410290249
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.19809908
Short name T472
Test name
Test status
Simulation time 143456776 ps
CPU time 1.08 seconds
Started Mar 19 02:20:04 PM PDT 24
Finished Mar 19 02:20:05 PM PDT 24
Peak memory 206952 kb
Host smart-5dbdeef5-6a9a-4308-9312-1ddb3664d34f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19809908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.19809908
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.3332431183
Short name T386
Test name
Test status
Simulation time 1077733689 ps
CPU time 3.3 seconds
Started Mar 19 02:20:07 PM PDT 24
Finished Mar 19 02:20:10 PM PDT 24
Peak memory 235904 kb
Host smart-56b91540-49ca-44ba-a2b3-1d3963b91f5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332431183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.3332431183
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.502483894
Short name T68
Test name
Test status
Simulation time 40226424 ps
CPU time 0.75 seconds
Started Mar 19 02:20:22 PM PDT 24
Finished Mar 19 02:20:22 PM PDT 24
Peak memory 205064 kb
Host smart-a3321282-6559-4e07-acf1-b2e77bf2ea03
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502483894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.502483894
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.3301580740
Short name T967
Test name
Test status
Simulation time 500087691 ps
CPU time 2.61 seconds
Started Mar 19 02:20:23 PM PDT 24
Finished Mar 19 02:20:26 PM PDT 24
Peak memory 217000 kb
Host smart-ddfe4b36-5820-4c22-a59f-a3d596146bb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3301580740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.3301580740
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.985371611
Short name T802
Test name
Test status
Simulation time 40422113 ps
CPU time 0.78 seconds
Started Mar 19 02:20:22 PM PDT 24
Finished Mar 19 02:20:23 PM PDT 24
Peak memory 206700 kb
Host smart-2d123ed3-7eab-4c00-b926-bf687e887325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985371611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.985371611
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.3092529699
Short name T699
Test name
Test status
Simulation time 23311736845 ps
CPU time 138.44 seconds
Started Mar 19 02:20:22 PM PDT 24
Finished Mar 19 02:22:41 PM PDT 24
Peak memory 249656 kb
Host smart-4191a01c-5a04-4a5a-8e7f-b4bc4333470a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3092529699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.3092529699
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.919314361
Short name T536
Test name
Test status
Simulation time 2359253546 ps
CPU time 36.04 seconds
Started Mar 19 02:20:23 PM PDT 24
Finished Mar 19 02:20:59 PM PDT 24
Peak memory 255912 kb
Host smart-98ddc22d-581a-4e32-9832-90cb79a162b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=919314361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.919314361
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.4020501681
Short name T531
Test name
Test status
Simulation time 14877263451 ps
CPU time 136.1 seconds
Started Mar 19 02:20:23 PM PDT 24
Finished Mar 19 02:22:39 PM PDT 24
Peak memory 257612 kb
Host smart-b6cca129-9702-4032-981e-12eb70b7d4e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4020501681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idl
e.4020501681
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.3819506066
Short name T638
Test name
Test status
Simulation time 3010903110 ps
CPU time 21.85 seconds
Started Mar 19 02:20:23 PM PDT 24
Finished Mar 19 02:20:46 PM PDT 24
Peak memory 234264 kb
Host smart-0c41059e-4cd9-468d-a224-203bd65a80c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819506066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.3819506066
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_intercept.3740984762
Short name T564
Test name
Test status
Simulation time 4041297384 ps
CPU time 15.14 seconds
Started Mar 19 02:20:25 PM PDT 24
Finished Mar 19 02:20:40 PM PDT 24
Peak memory 235308 kb
Host smart-b9bcb90c-424b-4ac3-aee1-e5fcf70f061d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3740984762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.3740984762
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.2620478416
Short name T442
Test name
Test status
Simulation time 3878160654 ps
CPU time 5.77 seconds
Started Mar 19 02:20:21 PM PDT 24
Finished Mar 19 02:20:27 PM PDT 24
Peak memory 238424 kb
Host smart-b4993d83-3667-4eef-a586-bb32333d6882
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620478416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.2620478416
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.122945383
Short name T851
Test name
Test status
Simulation time 428716832 ps
CPU time 4.06 seconds
Started Mar 19 02:20:23 PM PDT 24
Finished Mar 19 02:20:27 PM PDT 24
Peak memory 217088 kb
Host smart-eaadc156-7e40-493e-9846-584d1595b7ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=122945383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swap
.122945383
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.1589852200
Short name T408
Test name
Test status
Simulation time 69645903 ps
CPU time 2.19 seconds
Started Mar 19 02:20:22 PM PDT 24
Finished Mar 19 02:20:24 PM PDT 24
Peak memory 218308 kb
Host smart-de6ec6b3-081a-43bf-bbd9-53fdb8696bf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589852200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.1589852200
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.3804330207
Short name T414
Test name
Test status
Simulation time 198954455 ps
CPU time 3.49 seconds
Started Mar 19 02:20:21 PM PDT 24
Finished Mar 19 02:20:25 PM PDT 24
Peak memory 223232 kb
Host smart-a64bac75-cda9-4c57-b6f0-5377d0328c31
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3804330207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dir
ect.3804330207
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.1524859777
Short name T261
Test name
Test status
Simulation time 555100512967 ps
CPU time 1020.97 seconds
Started Mar 19 02:20:23 PM PDT 24
Finished Mar 19 02:37:24 PM PDT 24
Peak memory 274296 kb
Host smart-c592e1e6-2d03-4a3a-b1e5-56fd9a836337
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524859777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stre
ss_all.1524859777
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.1558489246
Short name T19
Test name
Test status
Simulation time 2071854683 ps
CPU time 21.02 seconds
Started Mar 19 02:20:23 PM PDT 24
Finished Mar 19 02:20:45 PM PDT 24
Peak memory 216740 kb
Host smart-6dd68187-c33f-4b96-a1b2-11f8c9377f71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558489246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.1558489246
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.3977453674
Short name T594
Test name
Test status
Simulation time 17060355282 ps
CPU time 11.33 seconds
Started Mar 19 02:20:22 PM PDT 24
Finished Mar 19 02:20:33 PM PDT 24
Peak memory 216620 kb
Host smart-9389a26d-2a4a-462c-8871-8a81fd8c9426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3977453674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.3977453674
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.4035605638
Short name T629
Test name
Test status
Simulation time 32065829 ps
CPU time 0.78 seconds
Started Mar 19 02:20:23 PM PDT 24
Finished Mar 19 02:20:24 PM PDT 24
Peak memory 205948 kb
Host smart-f0327721-c699-47c0-b58a-0b840f965c6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4035605638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.4035605638
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.3140858890
Short name T550
Test name
Test status
Simulation time 200955370 ps
CPU time 0.96 seconds
Started Mar 19 02:20:23 PM PDT 24
Finished Mar 19 02:20:24 PM PDT 24
Peak memory 206896 kb
Host smart-a2a28178-236c-4992-907f-f2847ea30df4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3140858890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.3140858890
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.3846363115
Short name T468
Test name
Test status
Simulation time 89796297 ps
CPU time 3.03 seconds
Started Mar 19 02:20:21 PM PDT 24
Finished Mar 19 02:20:24 PM PDT 24
Peak memory 234820 kb
Host smart-ccf81a12-d942-4789-9420-aadc8e924b05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3846363115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.3846363115
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.2027983153
Short name T701
Test name
Test status
Simulation time 18423311 ps
CPU time 0.76 seconds
Started Mar 19 02:20:35 PM PDT 24
Finished Mar 19 02:20:36 PM PDT 24
Peak memory 205600 kb
Host smart-4d6ad9f8-14f7-4a38-a73e-d7c7589774c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027983153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.
2027983153
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.477788168
Short name T427
Test name
Test status
Simulation time 88264842 ps
CPU time 2.59 seconds
Started Mar 19 02:20:36 PM PDT 24
Finished Mar 19 02:20:39 PM PDT 24
Peak memory 233656 kb
Host smart-2ba1473f-1ea1-4cef-8c34-77fca404a62b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=477788168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.477788168
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.3164756650
Short name T612
Test name
Test status
Simulation time 42660941 ps
CPU time 0.86 seconds
Started Mar 19 02:20:24 PM PDT 24
Finished Mar 19 02:20:25 PM PDT 24
Peak memory 206732 kb
Host smart-bc03767e-8c6c-4dfa-b1b7-78349af879d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3164756650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.3164756650
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.712489571
Short name T233
Test name
Test status
Simulation time 23703541999 ps
CPU time 112.56 seconds
Started Mar 19 02:20:36 PM PDT 24
Finished Mar 19 02:22:28 PM PDT 24
Peak memory 266272 kb
Host smart-afea2edc-24d4-43da-847c-a544f800b676
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=712489571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.712489571
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.1441236117
Short name T691
Test name
Test status
Simulation time 72062146517 ps
CPU time 302.99 seconds
Started Mar 19 02:20:36 PM PDT 24
Finished Mar 19 02:25:39 PM PDT 24
Peak memory 267116 kb
Host smart-a40d87dd-3dc9-4987-859a-0a046e908f2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1441236117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idl
e.1441236117
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.2257159679
Short name T83
Test name
Test status
Simulation time 2136082614 ps
CPU time 9.19 seconds
Started Mar 19 02:20:35 PM PDT 24
Finished Mar 19 02:20:44 PM PDT 24
Peak memory 246420 kb
Host smart-a712087a-365e-407c-abec-c05a3132beae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2257159679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.2257159679
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_intercept.920801361
Short name T948
Test name
Test status
Simulation time 3324634369 ps
CPU time 7.21 seconds
Started Mar 19 02:20:38 PM PDT 24
Finished Mar 19 02:20:46 PM PDT 24
Peak memory 233564 kb
Host smart-ed1f07b5-29ab-44d8-94f8-fe3754dc98e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920801361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.920801361
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.3310467456
Short name T225
Test name
Test status
Simulation time 11898573603 ps
CPU time 19.87 seconds
Started Mar 19 02:20:34 PM PDT 24
Finished Mar 19 02:20:54 PM PDT 24
Peak memory 238392 kb
Host smart-ef5e167b-3033-4ea8-a914-aee1c4da44d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3310467456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.3310467456
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.2926651370
Short name T671
Test name
Test status
Simulation time 40418831722 ps
CPU time 28.94 seconds
Started Mar 19 02:20:36 PM PDT 24
Finished Mar 19 02:21:05 PM PDT 24
Peak memory 241092 kb
Host smart-dec7e302-8977-44be-b98e-c2c8752926d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2926651370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swa
p.2926651370
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.4288487322
Short name T251
Test name
Test status
Simulation time 6777373443 ps
CPU time 17.1 seconds
Started Mar 19 02:20:37 PM PDT 24
Finished Mar 19 02:20:54 PM PDT 24
Peak memory 225108 kb
Host smart-8eea8940-f60a-49bb-8ba7-353d5fa70dcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288487322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.4288487322
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.3076114546
Short name T624
Test name
Test status
Simulation time 58012765 ps
CPU time 2.87 seconds
Started Mar 19 02:20:39 PM PDT 24
Finished Mar 19 02:20:43 PM PDT 24
Peak memory 223252 kb
Host smart-4f63df6e-e9ad-4294-92ee-edc1defb1426
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3076114546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dir
ect.3076114546
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.847928514
Short name T283
Test name
Test status
Simulation time 3220886274 ps
CPU time 25.88 seconds
Started Mar 19 02:20:23 PM PDT 24
Finished Mar 19 02:20:50 PM PDT 24
Peak memory 216660 kb
Host smart-a144fda1-2e3b-4410-93c0-dda88b019a70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847928514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.847928514
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.2283363049
Short name T573
Test name
Test status
Simulation time 6917909447 ps
CPU time 15.23 seconds
Started Mar 19 02:20:23 PM PDT 24
Finished Mar 19 02:20:38 PM PDT 24
Peak memory 216832 kb
Host smart-62cef65f-f9e0-4912-a561-1f4e884db3d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2283363049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.2283363049
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.2920247455
Short name T469
Test name
Test status
Simulation time 63859588 ps
CPU time 1.87 seconds
Started Mar 19 02:20:35 PM PDT 24
Finished Mar 19 02:20:37 PM PDT 24
Peak memory 216592 kb
Host smart-82295b23-1e06-435f-b032-81a290cf8cfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920247455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.2920247455
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.2216867664
Short name T773
Test name
Test status
Simulation time 153198870 ps
CPU time 1.07 seconds
Started Mar 19 02:20:23 PM PDT 24
Finished Mar 19 02:20:25 PM PDT 24
Peak memory 206828 kb
Host smart-9c97cf48-620b-494c-8b6f-6b1b00b12e84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2216867664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.2216867664
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.2257933520
Short name T362
Test name
Test status
Simulation time 1013311487 ps
CPU time 8.08 seconds
Started Mar 19 02:20:34 PM PDT 24
Finished Mar 19 02:20:43 PM PDT 24
Peak memory 236440 kb
Host smart-3d73811b-78ac-486f-96f4-d400aefc951e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2257933520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.2257933520
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.2275383663
Short name T80
Test name
Test status
Simulation time 14866579 ps
CPU time 0.74 seconds
Started Mar 19 02:15:07 PM PDT 24
Finished Mar 19 02:15:08 PM PDT 24
Peak memory 205676 kb
Host smart-19f544d3-28d7-40a3-b956-85506f31a2b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275383663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.2
275383663
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.1451410808
Short name T870
Test name
Test status
Simulation time 2794544630 ps
CPU time 8.39 seconds
Started Mar 19 02:14:50 PM PDT 24
Finished Mar 19 02:15:00 PM PDT 24
Peak memory 235772 kb
Host smart-96d48d7e-7a7a-467e-a81a-c7059eb8af91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1451410808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.1451410808
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.4281278002
Short name T327
Test name
Test status
Simulation time 15189606 ps
CPU time 0.76 seconds
Started Mar 19 02:14:38 PM PDT 24
Finished Mar 19 02:14:39 PM PDT 24
Peak memory 206028 kb
Host smart-7b2a6270-d59f-46a1-9dfa-4138ce439206
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281278002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.4281278002
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.2125343533
Short name T238
Test name
Test status
Simulation time 121215843471 ps
CPU time 98.18 seconds
Started Mar 19 02:15:01 PM PDT 24
Finished Mar 19 02:16:39 PM PDT 24
Peak memory 237160 kb
Host smart-879afee1-9197-4848-abed-0b33f3eec905
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2125343533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.2125343533
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.346043520
Short name T944
Test name
Test status
Simulation time 6675443933 ps
CPU time 34.17 seconds
Started Mar 19 02:14:59 PM PDT 24
Finished Mar 19 02:15:33 PM PDT 24
Peak memory 224220 kb
Host smart-bc102a01-1dc2-469e-9612-4c07e64a6f1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=346043520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.346043520
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.733650038
Short name T662
Test name
Test status
Simulation time 269841205814 ps
CPU time 662.76 seconds
Started Mar 19 02:15:07 PM PDT 24
Finished Mar 19 02:26:10 PM PDT 24
Peak memory 254716 kb
Host smart-08019fe3-f85e-43f2-906e-da7aa480d1d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733650038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle.
733650038
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.3393005910
Short name T795
Test name
Test status
Simulation time 920604256 ps
CPU time 15.11 seconds
Started Mar 19 02:15:08 PM PDT 24
Finished Mar 19 02:15:23 PM PDT 24
Peak memory 236860 kb
Host smart-c4b1ef6e-4edb-4924-ae52-a3f42e03440a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3393005910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.3393005910
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_intercept.575127738
Short name T198
Test name
Test status
Simulation time 3400965213 ps
CPU time 10.12 seconds
Started Mar 19 02:14:50 PM PDT 24
Finished Mar 19 02:15:01 PM PDT 24
Peak memory 220132 kb
Host smart-bb92a398-cc3e-435b-9e0a-e777385bf564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575127738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.575127738
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.3903907383
Short name T817
Test name
Test status
Simulation time 518594341 ps
CPU time 5.49 seconds
Started Mar 19 02:14:50 PM PDT 24
Finished Mar 19 02:14:56 PM PDT 24
Peak memory 238600 kb
Host smart-d1391cef-8630-49c1-8539-0b37fca224ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903907383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.3903907383
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_mem_parity.4199161109
Short name T361
Test name
Test status
Simulation time 87222755 ps
CPU time 1.16 seconds
Started Mar 19 02:14:50 PM PDT 24
Finished Mar 19 02:14:52 PM PDT 24
Peak memory 216984 kb
Host smart-b5c184f3-5439-42af-92ef-f39c4e0afd31
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199161109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 4.spi_device_mem_parity.4199161109
Directory /workspace/4.spi_device_mem_parity/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.270355496
Short name T830
Test name
Test status
Simulation time 11421353375 ps
CPU time 35.54 seconds
Started Mar 19 02:14:50 PM PDT 24
Finished Mar 19 02:15:26 PM PDT 24
Peak memory 218344 kb
Host smart-9a74bde4-2492-41e7-ba2a-743fcd4b6a23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=270355496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap.
270355496
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.3935040065
Short name T733
Test name
Test status
Simulation time 2776502960 ps
CPU time 9.63 seconds
Started Mar 19 02:14:49 PM PDT 24
Finished Mar 19 02:15:00 PM PDT 24
Peak memory 233960 kb
Host smart-07dba1b6-19c3-4f0c-b5e8-a869ba5efa13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3935040065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.3935040065
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_ram_cfg.2962782897
Short name T837
Test name
Test status
Simulation time 41243523 ps
CPU time 0.76 seconds
Started Mar 19 02:14:49 PM PDT 24
Finished Mar 19 02:14:50 PM PDT 24
Peak memory 216488 kb
Host smart-61d43982-5b98-49f2-a813-8eedbc47c459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962782897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_ram_cfg.2962782897
Directory /workspace/4.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.4234088004
Short name T139
Test name
Test status
Simulation time 2776652749 ps
CPU time 7.2 seconds
Started Mar 19 02:14:59 PM PDT 24
Finished Mar 19 02:15:07 PM PDT 24
Peak memory 222184 kb
Host smart-bb9375d9-fec9-45eb-b511-01466a14451a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4234088004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire
ct.4234088004
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.1313314815
Short name T78
Test name
Test status
Simulation time 291960913 ps
CPU time 0.98 seconds
Started Mar 19 02:14:59 PM PDT 24
Finished Mar 19 02:15:01 PM PDT 24
Peak memory 235848 kb
Host smart-18107545-c138-4435-adbc-0cac837dc27b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313314815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.1313314815
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.212376997
Short name T744
Test name
Test status
Simulation time 132913102 ps
CPU time 0.99 seconds
Started Mar 19 02:15:01 PM PDT 24
Finished Mar 19 02:15:02 PM PDT 24
Peak memory 206992 kb
Host smart-be2c00a9-2c27-43bc-86bc-6794c1cde545
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212376997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stress
_all.212376997
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.64437116
Short name T355
Test name
Test status
Simulation time 3811481977 ps
CPU time 39.04 seconds
Started Mar 19 02:14:50 PM PDT 24
Finished Mar 19 02:15:30 PM PDT 24
Peak memory 216832 kb
Host smart-4ab106c0-7296-472a-ab44-651553d31760
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64437116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.64437116
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.4085148734
Short name T605
Test name
Test status
Simulation time 629008472 ps
CPU time 2.55 seconds
Started Mar 19 02:14:51 PM PDT 24
Finished Mar 19 02:14:54 PM PDT 24
Peak memory 208248 kb
Host smart-395f8fa9-6861-4bb2-abcb-2eb001615430
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085148734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.4085148734
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.848335866
Short name T455
Test name
Test status
Simulation time 217240943 ps
CPU time 7.67 seconds
Started Mar 19 02:14:50 PM PDT 24
Finished Mar 19 02:14:59 PM PDT 24
Peak memory 216800 kb
Host smart-c9234826-348c-4b5a-b43f-c7dae7734a28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848335866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.848335866
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.1491631213
Short name T509
Test name
Test status
Simulation time 113800728 ps
CPU time 0.84 seconds
Started Mar 19 02:14:51 PM PDT 24
Finished Mar 19 02:14:52 PM PDT 24
Peak memory 205928 kb
Host smart-81651561-d063-4c6f-923b-c7e3d328f235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1491631213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.1491631213
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.639201493
Short name T684
Test name
Test status
Simulation time 1307582421 ps
CPU time 4.63 seconds
Started Mar 19 02:14:49 PM PDT 24
Finished Mar 19 02:14:55 PM PDT 24
Peak memory 234384 kb
Host smart-5d46929a-c6ee-4db5-a239-4318ee28d193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639201493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.639201493
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.2795952398
Short name T324
Test name
Test status
Simulation time 56399725 ps
CPU time 0.74 seconds
Started Mar 19 02:20:39 PM PDT 24
Finished Mar 19 02:20:40 PM PDT 24
Peak memory 205976 kb
Host smart-6fee841f-627c-4bf8-9ec2-2b528428389c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795952398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.
2795952398
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.65664529
Short name T1
Test name
Test status
Simulation time 1600562325 ps
CPU time 5.13 seconds
Started Mar 19 02:20:37 PM PDT 24
Finished Mar 19 02:20:42 PM PDT 24
Peak memory 219864 kb
Host smart-af313748-aa20-4830-bb24-79e4c7031b31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65664529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.65664529
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.2880151171
Short name T447
Test name
Test status
Simulation time 15513340 ps
CPU time 0.74 seconds
Started Mar 19 02:20:36 PM PDT 24
Finished Mar 19 02:20:37 PM PDT 24
Peak memory 206052 kb
Host smart-a7a7af8a-9c58-4a02-8ab9-9d6eca6a76a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2880151171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.2880151171
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.69474561
Short name T305
Test name
Test status
Simulation time 8399893927 ps
CPU time 25.12 seconds
Started Mar 19 02:20:39 PM PDT 24
Finished Mar 19 02:21:05 PM PDT 24
Peak memory 241492 kb
Host smart-5d0dc899-9e80-4061-a893-02810991e147
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69474561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.69474561
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.3894531811
Short name T796
Test name
Test status
Simulation time 113163641621 ps
CPU time 239.96 seconds
Started Mar 19 02:20:34 PM PDT 24
Finished Mar 19 02:24:34 PM PDT 24
Peak memory 254228 kb
Host smart-439177be-8f49-4984-82ed-1c98abd33abc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894531811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.3894531811
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.1419675899
Short name T823
Test name
Test status
Simulation time 20919467660 ps
CPU time 150.21 seconds
Started Mar 19 02:20:40 PM PDT 24
Finished Mar 19 02:23:10 PM PDT 24
Peak memory 274236 kb
Host smart-567a34e6-96cb-4b22-8bd4-6eb439e8759a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1419675899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idl
e.1419675899
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.2243484473
Short name T502
Test name
Test status
Simulation time 899410403 ps
CPU time 13.23 seconds
Started Mar 19 02:20:36 PM PDT 24
Finished Mar 19 02:20:50 PM PDT 24
Peak memory 241300 kb
Host smart-95ac7636-e307-46e9-8695-179bc208da3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2243484473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.2243484473
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_intercept.378915042
Short name T431
Test name
Test status
Simulation time 3417138824 ps
CPU time 4.93 seconds
Started Mar 19 02:20:36 PM PDT 24
Finished Mar 19 02:20:41 PM PDT 24
Peak memory 234052 kb
Host smart-475b300e-1a15-4498-b8b9-64586554e843
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=378915042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.378915042
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.224837993
Short name T492
Test name
Test status
Simulation time 4179947065 ps
CPU time 7.35 seconds
Started Mar 19 02:20:40 PM PDT 24
Finished Mar 19 02:20:47 PM PDT 24
Peak memory 234292 kb
Host smart-16a75f23-64fd-452b-92bf-4e9d2b1e8df4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=224837993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.224837993
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.198461893
Short name T63
Test name
Test status
Simulation time 18631067674 ps
CPU time 15.56 seconds
Started Mar 19 02:20:36 PM PDT 24
Finished Mar 19 02:20:52 PM PDT 24
Peak memory 234860 kb
Host smart-f4fa3aaf-21b5-41ef-9dd1-f013afcb0cb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=198461893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swap
.198461893
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.1049009013
Short name T862
Test name
Test status
Simulation time 18134519793 ps
CPU time 32.16 seconds
Started Mar 19 02:20:35 PM PDT 24
Finished Mar 19 02:21:07 PM PDT 24
Peak memory 241236 kb
Host smart-0424a052-0ac9-4009-8379-6aefd88cafa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1049009013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.1049009013
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.4118501386
Short name T716
Test name
Test status
Simulation time 251292350 ps
CPU time 3.28 seconds
Started Mar 19 02:20:33 PM PDT 24
Finished Mar 19 02:20:37 PM PDT 24
Peak memory 223136 kb
Host smart-c1fb3acf-7012-4965-b79a-5a16f1cb753d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4118501386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir
ect.4118501386
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.1272125866
Short name T815
Test name
Test status
Simulation time 3808530555 ps
CPU time 32.41 seconds
Started Mar 19 02:20:38 PM PDT 24
Finished Mar 19 02:21:11 PM PDT 24
Peak memory 216804 kb
Host smart-a1bc8069-f133-4a7a-8fac-6a6f183e44d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1272125866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.1272125866
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.2100225180
Short name T332
Test name
Test status
Simulation time 15101783318 ps
CPU time 18.22 seconds
Started Mar 19 02:20:37 PM PDT 24
Finished Mar 19 02:20:56 PM PDT 24
Peak memory 216724 kb
Host smart-16bd1548-f739-4f94-926b-6d21148e8198
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2100225180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.2100225180
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.3618801962
Short name T700
Test name
Test status
Simulation time 311630660 ps
CPU time 1.6 seconds
Started Mar 19 02:20:36 PM PDT 24
Finished Mar 19 02:20:38 PM PDT 24
Peak memory 216604 kb
Host smart-bf5a7aff-23c4-4e7b-b53f-cf6e0221146e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3618801962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.3618801962
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.2712535685
Short name T369
Test name
Test status
Simulation time 266468643 ps
CPU time 0.93 seconds
Started Mar 19 02:20:35 PM PDT 24
Finished Mar 19 02:20:36 PM PDT 24
Peak memory 206964 kb
Host smart-c695f210-0f38-4696-b6ed-0dc391e9627e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712535685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.2712535685
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.1678747478
Short name T216
Test name
Test status
Simulation time 6873742598 ps
CPU time 24.49 seconds
Started Mar 19 02:20:33 PM PDT 24
Finished Mar 19 02:20:57 PM PDT 24
Peak memory 234132 kb
Host smart-3b05679a-bf1a-4163-ba12-bebf5f1046b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1678747478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.1678747478
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.3022191545
Short name T827
Test name
Test status
Simulation time 33471368 ps
CPU time 0.72 seconds
Started Mar 19 02:20:46 PM PDT 24
Finished Mar 19 02:20:47 PM PDT 24
Peak memory 205004 kb
Host smart-9f00cfa4-29ee-41f8-bce3-3bcc69cae630
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022191545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.
3022191545
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.3115222788
Short name T538
Test name
Test status
Simulation time 3845057388 ps
CPU time 5.06 seconds
Started Mar 19 02:20:39 PM PDT 24
Finished Mar 19 02:20:45 PM PDT 24
Peak memory 218424 kb
Host smart-daea4173-665d-4602-b3f4-c8ea4f3b1a6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3115222788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.3115222788
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.914021207
Short name T833
Test name
Test status
Simulation time 46154755 ps
CPU time 0.75 seconds
Started Mar 19 02:20:34 PM PDT 24
Finished Mar 19 02:20:35 PM PDT 24
Peak memory 205672 kb
Host smart-a7d76e3b-f7be-4fa7-9b51-7686ab7710f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=914021207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.914021207
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.3094015114
Short name T847
Test name
Test status
Simulation time 48683034539 ps
CPU time 121.68 seconds
Started Mar 19 02:20:48 PM PDT 24
Finished Mar 19 02:22:50 PM PDT 24
Peak memory 266064 kb
Host smart-f4f6d24d-7a17-4b1d-b341-a091c80b0e6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3094015114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.3094015114
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.3742687079
Short name T676
Test name
Test status
Simulation time 78540537320 ps
CPU time 308.61 seconds
Started Mar 19 02:20:47 PM PDT 24
Finished Mar 19 02:25:55 PM PDT 24
Peak memory 261804 kb
Host smart-173f76f3-6d92-41f9-ae36-feadaa05ac5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742687079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.3742687079
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.4078963475
Short name T208
Test name
Test status
Simulation time 8102739275 ps
CPU time 70.93 seconds
Started Mar 19 02:20:49 PM PDT 24
Finished Mar 19 02:22:01 PM PDT 24
Peak memory 260676 kb
Host smart-a8ca9650-3b0e-49c0-a75f-34a8b432fd78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078963475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idl
e.4078963475
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_intercept.367837746
Short name T520
Test name
Test status
Simulation time 790665444 ps
CPU time 3.31 seconds
Started Mar 19 02:20:35 PM PDT 24
Finished Mar 19 02:20:38 PM PDT 24
Peak memory 218340 kb
Host smart-d5c73df1-c759-4961-bd34-0201f5efcb49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367837746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.367837746
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.1138021636
Short name T655
Test name
Test status
Simulation time 1736092987 ps
CPU time 7.84 seconds
Started Mar 19 02:20:39 PM PDT 24
Finished Mar 19 02:20:47 PM PDT 24
Peak memory 218784 kb
Host smart-c4c60b11-4062-40c7-a2a4-b9ff553cfdb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138021636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.1138021636
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.2807312288
Short name T242
Test name
Test status
Simulation time 3902150142 ps
CPU time 5.93 seconds
Started Mar 19 02:20:35 PM PDT 24
Finished Mar 19 02:20:41 PM PDT 24
Peak memory 218168 kb
Host smart-0c075e11-c372-4f89-81ce-f4dd9604dad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807312288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swa
p.2807312288
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.387851172
Short name T786
Test name
Test status
Simulation time 47189917464 ps
CPU time 34.82 seconds
Started Mar 19 02:20:40 PM PDT 24
Finished Mar 19 02:21:15 PM PDT 24
Peak memory 240748 kb
Host smart-4560283a-fa0e-47b9-a595-6beb4026bd21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387851172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.387851172
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.1072625670
Short name T819
Test name
Test status
Simulation time 9067316704 ps
CPU time 5.97 seconds
Started Mar 19 02:20:50 PM PDT 24
Finished Mar 19 02:20:57 PM PDT 24
Peak memory 223448 kb
Host smart-fe0753c9-613b-4324-a4b3-3e4189ed05e2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1072625670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dir
ect.1072625670
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.376274345
Short name T779
Test name
Test status
Simulation time 687036133 ps
CPU time 9.33 seconds
Started Mar 19 02:20:37 PM PDT 24
Finished Mar 19 02:20:46 PM PDT 24
Peak memory 216756 kb
Host smart-d286cb33-f236-409e-b82e-97088c83fc4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376274345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.376274345
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.997931968
Short name T383
Test name
Test status
Simulation time 6798726883 ps
CPU time 11.26 seconds
Started Mar 19 02:20:38 PM PDT 24
Finished Mar 19 02:20:50 PM PDT 24
Peak memory 216744 kb
Host smart-53f15555-076c-46ef-a6b8-f202b8efdb64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997931968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.997931968
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.3243178666
Short name T412
Test name
Test status
Simulation time 60704180 ps
CPU time 3.48 seconds
Started Mar 19 02:20:36 PM PDT 24
Finished Mar 19 02:20:40 PM PDT 24
Peak memory 216684 kb
Host smart-a9b16c02-fec1-402b-b827-cd55b26d604e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243178666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.3243178666
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.92460911
Short name T367
Test name
Test status
Simulation time 40411712 ps
CPU time 0.85 seconds
Started Mar 19 02:20:35 PM PDT 24
Finished Mar 19 02:20:36 PM PDT 24
Peak memory 206936 kb
Host smart-18bd14be-99c8-4b25-bbf3-f3c030622f06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92460911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.92460911
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.1462021897
Short name T314
Test name
Test status
Simulation time 2026675761 ps
CPU time 7.72 seconds
Started Mar 19 02:20:34 PM PDT 24
Finished Mar 19 02:20:42 PM PDT 24
Peak memory 219076 kb
Host smart-0be50504-b7d0-4ecf-bc76-4ac152144c4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1462021897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.1462021897
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.1879879088
Short name T645
Test name
Test status
Simulation time 13676119 ps
CPU time 0.71 seconds
Started Mar 19 02:20:49 PM PDT 24
Finished Mar 19 02:20:50 PM PDT 24
Peak memory 205064 kb
Host smart-c8c58927-56d8-4f6f-b734-4532ca761b4b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879879088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
1879879088
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.3936170537
Short name T384
Test name
Test status
Simulation time 56455204 ps
CPU time 2.63 seconds
Started Mar 19 02:20:46 PM PDT 24
Finished Mar 19 02:20:49 PM PDT 24
Peak memory 234156 kb
Host smart-2415e2d2-2727-4ce7-8062-0d078c68b206
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936170537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.3936170537
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.1751706140
Short name T371
Test name
Test status
Simulation time 49694466 ps
CPU time 0.82 seconds
Started Mar 19 02:20:48 PM PDT 24
Finished Mar 19 02:20:50 PM PDT 24
Peak memory 205704 kb
Host smart-dde5d8bb-3b2c-4980-abf7-03b132a7d81f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751706140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.1751706140
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.3930381862
Short name T169
Test name
Test status
Simulation time 41363098823 ps
CPU time 206.07 seconds
Started Mar 19 02:20:47 PM PDT 24
Finished Mar 19 02:24:14 PM PDT 24
Peak memory 257036 kb
Host smart-e75b9cda-be40-487f-940b-00583926af61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930381862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.3930381862
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.2489319981
Short name T243
Test name
Test status
Simulation time 10630896685 ps
CPU time 57.81 seconds
Started Mar 19 02:20:47 PM PDT 24
Finished Mar 19 02:21:45 PM PDT 24
Peak memory 249624 kb
Host smart-8883fdeb-f8d6-4975-b589-af6744e86fde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2489319981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.2489319981
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.2686309402
Short name T211
Test name
Test status
Simulation time 4709027397 ps
CPU time 60.85 seconds
Started Mar 19 02:20:47 PM PDT 24
Finished Mar 19 02:21:48 PM PDT 24
Peak memory 240264 kb
Host smart-c4d06809-fa94-4b3e-87b5-9ac496f8772d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2686309402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idl
e.2686309402
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.2615334665
Short name T909
Test name
Test status
Simulation time 22562014014 ps
CPU time 61.52 seconds
Started Mar 19 02:20:47 PM PDT 24
Finished Mar 19 02:21:49 PM PDT 24
Peak memory 241436 kb
Host smart-ae582de1-ff9a-4105-a0d9-cb304bb6e9f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2615334665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.2615334665
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_intercept.2183038218
Short name T30
Test name
Test status
Simulation time 1446134498 ps
CPU time 5.73 seconds
Started Mar 19 02:20:47 PM PDT 24
Finished Mar 19 02:20:53 PM PDT 24
Peak memory 235884 kb
Host smart-ae57eb6b-62d8-4353-8374-65f021bd8f5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2183038218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.2183038218
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.2065996234
Short name T678
Test name
Test status
Simulation time 21572891628 ps
CPU time 54.35 seconds
Started Mar 19 02:20:48 PM PDT 24
Finished Mar 19 02:21:44 PM PDT 24
Peak memory 234220 kb
Host smart-ccaab1cf-c5d2-42c1-8b74-3a102f1d2b61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065996234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.2065996234
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.131178178
Short name T985
Test name
Test status
Simulation time 704878303 ps
CPU time 7.31 seconds
Started Mar 19 02:20:47 PM PDT 24
Finished Mar 19 02:20:55 PM PDT 24
Peak memory 237228 kb
Host smart-bce22ada-c318-4f4a-86b8-cef12aef0589
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=131178178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swap
.131178178
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.623004842
Short name T406
Test name
Test status
Simulation time 8916289505 ps
CPU time 22.15 seconds
Started Mar 19 02:20:48 PM PDT 24
Finished Mar 19 02:21:10 PM PDT 24
Peak memory 218208 kb
Host smart-a379d570-cf3d-44fd-bfe2-291d778ff16a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=623004842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.623004842
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.1195865536
Short name T3
Test name
Test status
Simulation time 108849036 ps
CPU time 3.87 seconds
Started Mar 19 02:20:47 PM PDT 24
Finished Mar 19 02:20:52 PM PDT 24
Peak memory 222796 kb
Host smart-7d103265-681d-477a-93e7-a9d99889603d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1195865536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dir
ect.1195865536
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.1087148381
Short name T351
Test name
Test status
Simulation time 74821823 ps
CPU time 1.02 seconds
Started Mar 19 02:20:48 PM PDT 24
Finished Mar 19 02:20:49 PM PDT 24
Peak memory 207008 kb
Host smart-e72463b6-509d-4c4f-ab9a-8326756838aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087148381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stre
ss_all.1087148381
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.3180627845
Short name T443
Test name
Test status
Simulation time 15880689094 ps
CPU time 41.8 seconds
Started Mar 19 02:20:48 PM PDT 24
Finished Mar 19 02:21:31 PM PDT 24
Peak memory 216744 kb
Host smart-d8ee4ae6-8340-470d-bdb9-b585acf7ee8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3180627845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.3180627845
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.241011322
Short name T310
Test name
Test status
Simulation time 352486313 ps
CPU time 1.83 seconds
Started Mar 19 02:20:49 PM PDT 24
Finished Mar 19 02:20:51 PM PDT 24
Peak memory 208228 kb
Host smart-ba72b186-da26-47a1-be5d-992944144c99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=241011322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.241011322
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.2935687765
Short name T885
Test name
Test status
Simulation time 421120800 ps
CPU time 4.6 seconds
Started Mar 19 02:20:51 PM PDT 24
Finished Mar 19 02:20:56 PM PDT 24
Peak memory 216756 kb
Host smart-3f512bf1-9118-4678-b5e5-e6bd7717b178
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2935687765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.2935687765
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.2763973622
Short name T941
Test name
Test status
Simulation time 310361756 ps
CPU time 0.83 seconds
Started Mar 19 02:20:48 PM PDT 24
Finished Mar 19 02:20:50 PM PDT 24
Peak memory 205908 kb
Host smart-7af166cc-52a2-4b5e-bc93-007f4efb0205
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2763973622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.2763973622
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.3934271802
Short name T712
Test name
Test status
Simulation time 819247294 ps
CPU time 4.05 seconds
Started Mar 19 02:20:49 PM PDT 24
Finished Mar 19 02:20:54 PM PDT 24
Peak memory 234428 kb
Host smart-005912ac-2cad-48a0-b2fb-0297cfb65677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3934271802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.3934271802
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.392487133
Short name T832
Test name
Test status
Simulation time 39094295 ps
CPU time 0.72 seconds
Started Mar 19 02:21:09 PM PDT 24
Finished Mar 19 02:21:09 PM PDT 24
Peak memory 206004 kb
Host smart-7ed88e06-3031-44a0-ad2f-cb617a358910
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392487133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.392487133
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.2185790880
Short name T702
Test name
Test status
Simulation time 268574361 ps
CPU time 2.59 seconds
Started Mar 19 02:20:47 PM PDT 24
Finished Mar 19 02:20:50 PM PDT 24
Peak memory 233576 kb
Host smart-ae218f3d-cc98-40b0-9c4d-0aeca8cef688
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2185790880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.2185790880
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.2935314796
Short name T301
Test name
Test status
Simulation time 143330221 ps
CPU time 0.8 seconds
Started Mar 19 02:20:49 PM PDT 24
Finished Mar 19 02:20:50 PM PDT 24
Peak memory 207012 kb
Host smart-c1b47af5-d4f8-41ab-9288-5bde93a43c8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2935314796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.2935314796
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.3072906723
Short name T818
Test name
Test status
Simulation time 27062368275 ps
CPU time 148.94 seconds
Started Mar 19 02:21:01 PM PDT 24
Finished Mar 19 02:23:30 PM PDT 24
Peak memory 249648 kb
Host smart-41f5b291-bd92-4086-b478-82b2a401db86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3072906723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.3072906723
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.3564729829
Short name T143
Test name
Test status
Simulation time 26675148210 ps
CPU time 68 seconds
Started Mar 19 02:20:49 PM PDT 24
Finished Mar 19 02:21:57 PM PDT 24
Peak memory 241360 kb
Host smart-b18bb6bc-ccc7-4dab-ad10-bd50236df568
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3564729829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.3564729829
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_intercept.3500587898
Short name T861
Test name
Test status
Simulation time 3180766322 ps
CPU time 12.51 seconds
Started Mar 19 02:20:48 PM PDT 24
Finished Mar 19 02:21:02 PM PDT 24
Peak memory 233704 kb
Host smart-0d4aa09a-981a-4b60-9be6-db0319367ff1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3500587898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.3500587898
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.383539041
Short name T428
Test name
Test status
Simulation time 3234884093 ps
CPU time 16.04 seconds
Started Mar 19 02:20:48 PM PDT 24
Finished Mar 19 02:21:04 PM PDT 24
Peak memory 241360 kb
Host smart-dc8429cc-2339-436a-8aba-ad656bb0abae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383539041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.383539041
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.2085823975
Short name T810
Test name
Test status
Simulation time 3525045565 ps
CPU time 6.72 seconds
Started Mar 19 02:20:51 PM PDT 24
Finished Mar 19 02:20:58 PM PDT 24
Peak memory 237848 kb
Host smart-f4461429-08a6-413d-a205-ca91bd055e42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2085823975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swa
p.2085823975
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.695550565
Short name T514
Test name
Test status
Simulation time 2361173519 ps
CPU time 9.39 seconds
Started Mar 19 02:20:47 PM PDT 24
Finished Mar 19 02:20:56 PM PDT 24
Peak memory 238600 kb
Host smart-183dbf9e-68df-407b-a2ed-dcfce30626a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=695550565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.695550565
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.1190897991
Short name T632
Test name
Test status
Simulation time 75340795 ps
CPU time 3.92 seconds
Started Mar 19 02:21:01 PM PDT 24
Finished Mar 19 02:21:06 PM PDT 24
Peak memory 223224 kb
Host smart-dd5e00c5-c99d-4fa8-9801-de008eabebce
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1190897991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dir
ect.1190897991
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.1021683275
Short name T197
Test name
Test status
Simulation time 36932467084 ps
CPU time 84.04 seconds
Started Mar 19 02:21:03 PM PDT 24
Finished Mar 19 02:22:27 PM PDT 24
Peak memory 265536 kb
Host smart-588d1f4a-0efd-4262-9785-20971b0450c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021683275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stre
ss_all.1021683275
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.543740101
Short name T970
Test name
Test status
Simulation time 2287066251 ps
CPU time 19.09 seconds
Started Mar 19 02:20:51 PM PDT 24
Finished Mar 19 02:21:10 PM PDT 24
Peak memory 216776 kb
Host smart-035e2f81-e9bf-42fe-88f5-01b10f2671a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=543740101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.543740101
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.3452667154
Short name T560
Test name
Test status
Simulation time 11325561816 ps
CPU time 6.08 seconds
Started Mar 19 02:20:51 PM PDT 24
Finished Mar 19 02:20:57 PM PDT 24
Peak memory 216792 kb
Host smart-718943e4-dd67-4de2-9ae0-b26641a6a5ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3452667154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.3452667154
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.379913944
Short name T391
Test name
Test status
Simulation time 286104665 ps
CPU time 1.9 seconds
Started Mar 19 02:20:48 PM PDT 24
Finished Mar 19 02:20:51 PM PDT 24
Peak memory 216696 kb
Host smart-cdba44a2-f7e3-4bbd-9d99-9fdc3b9de6bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379913944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.379913944
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.2147216431
Short name T637
Test name
Test status
Simulation time 130942734 ps
CPU time 0.85 seconds
Started Mar 19 02:20:45 PM PDT 24
Finished Mar 19 02:20:46 PM PDT 24
Peak memory 205888 kb
Host smart-f66bde0b-ebb9-48c7-a662-b5c491036ab1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2147216431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.2147216431
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.121465571
Short name T745
Test name
Test status
Simulation time 114203606 ps
CPU time 2.47 seconds
Started Mar 19 02:20:48 PM PDT 24
Finished Mar 19 02:20:51 PM PDT 24
Peak memory 216660 kb
Host smart-23b438f5-d378-4e98-a767-6fbb0ff65461
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=121465571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.121465571
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.2592351595
Short name T291
Test name
Test status
Simulation time 16176293 ps
CPU time 0.77 seconds
Started Mar 19 02:21:03 PM PDT 24
Finished Mar 19 02:21:04 PM PDT 24
Peak memory 205640 kb
Host smart-e1815162-3e7b-4079-a189-3070594a151f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592351595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.
2592351595
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.67310810
Short name T45
Test name
Test status
Simulation time 316922921 ps
CPU time 2.39 seconds
Started Mar 19 02:21:04 PM PDT 24
Finished Mar 19 02:21:08 PM PDT 24
Peak memory 217148 kb
Host smart-bacf55ed-e790-417d-8648-aa81ff2b2e6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67310810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.67310810
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.4139028514
Short name T485
Test name
Test status
Simulation time 154240613 ps
CPU time 0.84 seconds
Started Mar 19 02:21:02 PM PDT 24
Finished Mar 19 02:21:03 PM PDT 24
Peak memory 207080 kb
Host smart-e3e2de26-a1d8-4443-b1bd-2925e2c44718
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4139028514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.4139028514
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.3265839765
Short name T452
Test name
Test status
Simulation time 18266503060 ps
CPU time 29.42 seconds
Started Mar 19 02:21:02 PM PDT 24
Finished Mar 19 02:21:32 PM PDT 24
Peak memory 241444 kb
Host smart-8e0241ea-d395-4fb2-9278-800387d82867
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265839765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.3265839765
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.2023652699
Short name T258
Test name
Test status
Simulation time 30740372685 ps
CPU time 213.58 seconds
Started Mar 19 02:21:01 PM PDT 24
Finished Mar 19 02:24:34 PM PDT 24
Peak memory 256324 kb
Host smart-6bc7ac40-eb90-4b1f-8b1d-33f709e63e2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023652699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.2023652699
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.2798338157
Short name T236
Test name
Test status
Simulation time 45694675129 ps
CPU time 277.69 seconds
Started Mar 19 02:21:03 PM PDT 24
Finished Mar 19 02:25:41 PM PDT 24
Peak memory 272908 kb
Host smart-12af1a73-d073-45a2-9239-c64d158582c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2798338157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idl
e.2798338157
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_intercept.3105481994
Short name T891
Test name
Test status
Simulation time 1918495657 ps
CPU time 7.89 seconds
Started Mar 19 02:21:01 PM PDT 24
Finished Mar 19 02:21:09 PM PDT 24
Peak memory 217724 kb
Host smart-cf72e8d5-6382-4f2d-baba-20ca91507cc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3105481994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.3105481994
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.2040817786
Short name T781
Test name
Test status
Simulation time 10169648196 ps
CPU time 13.02 seconds
Started Mar 19 02:21:08 PM PDT 24
Finished Mar 19 02:21:22 PM PDT 24
Peak memory 233212 kb
Host smart-5b29cbfc-dd70-4fb5-a310-c42f4219aba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040817786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.2040817786
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.2131996113
Short name T475
Test name
Test status
Simulation time 278872192 ps
CPU time 2.99 seconds
Started Mar 19 02:21:03 PM PDT 24
Finished Mar 19 02:21:06 PM PDT 24
Peak memory 234196 kb
Host smart-b8103f28-f708-4b4e-89c6-f73149d9f2fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2131996113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swa
p.2131996113
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.3971700353
Short name T484
Test name
Test status
Simulation time 12109625042 ps
CPU time 17.51 seconds
Started Mar 19 02:21:01 PM PDT 24
Finished Mar 19 02:21:19 PM PDT 24
Peak memory 237580 kb
Host smart-9b07cebf-26cc-42ff-a7a6-99eb7d9167ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3971700353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.3971700353
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.2348623295
Short name T884
Test name
Test status
Simulation time 722313876 ps
CPU time 4.91 seconds
Started Mar 19 02:21:02 PM PDT 24
Finished Mar 19 02:21:07 PM PDT 24
Peak memory 219660 kb
Host smart-8dd79721-6b1c-4a66-b68d-374fa461507a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2348623295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dir
ect.2348623295
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.3921833959
Short name T905
Test name
Test status
Simulation time 24261462377 ps
CPU time 154.29 seconds
Started Mar 19 02:21:03 PM PDT 24
Finished Mar 19 02:23:38 PM PDT 24
Peak memory 256396 kb
Host smart-2cfb7045-cfed-49d4-8892-625859637ce4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921833959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stre
ss_all.3921833959
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.358107767
Short name T840
Test name
Test status
Simulation time 8348470274 ps
CPU time 15.64 seconds
Started Mar 19 02:21:01 PM PDT 24
Finished Mar 19 02:21:17 PM PDT 24
Peak memory 216780 kb
Host smart-8a82a707-9db9-44aa-aa71-105312eba9b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=358107767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.358107767
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.1054563702
Short name T894
Test name
Test status
Simulation time 4082922802 ps
CPU time 12.42 seconds
Started Mar 19 02:21:00 PM PDT 24
Finished Mar 19 02:21:12 PM PDT 24
Peak memory 216664 kb
Host smart-06fb45ce-900e-4324-b785-d62b94ba316f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1054563702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.1054563702
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.3302335807
Short name T294
Test name
Test status
Simulation time 3329457367 ps
CPU time 4.5 seconds
Started Mar 19 02:21:02 PM PDT 24
Finished Mar 19 02:21:07 PM PDT 24
Peak memory 218628 kb
Host smart-ad07931e-13e5-4f72-b565-863c6313435f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302335807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.3302335807
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.645455197
Short name T416
Test name
Test status
Simulation time 307947795 ps
CPU time 1.06 seconds
Started Mar 19 02:21:03 PM PDT 24
Finished Mar 19 02:21:05 PM PDT 24
Peak memory 206936 kb
Host smart-7acf3acd-3153-4acc-9fa2-55e0edb78d59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645455197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.645455197
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.2564983508
Short name T388
Test name
Test status
Simulation time 2587667740 ps
CPU time 4.96 seconds
Started Mar 19 02:21:01 PM PDT 24
Finished Mar 19 02:21:06 PM PDT 24
Peak memory 234680 kb
Host smart-144a5f5d-ab1a-4ee7-bda2-af01a5930b91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564983508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.2564983508
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.237972097
Short name T980
Test name
Test status
Simulation time 22375090 ps
CPU time 0.75 seconds
Started Mar 19 02:21:19 PM PDT 24
Finished Mar 19 02:21:20 PM PDT 24
Peak memory 206020 kb
Host smart-60738395-e7e2-4ee4-bb93-f41ab0073302
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237972097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.237972097
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.2694515690
Short name T229
Test name
Test status
Simulation time 2292752826 ps
CPU time 4.14 seconds
Started Mar 19 02:21:03 PM PDT 24
Finished Mar 19 02:21:08 PM PDT 24
Peak memory 221020 kb
Host smart-c55f2ce6-2869-4968-9681-2a0a30fed999
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2694515690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.2694515690
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.372906670
Short name T287
Test name
Test status
Simulation time 15637348 ps
CPU time 0.75 seconds
Started Mar 19 02:21:08 PM PDT 24
Finished Mar 19 02:21:09 PM PDT 24
Peak memory 205984 kb
Host smart-96b43f07-35cf-4e6e-a8d1-539ce35497ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372906670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.372906670
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.3839382919
Short name T912
Test name
Test status
Simulation time 62351386656 ps
CPU time 39.1 seconds
Started Mar 19 02:21:11 PM PDT 24
Finished Mar 19 02:21:50 PM PDT 24
Peak memory 245552 kb
Host smart-a863a92e-f171-41c6-83e0-47b9863d53aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3839382919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.3839382919
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.10981368
Short name T917
Test name
Test status
Simulation time 133019264551 ps
CPU time 193.4 seconds
Started Mar 19 02:21:10 PM PDT 24
Finished Mar 19 02:24:23 PM PDT 24
Peak memory 256368 kb
Host smart-c5404cc3-e840-4ed2-be71-054e1d233145
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10981368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.10981368
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.3674398777
Short name T602
Test name
Test status
Simulation time 4929645759 ps
CPU time 30.61 seconds
Started Mar 19 02:21:13 PM PDT 24
Finished Mar 19 02:21:44 PM PDT 24
Peak memory 233620 kb
Host smart-3c092d5c-bf38-48d7-a1b5-f983a7727ba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3674398777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idl
e.3674398777
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.2086195697
Short name T552
Test name
Test status
Simulation time 45254494062 ps
CPU time 32.78 seconds
Started Mar 19 02:21:00 PM PDT 24
Finished Mar 19 02:21:33 PM PDT 24
Peak memory 250960 kb
Host smart-3a4d5560-994a-4ae8-b999-11c1b0ee74c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2086195697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.2086195697
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_intercept.2520180074
Short name T491
Test name
Test status
Simulation time 788960241 ps
CPU time 3.3 seconds
Started Mar 19 02:21:00 PM PDT 24
Finished Mar 19 02:21:03 PM PDT 24
Peak memory 218244 kb
Host smart-f23dc528-6598-4865-8d0e-7b13dab82602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2520180074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.2520180074
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.2927636961
Short name T821
Test name
Test status
Simulation time 3602750277 ps
CPU time 13.15 seconds
Started Mar 19 02:21:04 PM PDT 24
Finished Mar 19 02:21:18 PM PDT 24
Peak memory 236728 kb
Host smart-3432be1d-620c-4a47-b5a0-989c7204a51b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927636961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.2927636961
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.3726555258
Short name T235
Test name
Test status
Simulation time 2342321403 ps
CPU time 5.21 seconds
Started Mar 19 02:21:00 PM PDT 24
Finished Mar 19 02:21:05 PM PDT 24
Peak memory 225084 kb
Host smart-00596d10-7966-4537-a2b9-add81326f4ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3726555258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swa
p.3726555258
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.3264320960
Short name T228
Test name
Test status
Simulation time 26838757349 ps
CPU time 20.43 seconds
Started Mar 19 02:21:01 PM PDT 24
Finished Mar 19 02:21:21 PM PDT 24
Peak memory 235696 kb
Host smart-66ae42b1-65a9-4238-bf94-0d591bde6b65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3264320960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.3264320960
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.712229509
Short name T839
Test name
Test status
Simulation time 2497587760 ps
CPU time 6.02 seconds
Started Mar 19 02:21:00 PM PDT 24
Finished Mar 19 02:21:06 PM PDT 24
Peak memory 220564 kb
Host smart-b427898e-8b1e-40e2-9ed2-dfe965fe0765
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=712229509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dire
ct.712229509
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.639451832
Short name T161
Test name
Test status
Simulation time 4246908811 ps
CPU time 64.88 seconds
Started Mar 19 02:21:12 PM PDT 24
Finished Mar 19 02:22:17 PM PDT 24
Peak memory 249712 kb
Host smart-2e14be5b-7750-42cd-a00c-2afea30e84df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639451832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stres
s_all.639451832
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.3077369649
Short name T285
Test name
Test status
Simulation time 17142420661 ps
CPU time 90.05 seconds
Started Mar 19 02:21:01 PM PDT 24
Finished Mar 19 02:22:31 PM PDT 24
Peak memory 216856 kb
Host smart-267267b7-4c0c-4d28-a672-f31db407ebd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3077369649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.3077369649
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.1556925113
Short name T506
Test name
Test status
Simulation time 1187694345 ps
CPU time 6.25 seconds
Started Mar 19 02:20:59 PM PDT 24
Finished Mar 19 02:21:06 PM PDT 24
Peak memory 216576 kb
Host smart-3fc07a18-9863-4ed2-9b77-c15f7063adf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556925113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.1556925113
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.749242654
Short name T634
Test name
Test status
Simulation time 202106423 ps
CPU time 4.09 seconds
Started Mar 19 02:21:08 PM PDT 24
Finished Mar 19 02:21:13 PM PDT 24
Peak memory 218304 kb
Host smart-f034e3fb-c424-4c30-80e1-9ce64990f916
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=749242654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.749242654
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.193971784
Short name T913
Test name
Test status
Simulation time 33006063 ps
CPU time 0.81 seconds
Started Mar 19 02:21:01 PM PDT 24
Finished Mar 19 02:21:02 PM PDT 24
Peak memory 205852 kb
Host smart-552a4aa2-9afa-4074-b689-22312a4d1157
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=193971784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.193971784
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.459153899
Short name T438
Test name
Test status
Simulation time 15320148554 ps
CPU time 44.86 seconds
Started Mar 19 02:20:59 PM PDT 24
Finished Mar 19 02:21:44 PM PDT 24
Peak memory 255320 kb
Host smart-deecd5ae-3734-4fd6-a92a-39e30cf0bdd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459153899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.459153899
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.3986812178
Short name T643
Test name
Test status
Simulation time 49175095 ps
CPU time 0.73 seconds
Started Mar 19 02:21:18 PM PDT 24
Finished Mar 19 02:21:18 PM PDT 24
Peak memory 205068 kb
Host smart-4c02d5c2-bfa7-49b4-9068-171716e2f02b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986812178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.
3986812178
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.482502675
Short name T774
Test name
Test status
Simulation time 161179144 ps
CPU time 2.5 seconds
Started Mar 19 02:21:09 PM PDT 24
Finished Mar 19 02:21:12 PM PDT 24
Peak memory 218796 kb
Host smart-dcf3847d-93e0-4aa9-91b4-aee0cf8f3ea2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=482502675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.482502675
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.4029165235
Short name T942
Test name
Test status
Simulation time 57650110 ps
CPU time 0.8 seconds
Started Mar 19 02:21:13 PM PDT 24
Finished Mar 19 02:21:14 PM PDT 24
Peak memory 205712 kb
Host smart-e54edbb6-164e-4b31-bb75-5f12b80330b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4029165235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.4029165235
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.4142427173
Short name T422
Test name
Test status
Simulation time 10051374538 ps
CPU time 56.93 seconds
Started Mar 19 02:21:10 PM PDT 24
Finished Mar 19 02:22:08 PM PDT 24
Peak memory 235288 kb
Host smart-32370267-7821-4b2d-8610-1e220fef9f1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4142427173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.4142427173
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.3489529417
Short name T743
Test name
Test status
Simulation time 126929712735 ps
CPU time 248.95 seconds
Started Mar 19 02:21:17 PM PDT 24
Finished Mar 19 02:25:26 PM PDT 24
Peak memory 256856 kb
Host smart-be13ec60-3093-4abd-b5fc-cd2b0d72b029
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3489529417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.3489529417
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.356914591
Short name T22
Test name
Test status
Simulation time 58955605068 ps
CPU time 223.01 seconds
Started Mar 19 02:21:12 PM PDT 24
Finished Mar 19 02:24:55 PM PDT 24
Peak memory 250944 kb
Host smart-4c6f47e6-f7c2-4683-8588-9476f223043b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=356914591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idle
.356914591
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.2907717327
Short name T771
Test name
Test status
Simulation time 10470200324 ps
CPU time 60.82 seconds
Started Mar 19 02:21:18 PM PDT 24
Finished Mar 19 02:22:19 PM PDT 24
Peak memory 241468 kb
Host smart-a7ed8a40-5560-4799-9801-5bf335b528fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2907717327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.2907717327
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_intercept.1348662684
Short name T227
Test name
Test status
Simulation time 827170570 ps
CPU time 4.74 seconds
Started Mar 19 02:21:12 PM PDT 24
Finished Mar 19 02:21:17 PM PDT 24
Peak memory 233612 kb
Host smart-e0f67c39-ab91-431a-86cb-c4fb20ce8827
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1348662684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.1348662684
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.3993673907
Short name T918
Test name
Test status
Simulation time 10395115655 ps
CPU time 13.08 seconds
Started Mar 19 02:21:09 PM PDT 24
Finished Mar 19 02:21:22 PM PDT 24
Peak memory 227664 kb
Host smart-a0f821c2-c040-4007-9f6a-757a8945d1f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3993673907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.3993673907
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.340491335
Short name T413
Test name
Test status
Simulation time 14316579651 ps
CPU time 17.75 seconds
Started Mar 19 02:21:13 PM PDT 24
Finished Mar 19 02:21:31 PM PDT 24
Peak memory 239244 kb
Host smart-0fc4e639-53a1-4217-8948-516ce3e5f32b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=340491335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swap
.340491335
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.3997827731
Short name T752
Test name
Test status
Simulation time 55391572597 ps
CPU time 31.48 seconds
Started Mar 19 02:21:11 PM PDT 24
Finished Mar 19 02:21:43 PM PDT 24
Peak memory 232308 kb
Host smart-e72f58e0-f213-4417-a901-562d57c364b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3997827731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.3997827731
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.2532756095
Short name T458
Test name
Test status
Simulation time 314817987 ps
CPU time 3.35 seconds
Started Mar 19 02:21:11 PM PDT 24
Finished Mar 19 02:21:14 PM PDT 24
Peak memory 222804 kb
Host smart-254514b8-72f3-4eb6-a3e9-fae6a3123268
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2532756095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dir
ect.2532756095
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.1455622694
Short name T419
Test name
Test status
Simulation time 265210759574 ps
CPU time 473.83 seconds
Started Mar 19 02:21:11 PM PDT 24
Finished Mar 19 02:29:05 PM PDT 24
Peak memory 257864 kb
Host smart-08a66d72-913d-42c3-9937-a1dd9dbb1668
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455622694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stre
ss_all.1455622694
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.2200680264
Short name T375
Test name
Test status
Simulation time 26849884453 ps
CPU time 40.19 seconds
Started Mar 19 02:21:13 PM PDT 24
Finished Mar 19 02:21:53 PM PDT 24
Peak memory 216808 kb
Host smart-a3057766-3e17-44dd-9ad2-9841169820a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2200680264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.2200680264
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.109054023
Short name T844
Test name
Test status
Simulation time 6039524932 ps
CPU time 19.33 seconds
Started Mar 19 02:21:11 PM PDT 24
Finished Mar 19 02:21:30 PM PDT 24
Peak memory 216768 kb
Host smart-7a2a0e7e-e5d5-4af4-8a1a-055d585ec5de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109054023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.109054023
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.3167352549
Short name T504
Test name
Test status
Simulation time 90861217 ps
CPU time 0.98 seconds
Started Mar 19 02:21:12 PM PDT 24
Finished Mar 19 02:21:14 PM PDT 24
Peak memory 207340 kb
Host smart-bcf6e74c-98f8-4fb3-8235-8eadac38c8a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3167352549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.3167352549
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.3322085565
Short name T308
Test name
Test status
Simulation time 49865746 ps
CPU time 0.89 seconds
Started Mar 19 02:21:17 PM PDT 24
Finished Mar 19 02:21:18 PM PDT 24
Peak memory 206384 kb
Host smart-72ad1a71-3e94-4427-8644-3272f5fbf12a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3322085565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.3322085565
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.2072571566
Short name T569
Test name
Test status
Simulation time 1503633992 ps
CPU time 11.66 seconds
Started Mar 19 02:21:18 PM PDT 24
Finished Mar 19 02:21:30 PM PDT 24
Peak memory 219220 kb
Host smart-98d28d87-f8f8-4e03-80ea-889399c59fa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2072571566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.2072571566
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.636340770
Short name T298
Test name
Test status
Simulation time 13218695 ps
CPU time 0.7 seconds
Started Mar 19 02:21:20 PM PDT 24
Finished Mar 19 02:21:22 PM PDT 24
Peak memory 205632 kb
Host smart-b17c1872-8609-44f3-b508-abc97e2de8ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636340770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.636340770
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.2905884717
Short name T349
Test name
Test status
Simulation time 877104432 ps
CPU time 3.81 seconds
Started Mar 19 02:21:20 PM PDT 24
Finished Mar 19 02:21:25 PM PDT 24
Peak memory 224844 kb
Host smart-f270b2f1-729d-462e-a12b-67c9aeace097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2905884717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.2905884717
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.667405129
Short name T974
Test name
Test status
Simulation time 51870980 ps
CPU time 0.79 seconds
Started Mar 19 02:21:11 PM PDT 24
Finished Mar 19 02:21:12 PM PDT 24
Peak memory 207024 kb
Host smart-28380a71-ba94-40a1-ba74-6a8b41e69f53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=667405129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.667405129
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.3924565018
Short name T803
Test name
Test status
Simulation time 64726790616 ps
CPU time 131.9 seconds
Started Mar 19 02:21:19 PM PDT 24
Finished Mar 19 02:23:31 PM PDT 24
Peak memory 257004 kb
Host smart-e1326d44-b40f-46e2-b2e8-dfdb976314f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3924565018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.3924565018
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.2202123069
Short name T65
Test name
Test status
Simulation time 17747994679 ps
CPU time 64.28 seconds
Started Mar 19 02:21:19 PM PDT 24
Finished Mar 19 02:22:24 PM PDT 24
Peak memory 241836 kb
Host smart-640e4d9b-be94-4b88-9e63-569f7d96815c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2202123069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.2202123069
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.2374577269
Short name T254
Test name
Test status
Simulation time 35298892729 ps
CPU time 265.58 seconds
Started Mar 19 02:21:19 PM PDT 24
Finished Mar 19 02:25:45 PM PDT 24
Peak memory 256716 kb
Host smart-6f9bb6e0-719c-4673-bfca-57c60dea0bb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2374577269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idl
e.2374577269
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.867839292
Short name T62
Test name
Test status
Simulation time 923818037 ps
CPU time 15.47 seconds
Started Mar 19 02:21:22 PM PDT 24
Finished Mar 19 02:21:38 PM PDT 24
Peak memory 232036 kb
Host smart-f798f1a9-2d42-4904-8f7d-569ef4755620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=867839292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.867839292
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_intercept.66304783
Short name T547
Test name
Test status
Simulation time 7376811876 ps
CPU time 11.57 seconds
Started Mar 19 02:21:19 PM PDT 24
Finished Mar 19 02:21:31 PM PDT 24
Peak memory 219476 kb
Host smart-5a37c2f6-cb5b-4902-aa22-893d70aec0a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66304783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.66304783
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.1597551819
Short name T898
Test name
Test status
Simulation time 1127491595 ps
CPU time 4.97 seconds
Started Mar 19 02:21:20 PM PDT 24
Finished Mar 19 02:21:26 PM PDT 24
Peak memory 233640 kb
Host smart-c2c9b8ff-75f4-43d7-b659-3ef2a2c45528
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1597551819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.1597551819
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.3388866697
Short name T626
Test name
Test status
Simulation time 2063308442 ps
CPU time 7.59 seconds
Started Mar 19 02:21:19 PM PDT 24
Finished Mar 19 02:21:27 PM PDT 24
Peak memory 224884 kb
Host smart-068eef64-c920-4442-bfa2-c88eddc80bb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3388866697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swa
p.3388866697
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.3147694702
Short name T749
Test name
Test status
Simulation time 18111996381 ps
CPU time 15.71 seconds
Started Mar 19 02:21:20 PM PDT 24
Finished Mar 19 02:21:37 PM PDT 24
Peak memory 240412 kb
Host smart-dab5bedd-7b21-482c-8612-aa1e675d6242
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3147694702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.3147694702
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.1462229223
Short name T495
Test name
Test status
Simulation time 694386178 ps
CPU time 4.04 seconds
Started Mar 19 02:21:22 PM PDT 24
Finished Mar 19 02:21:26 PM PDT 24
Peak memory 223240 kb
Host smart-c8b340f3-c460-4d7e-bb79-2ab2fe9eda83
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1462229223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir
ect.1462229223
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.2795335337
Short name T907
Test name
Test status
Simulation time 199352431390 ps
CPU time 332.99 seconds
Started Mar 19 02:21:20 PM PDT 24
Finished Mar 19 02:26:54 PM PDT 24
Peak memory 257392 kb
Host smart-9442a34d-2f13-40f3-9891-f5ed22097d16
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795335337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stre
ss_all.2795335337
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.1164133102
Short name T17
Test name
Test status
Simulation time 4991364598 ps
CPU time 15.65 seconds
Started Mar 19 02:21:12 PM PDT 24
Finished Mar 19 02:21:28 PM PDT 24
Peak memory 216460 kb
Host smart-a73453ef-b439-4af0-8294-4ddd247f10c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1164133102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.1164133102
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.858339243
Short name T888
Test name
Test status
Simulation time 4130120403 ps
CPU time 14.39 seconds
Started Mar 19 02:21:12 PM PDT 24
Finished Mar 19 02:21:27 PM PDT 24
Peak memory 216740 kb
Host smart-47a8dec1-b170-4bdf-8a79-24eee6d228e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=858339243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.858339243
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.3393918386
Short name T935
Test name
Test status
Simulation time 90645515 ps
CPU time 1.11 seconds
Started Mar 19 02:21:19 PM PDT 24
Finished Mar 19 02:21:21 PM PDT 24
Peak memory 207012 kb
Host smart-342c6890-0b34-4108-b9a7-aa9d2ea11600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3393918386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.3393918386
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.345950049
Short name T758
Test name
Test status
Simulation time 275506342 ps
CPU time 0.98 seconds
Started Mar 19 02:21:19 PM PDT 24
Finished Mar 19 02:21:20 PM PDT 24
Peak memory 206940 kb
Host smart-1f478262-a1bd-49cc-855d-6a22f165a6c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345950049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.345950049
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.3238825453
Short name T168
Test name
Test status
Simulation time 1143880956 ps
CPU time 9.52 seconds
Started Mar 19 02:21:20 PM PDT 24
Finished Mar 19 02:21:31 PM PDT 24
Peak memory 230288 kb
Host smart-7231aaec-977a-480a-b421-b7e573924121
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3238825453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.3238825453
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.1109951508
Short name T765
Test name
Test status
Simulation time 13104129 ps
CPU time 0.71 seconds
Started Mar 19 02:21:32 PM PDT 24
Finished Mar 19 02:21:33 PM PDT 24
Peak memory 205608 kb
Host smart-25a5a00c-1aa7-4e1f-91bf-a35cee99ab01
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109951508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.
1109951508
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.1319081378
Short name T567
Test name
Test status
Simulation time 131804300 ps
CPU time 2.63 seconds
Started Mar 19 02:21:19 PM PDT 24
Finished Mar 19 02:21:22 PM PDT 24
Peak memory 224856 kb
Host smart-8e2f3290-7de5-472a-bfb3-4937b4ef6efd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1319081378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.1319081378
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.3691122322
Short name T66
Test name
Test status
Simulation time 81747848 ps
CPU time 0.85 seconds
Started Mar 19 02:21:20 PM PDT 24
Finished Mar 19 02:21:22 PM PDT 24
Peak memory 207080 kb
Host smart-28593144-4f7c-49fa-a60b-999fe685e1c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3691122322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.3691122322
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.1605887383
Short name T551
Test name
Test status
Simulation time 2035798966 ps
CPU time 10.23 seconds
Started Mar 19 02:21:37 PM PDT 24
Finished Mar 19 02:21:47 PM PDT 24
Peak memory 234204 kb
Host smart-c7540f1f-2a32-4067-8334-2550ffef6942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1605887383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.1605887383
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.2035733013
Short name T245
Test name
Test status
Simulation time 294289172641 ps
CPU time 605.65 seconds
Started Mar 19 02:21:33 PM PDT 24
Finished Mar 19 02:31:39 PM PDT 24
Peak memory 274324 kb
Host smart-617e9127-30e1-4b58-83ec-3fdbb8573048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035733013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.2035733013
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.567843849
Short name T253
Test name
Test status
Simulation time 15639496749 ps
CPU time 71.34 seconds
Started Mar 19 02:21:32 PM PDT 24
Finished Mar 19 02:22:43 PM PDT 24
Peak memory 256620 kb
Host smart-43b45f81-50cf-4ba1-990f-6cd38dfd51ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=567843849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idle
.567843849
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.758202775
Short name T688
Test name
Test status
Simulation time 13258211166 ps
CPU time 26.56 seconds
Started Mar 19 02:21:20 PM PDT 24
Finished Mar 19 02:21:48 PM PDT 24
Peak memory 238448 kb
Host smart-46feaeb0-8c0a-4e6d-b3de-910332bf5bb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=758202775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.758202775
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_intercept.2074351721
Short name T457
Test name
Test status
Simulation time 132053306 ps
CPU time 4 seconds
Started Mar 19 02:21:21 PM PDT 24
Finished Mar 19 02:21:26 PM PDT 24
Peak memory 234556 kb
Host smart-16f9c707-0a1d-4406-a515-f2e9cac58db5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2074351721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.2074351721
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.3806244844
Short name T720
Test name
Test status
Simulation time 1241926116 ps
CPU time 13.26 seconds
Started Mar 19 02:21:21 PM PDT 24
Finished Mar 19 02:21:35 PM PDT 24
Peak memory 237564 kb
Host smart-2cc129a0-f241-40e0-ac1d-64265677749e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806244844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.3806244844
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.2656010360
Short name T366
Test name
Test status
Simulation time 1438230984 ps
CPU time 7.51 seconds
Started Mar 19 02:21:20 PM PDT 24
Finished Mar 19 02:21:29 PM PDT 24
Peak memory 218264 kb
Host smart-6b2794ec-809d-4192-8cd2-069cc0208d16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2656010360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swa
p.2656010360
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.1133805172
Short name T407
Test name
Test status
Simulation time 40355248511 ps
CPU time 43.11 seconds
Started Mar 19 02:21:22 PM PDT 24
Finished Mar 19 02:22:05 PM PDT 24
Peak memory 234164 kb
Host smart-24db49f5-cc12-43db-8c04-9fbf5ee536d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1133805172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.1133805172
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.206833527
Short name T757
Test name
Test status
Simulation time 1005523399 ps
CPU time 5.95 seconds
Started Mar 19 02:21:20 PM PDT 24
Finished Mar 19 02:21:27 PM PDT 24
Peak memory 222128 kb
Host smart-8314e2f1-8b4e-4938-871c-34999b686bf3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=206833527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dire
ct.206833527
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.3106889218
Short name T463
Test name
Test status
Simulation time 5980126396 ps
CPU time 131.3 seconds
Started Mar 19 02:21:32 PM PDT 24
Finished Mar 19 02:23:43 PM PDT 24
Peak memory 269332 kb
Host smart-5e8b1e4b-dead-46dc-9b7a-36ede00a9358
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106889218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stre
ss_all.3106889218
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.2323561509
Short name T316
Test name
Test status
Simulation time 10823628981 ps
CPU time 22.3 seconds
Started Mar 19 02:21:20 PM PDT 24
Finished Mar 19 02:21:43 PM PDT 24
Peak memory 216796 kb
Host smart-1b08c981-8951-4145-8692-ac03315dfe5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2323561509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.2323561509
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.138922489
Short name T946
Test name
Test status
Simulation time 914220089 ps
CPU time 7.34 seconds
Started Mar 19 02:21:18 PM PDT 24
Finished Mar 19 02:21:25 PM PDT 24
Peak memory 216608 kb
Host smart-b68db6a5-f581-4c25-91bf-b4bce9651686
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=138922489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.138922489
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.2923123870
Short name T915
Test name
Test status
Simulation time 127976088 ps
CPU time 6.89 seconds
Started Mar 19 02:21:20 PM PDT 24
Finished Mar 19 02:21:28 PM PDT 24
Peak memory 216860 kb
Host smart-367f0b46-b2f2-47d1-b960-45ace60ed6d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2923123870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.2923123870
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.1944921846
Short name T831
Test name
Test status
Simulation time 78805798 ps
CPU time 1 seconds
Started Mar 19 02:21:20 PM PDT 24
Finished Mar 19 02:21:21 PM PDT 24
Peak memory 205904 kb
Host smart-30c8ce13-fd7a-42b0-a1aa-65cd75be5d0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1944921846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.1944921846
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.2410008760
Short name T207
Test name
Test status
Simulation time 740021399 ps
CPU time 8.94 seconds
Started Mar 19 02:21:19 PM PDT 24
Finished Mar 19 02:21:28 PM PDT 24
Peak memory 234676 kb
Host smart-f5da19fb-fda8-4794-9832-8cd215f9cfd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2410008760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.2410008760
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.736084377
Short name T921
Test name
Test status
Simulation time 13938480 ps
CPU time 0.76 seconds
Started Mar 19 02:21:32 PM PDT 24
Finished Mar 19 02:21:33 PM PDT 24
Peak memory 205668 kb
Host smart-48c54e02-90cb-4a97-9e4a-d7f3caf09227
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736084377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.736084377
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.2176015832
Short name T246
Test name
Test status
Simulation time 176363004 ps
CPU time 2.79 seconds
Started Mar 19 02:21:34 PM PDT 24
Finished Mar 19 02:21:37 PM PDT 24
Peak memory 235320 kb
Host smart-c73640b4-3421-4ec4-add8-65d6f9018a1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2176015832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.2176015832
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.658862176
Short name T834
Test name
Test status
Simulation time 14633885 ps
CPU time 0.8 seconds
Started Mar 19 02:21:34 PM PDT 24
Finished Mar 19 02:21:35 PM PDT 24
Peak memory 206724 kb
Host smart-23c69e27-4564-4f3c-9a5a-470fd9858516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658862176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.658862176
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.438633503
Short name T170
Test name
Test status
Simulation time 2829604550 ps
CPU time 50.86 seconds
Started Mar 19 02:21:32 PM PDT 24
Finished Mar 19 02:22:23 PM PDT 24
Peak memory 249660 kb
Host smart-e424d24d-c5a0-4424-b2e4-1b3c3e801c38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=438633503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.438633503
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.4144980035
Short name T37
Test name
Test status
Simulation time 13770436196 ps
CPU time 75.27 seconds
Started Mar 19 02:21:39 PM PDT 24
Finished Mar 19 02:22:55 PM PDT 24
Peak memory 250588 kb
Host smart-64d9e566-f7f3-4c50-bead-3f2c88b27128
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4144980035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idl
e.4144980035
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.1872109650
Short name T736
Test name
Test status
Simulation time 8710923997 ps
CPU time 45.94 seconds
Started Mar 19 02:21:33 PM PDT 24
Finished Mar 19 02:22:19 PM PDT 24
Peak memory 240428 kb
Host smart-5f6d1b6c-2c48-41bb-ba1a-c0c38802c8e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1872109650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.1872109650
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_intercept.4149796647
Short name T896
Test name
Test status
Simulation time 3084482862 ps
CPU time 10.9 seconds
Started Mar 19 02:21:33 PM PDT 24
Finished Mar 19 02:21:44 PM PDT 24
Peak memory 225008 kb
Host smart-724cdc48-6720-45e2-86eb-8cac3562a873
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4149796647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.4149796647
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.4111187633
Short name T4
Test name
Test status
Simulation time 9239768700 ps
CPU time 27.41 seconds
Started Mar 19 02:21:31 PM PDT 24
Finished Mar 19 02:21:59 PM PDT 24
Peak memory 218908 kb
Host smart-92ae2d26-fc78-4c95-896a-c027b42a6ae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4111187633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.4111187633
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.3926856181
Short name T614
Test name
Test status
Simulation time 3712092182 ps
CPU time 5.11 seconds
Started Mar 19 02:21:33 PM PDT 24
Finished Mar 19 02:21:39 PM PDT 24
Peak memory 234216 kb
Host smart-f3665673-9c54-4340-b8cc-388ac973f93e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3926856181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swa
p.3926856181
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.1481256113
Short name T877
Test name
Test status
Simulation time 2083411835 ps
CPU time 13.75 seconds
Started Mar 19 02:21:35 PM PDT 24
Finished Mar 19 02:21:49 PM PDT 24
Peak memory 233032 kb
Host smart-7714b953-5e03-45ff-ade9-6abbb0c29b70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1481256113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.1481256113
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.4027469318
Short name T900
Test name
Test status
Simulation time 8476112301 ps
CPU time 8.39 seconds
Started Mar 19 02:21:31 PM PDT 24
Finished Mar 19 02:21:40 PM PDT 24
Peak memory 220872 kb
Host smart-dac6cd16-831a-4b82-8956-51a8e56c7d43
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4027469318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dir
ect.4027469318
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.54510446
Short name T159
Test name
Test status
Simulation time 7346583667 ps
CPU time 67.81 seconds
Started Mar 19 02:21:32 PM PDT 24
Finished Mar 19 02:22:40 PM PDT 24
Peak memory 249728 kb
Host smart-d44d6c07-1d93-497d-96dc-2aa19f01c50a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54510446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stress
_all.54510446
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.1055834133
Short name T532
Test name
Test status
Simulation time 2284538378 ps
CPU time 14.91 seconds
Started Mar 19 02:21:33 PM PDT 24
Finished Mar 19 02:21:48 PM PDT 24
Peak memory 216876 kb
Host smart-0d2a1334-d5eb-46ac-8cb9-88ebd79e492c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1055834133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.1055834133
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.1242791238
Short name T303
Test name
Test status
Simulation time 5801060407 ps
CPU time 8.21 seconds
Started Mar 19 02:21:31 PM PDT 24
Finished Mar 19 02:21:40 PM PDT 24
Peak memory 216676 kb
Host smart-436bdfc6-2a13-4601-86a5-7c3330c1f9d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242791238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.1242791238
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.1258790598
Short name T513
Test name
Test status
Simulation time 21854118 ps
CPU time 0.96 seconds
Started Mar 19 02:21:32 PM PDT 24
Finished Mar 19 02:21:33 PM PDT 24
Peak memory 207012 kb
Host smart-01159d34-019e-48e5-9f10-3d401c3c192f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258790598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.1258790598
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.3660208391
Short name T719
Test name
Test status
Simulation time 91165643 ps
CPU time 0.97 seconds
Started Mar 19 02:21:33 PM PDT 24
Finished Mar 19 02:21:34 PM PDT 24
Peak memory 205888 kb
Host smart-749efc0d-248c-43bb-94be-1e0046f4f7d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3660208391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.3660208391
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.2735547437
Short name T108
Test name
Test status
Simulation time 2593531276 ps
CPU time 4.68 seconds
Started Mar 19 02:21:36 PM PDT 24
Finished Mar 19 02:21:41 PM PDT 24
Peak memory 233248 kb
Host smart-a9979233-ace5-47a8-b229-e936917b5346
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735547437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.2735547437
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.3056313801
Short name T879
Test name
Test status
Simulation time 36758452 ps
CPU time 0.73 seconds
Started Mar 19 02:15:10 PM PDT 24
Finished Mar 19 02:15:11 PM PDT 24
Peak memory 205656 kb
Host smart-8913302a-7979-4109-88eb-ff94d4bdbc89
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056313801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.3
056313801
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.4054581361
Short name T465
Test name
Test status
Simulation time 528991182 ps
CPU time 3.65 seconds
Started Mar 19 02:15:11 PM PDT 24
Finished Mar 19 02:15:15 PM PDT 24
Peak memory 218304 kb
Host smart-150aa942-bf1d-4a62-847e-d952cb3d08c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4054581361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.4054581361
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.1467889338
Short name T82
Test name
Test status
Simulation time 44542995 ps
CPU time 0.73 seconds
Started Mar 19 02:15:00 PM PDT 24
Finished Mar 19 02:15:01 PM PDT 24
Peak memory 206060 kb
Host smart-2a680bf8-0e5c-430a-8076-d9a54f3631df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1467889338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.1467889338
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.401093881
Short name T947
Test name
Test status
Simulation time 8906281858 ps
CPU time 68.87 seconds
Started Mar 19 02:15:11 PM PDT 24
Finished Mar 19 02:16:20 PM PDT 24
Peak memory 250632 kb
Host smart-d0a3e75e-f885-41c7-8e1f-3abd4619c681
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401093881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.401093881
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.1632811575
Short name T498
Test name
Test status
Simulation time 116391873375 ps
CPU time 108.11 seconds
Started Mar 19 02:15:10 PM PDT 24
Finished Mar 19 02:16:59 PM PDT 24
Peak memory 249680 kb
Host smart-335244d4-09a9-4e50-b315-0e8b697fcd98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1632811575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.1632811575
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.2272626186
Short name T889
Test name
Test status
Simulation time 2507254668 ps
CPU time 57.1 seconds
Started Mar 19 02:15:11 PM PDT 24
Finished Mar 19 02:16:08 PM PDT 24
Peak memory 249668 kb
Host smart-bfd69954-8413-4a56-af87-cbe80b19d84a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272626186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle
.2272626186
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.4200061943
Short name T737
Test name
Test status
Simulation time 5658886150 ps
CPU time 18.25 seconds
Started Mar 19 02:15:11 PM PDT 24
Finished Mar 19 02:15:30 PM PDT 24
Peak memory 234280 kb
Host smart-6c6d9c14-f2a9-4931-bc02-58bef71d42cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4200061943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.4200061943
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_intercept.2055594100
Short name T215
Test name
Test status
Simulation time 2944665618 ps
CPU time 10.12 seconds
Started Mar 19 02:14:59 PM PDT 24
Finished Mar 19 02:15:09 PM PDT 24
Peak memory 234264 kb
Host smart-0b73614d-47ef-471d-a053-546b43910c68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2055594100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.2055594100
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.1023145454
Short name T919
Test name
Test status
Simulation time 1157333394 ps
CPU time 5.68 seconds
Started Mar 19 02:15:10 PM PDT 24
Finished Mar 19 02:15:16 PM PDT 24
Peak memory 224828 kb
Host smart-e1ad0587-ddf9-4ecf-8ecf-333194b9a3cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023145454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.1023145454
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_mem_parity.1996549224
Short name T708
Test name
Test status
Simulation time 125121183 ps
CPU time 1.1 seconds
Started Mar 19 02:14:59 PM PDT 24
Finished Mar 19 02:15:00 PM PDT 24
Peak memory 217060 kb
Host smart-a4bc66ed-d82c-4ee3-9a9d-606edeb5a88c
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996549224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 5.spi_device_mem_parity.1996549224
Directory /workspace/5.spi_device_mem_parity/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.3766179101
Short name T806
Test name
Test status
Simulation time 7943343352 ps
CPU time 14.42 seconds
Started Mar 19 02:15:01 PM PDT 24
Finished Mar 19 02:15:15 PM PDT 24
Peak memory 233336 kb
Host smart-432d7136-a54c-4fab-98aa-25b32b40d987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766179101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.3766179101
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.2971762097
Short name T167
Test name
Test status
Simulation time 3237488301 ps
CPU time 13.74 seconds
Started Mar 19 02:14:59 PM PDT 24
Finished Mar 19 02:15:13 PM PDT 24
Peak memory 233248 kb
Host smart-9a9bc4e6-feaa-447f-84b9-4f94a46cac83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971762097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.2971762097
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_ram_cfg.2000388192
Short name T73
Test name
Test status
Simulation time 19442483 ps
CPU time 0.77 seconds
Started Mar 19 02:15:00 PM PDT 24
Finished Mar 19 02:15:01 PM PDT 24
Peak memory 216488 kb
Host smart-7fd523fe-2388-40a7-b5a2-4e8c763c5f73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2000388192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_ram_cfg.2000388192
Directory /workspace/5.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.2568174839
Short name T596
Test name
Test status
Simulation time 907171010 ps
CPU time 4.96 seconds
Started Mar 19 02:15:14 PM PDT 24
Finished Mar 19 02:15:19 PM PDT 24
Peak memory 219768 kb
Host smart-0cf6dec6-0325-4c05-938a-7e34f74b7c8e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2568174839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_dire
ct.2568174839
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.2017503778
Short name T262
Test name
Test status
Simulation time 98629274934 ps
CPU time 378.14 seconds
Started Mar 19 02:15:10 PM PDT 24
Finished Mar 19 02:21:29 PM PDT 24
Peak memory 257532 kb
Host smart-b3b62b62-ead1-4c59-a18d-15cfef24bad6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017503778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stres
s_all.2017503778
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.1514929964
Short name T377
Test name
Test status
Simulation time 6870524534 ps
CPU time 16.89 seconds
Started Mar 19 02:14:59 PM PDT 24
Finished Mar 19 02:15:16 PM PDT 24
Peak memory 216812 kb
Host smart-a9271ee4-5d49-4419-8d5f-df47d48976eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514929964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.1514929964
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.2678453298
Short name T965
Test name
Test status
Simulation time 815271280 ps
CPU time 5.54 seconds
Started Mar 19 02:15:07 PM PDT 24
Finished Mar 19 02:15:13 PM PDT 24
Peak memory 216596 kb
Host smart-30317e80-4de2-4ff1-8306-b9cd331aba74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2678453298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.2678453298
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.1404092560
Short name T583
Test name
Test status
Simulation time 676518852 ps
CPU time 1.26 seconds
Started Mar 19 02:15:00 PM PDT 24
Finished Mar 19 02:15:01 PM PDT 24
Peak memory 216468 kb
Host smart-675dc35d-0adf-48d0-bb46-2173c42975d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404092560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.1404092560
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.2285254826
Short name T44
Test name
Test status
Simulation time 425396922 ps
CPU time 0.99 seconds
Started Mar 19 02:15:01 PM PDT 24
Finished Mar 19 02:15:03 PM PDT 24
Peak memory 205920 kb
Host smart-30fe0c74-7247-4bf5-9d0d-ce5b37c7bbdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2285254826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.2285254826
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.1077761435
Short name T249
Test name
Test status
Simulation time 20917745679 ps
CPU time 20.19 seconds
Started Mar 19 02:15:11 PM PDT 24
Finished Mar 19 02:15:31 PM PDT 24
Peak memory 240384 kb
Host smart-cca71779-f6c9-4e1f-a540-3de24d72cf85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1077761435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.1077761435
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.3539176124
Short name T825
Test name
Test status
Simulation time 13175898 ps
CPU time 0.74 seconds
Started Mar 19 02:15:32 PM PDT 24
Finished Mar 19 02:15:32 PM PDT 24
Peak memory 205664 kb
Host smart-3a41e664-1c2d-4e61-b21a-1aae3541420b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539176124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.3
539176124
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.798319964
Short name T482
Test name
Test status
Simulation time 149816904 ps
CPU time 2.6 seconds
Started Mar 19 02:15:21 PM PDT 24
Finished Mar 19 02:15:25 PM PDT 24
Peak memory 234360 kb
Host smart-1b13c4e1-5a97-4bd1-9b30-dfc92a38e6e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=798319964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.798319964
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.640442952
Short name T331
Test name
Test status
Simulation time 71563597 ps
CPU time 0.81 seconds
Started Mar 19 02:15:19 PM PDT 24
Finished Mar 19 02:15:20 PM PDT 24
Peak memory 205736 kb
Host smart-27fd1275-ad5b-4d7c-bb2c-ef0496b0b12e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=640442952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.640442952
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.2215409489
Short name T852
Test name
Test status
Simulation time 60966317967 ps
CPU time 82.27 seconds
Started Mar 19 02:15:20 PM PDT 24
Finished Mar 19 02:16:44 PM PDT 24
Peak memory 249260 kb
Host smart-5d8a78a6-1f1e-40f6-b820-771a7439252b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2215409489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.2215409489
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.2401815257
Short name T85
Test name
Test status
Simulation time 56598776013 ps
CPU time 93.38 seconds
Started Mar 19 02:15:20 PM PDT 24
Finished Mar 19 02:16:55 PM PDT 24
Peak memory 250804 kb
Host smart-2183e85f-89bb-4165-aaf1-85fab45645c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2401815257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.2401815257
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.4241525894
Short name T838
Test name
Test status
Simulation time 4654967472 ps
CPU time 69.2 seconds
Started Mar 19 02:15:21 PM PDT 24
Finished Mar 19 02:16:32 PM PDT 24
Peak memory 238316 kb
Host smart-e694389d-8ddf-4c82-a3e1-a9b05f988e1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241525894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle
.4241525894
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.1556819060
Short name T639
Test name
Test status
Simulation time 1217375837 ps
CPU time 9.9 seconds
Started Mar 19 02:15:19 PM PDT 24
Finished Mar 19 02:15:30 PM PDT 24
Peak memory 249456 kb
Host smart-2502819c-ae68-43a7-9c1e-e7363306ea1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556819060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.1556819060
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_intercept.1485383540
Short name T705
Test name
Test status
Simulation time 2059263310 ps
CPU time 3.62 seconds
Started Mar 19 02:15:20 PM PDT 24
Finished Mar 19 02:15:25 PM PDT 24
Peak memory 224716 kb
Host smart-acbb8124-d00a-4e08-aa0c-2d6c7a70a2f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1485383540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.1485383540
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.2272994500
Short name T343
Test name
Test status
Simulation time 1711927125 ps
CPU time 8.6 seconds
Started Mar 19 02:15:26 PM PDT 24
Finished Mar 19 02:15:34 PM PDT 24
Peak memory 235128 kb
Host smart-794ee7b8-9d2f-4ba8-84d5-22cebcf545db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272994500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.2272994500
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_mem_parity.3871416184
Short name T984
Test name
Test status
Simulation time 34826394 ps
CPU time 1.09 seconds
Started Mar 19 02:15:21 PM PDT 24
Finished Mar 19 02:15:23 PM PDT 24
Peak memory 217076 kb
Host smart-07f46243-7a12-4f2a-8e0a-0579346eb443
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871416184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 6.spi_device_mem_parity.3871416184
Directory /workspace/6.spi_device_mem_parity/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.325569695
Short name T237
Test name
Test status
Simulation time 21198192303 ps
CPU time 18.32 seconds
Started Mar 19 02:15:20 PM PDT 24
Finished Mar 19 02:15:39 PM PDT 24
Peak memory 233220 kb
Host smart-20a5a365-61f6-4fa0-a83d-00b1bf58b3d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=325569695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap.
325569695
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.4158962874
Short name T649
Test name
Test status
Simulation time 328540741 ps
CPU time 5.54 seconds
Started Mar 19 02:15:19 PM PDT 24
Finished Mar 19 02:15:25 PM PDT 24
Peak memory 217872 kb
Host smart-daf2b7a4-37c5-4fbe-bffb-b81918c81093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4158962874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.4158962874
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_ram_cfg.2674099716
Short name T417
Test name
Test status
Simulation time 25357716 ps
CPU time 0.75 seconds
Started Mar 19 02:15:19 PM PDT 24
Finished Mar 19 02:15:20 PM PDT 24
Peak memory 216476 kb
Host smart-ac93791a-1591-4a70-9d61-3be3cfa9d124
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674099716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_ram_cfg.2674099716
Directory /workspace/6.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.2705477024
Short name T966
Test name
Test status
Simulation time 224796549 ps
CPU time 4.1 seconds
Started Mar 19 02:15:20 PM PDT 24
Finished Mar 19 02:15:26 PM PDT 24
Peak memory 219204 kb
Host smart-f3758ac8-c4c8-4826-a79b-9d1e07795cef
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2705477024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_dire
ct.2705477024
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.432467385
Short name T939
Test name
Test status
Simulation time 30702160355 ps
CPU time 139.26 seconds
Started Mar 19 02:15:32 PM PDT 24
Finished Mar 19 02:17:52 PM PDT 24
Peak memory 257496 kb
Host smart-a2cc5c25-de1f-42a9-993b-a1836f3464ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432467385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stress
_all.432467385
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.3723518686
Short name T480
Test name
Test status
Simulation time 33244427876 ps
CPU time 78.24 seconds
Started Mar 19 02:15:21 PM PDT 24
Finished Mar 19 02:16:40 PM PDT 24
Peak memory 216964 kb
Host smart-d919001e-700b-4271-8c95-88b4aabf6087
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723518686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.3723518686
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.963736823
Short name T843
Test name
Test status
Simulation time 9069851985 ps
CPU time 24.38 seconds
Started Mar 19 02:15:20 PM PDT 24
Finished Mar 19 02:15:46 PM PDT 24
Peak memory 216728 kb
Host smart-7f47eb4b-7de7-4dce-8eb3-2e837c0bcd04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963736823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.963736823
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.3094279027
Short name T607
Test name
Test status
Simulation time 133293562 ps
CPU time 1.81 seconds
Started Mar 19 02:15:20 PM PDT 24
Finished Mar 19 02:15:23 PM PDT 24
Peak memory 217820 kb
Host smart-1aa6cd35-e540-4f57-a465-12902e30af1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3094279027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.3094279027
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.3184662613
Short name T554
Test name
Test status
Simulation time 52329255 ps
CPU time 0.88 seconds
Started Mar 19 02:15:19 PM PDT 24
Finished Mar 19 02:15:20 PM PDT 24
Peak memory 205892 kb
Host smart-57858db2-662b-4707-9b3a-2fd7e83e97e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3184662613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.3184662613
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.2920904827
Short name T556
Test name
Test status
Simulation time 271988900 ps
CPU time 2.63 seconds
Started Mar 19 02:15:21 PM PDT 24
Finished Mar 19 02:15:24 PM PDT 24
Peak memory 233924 kb
Host smart-43abfeeb-9027-46d7-87b6-4af730f0c95b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920904827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.2920904827
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.3289272991
Short name T932
Test name
Test status
Simulation time 14554564 ps
CPU time 0.73 seconds
Started Mar 19 02:15:45 PM PDT 24
Finished Mar 19 02:15:46 PM PDT 24
Peak memory 205692 kb
Host smart-caedb734-6f26-456a-b013-b9ea1efc8954
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289272991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.3
289272991
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.1050458493
Short name T486
Test name
Test status
Simulation time 688158353 ps
CPU time 4.07 seconds
Started Mar 19 02:15:40 PM PDT 24
Finished Mar 19 02:15:45 PM PDT 24
Peak memory 233976 kb
Host smart-28b494b9-7ad8-4030-891b-1fab1741fa57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1050458493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.1050458493
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.7270408
Short name T872
Test name
Test status
Simulation time 45082148 ps
CPU time 0.82 seconds
Started Mar 19 02:15:31 PM PDT 24
Finished Mar 19 02:15:32 PM PDT 24
Peak memory 207120 kb
Host smart-8e9deda8-1de7-4c32-91ab-243593ac70d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7270408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.7270408
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.2858751793
Short name T186
Test name
Test status
Simulation time 8801777392 ps
CPU time 92.89 seconds
Started Mar 19 02:15:41 PM PDT 24
Finished Mar 19 02:17:14 PM PDT 24
Peak memory 241484 kb
Host smart-cd9fd089-136e-42a3-af78-a6a08c435d6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858751793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.2858751793
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.575673991
Short name T784
Test name
Test status
Simulation time 60597092367 ps
CPU time 77.23 seconds
Started Mar 19 02:15:40 PM PDT 24
Finished Mar 19 02:16:57 PM PDT 24
Peak memory 241500 kb
Host smart-8572bf36-1603-4df5-94a7-72ce7175ce6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575673991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle.
575673991
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.987805883
Short name T277
Test name
Test status
Simulation time 1483580508 ps
CPU time 22.31 seconds
Started Mar 19 02:15:40 PM PDT 24
Finished Mar 19 02:16:03 PM PDT 24
Peak memory 249300 kb
Host smart-55a16a25-1348-42c6-ae79-820a4f41daa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=987805883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.987805883
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_intercept.11815956
Short name T958
Test name
Test status
Simulation time 11833389894 ps
CPU time 5.92 seconds
Started Mar 19 02:15:39 PM PDT 24
Finished Mar 19 02:15:45 PM PDT 24
Peak memory 235344 kb
Host smart-fa267073-2217-48da-a67e-6d61167304e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11815956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.11815956
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.2727224723
Short name T220
Test name
Test status
Simulation time 2917787842 ps
CPU time 9.79 seconds
Started Mar 19 02:15:41 PM PDT 24
Finished Mar 19 02:15:52 PM PDT 24
Peak memory 232896 kb
Host smart-8abdee7f-e5a0-4977-8339-a0ee92a7fd09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2727224723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.2727224723
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_mem_parity.2206953443
Short name T453
Test name
Test status
Simulation time 36029071 ps
CPU time 1.14 seconds
Started Mar 19 02:15:30 PM PDT 24
Finished Mar 19 02:15:31 PM PDT 24
Peak memory 216992 kb
Host smart-e241a993-88a7-4da7-8f1e-97891cc7c5d4
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206953443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 7.spi_device_mem_parity.2206953443
Directory /workspace/7.spi_device_mem_parity/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.1694246942
Short name T807
Test name
Test status
Simulation time 1805892300 ps
CPU time 5.43 seconds
Started Mar 19 02:15:40 PM PDT 24
Finished Mar 19 02:15:46 PM PDT 24
Peak memory 233676 kb
Host smart-8749b87f-c307-451a-bfe0-e7bb270c585d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1694246942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap
.1694246942
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.249262559
Short name T487
Test name
Test status
Simulation time 2864523638 ps
CPU time 6.38 seconds
Started Mar 19 02:15:40 PM PDT 24
Finished Mar 19 02:15:46 PM PDT 24
Peak memory 217296 kb
Host smart-56afa5bf-9f30-4e7b-8306-7541cac19ac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=249262559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.249262559
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_ram_cfg.2286257103
Short name T329
Test name
Test status
Simulation time 43706335 ps
CPU time 0.73 seconds
Started Mar 19 02:15:31 PM PDT 24
Finished Mar 19 02:15:32 PM PDT 24
Peak memory 216492 kb
Host smart-2e77475d-17ec-4a5d-a537-47331e76ba2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2286257103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_ram_cfg.2286257103
Directory /workspace/7.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.790289456
Short name T548
Test name
Test status
Simulation time 819900380 ps
CPU time 5.44 seconds
Started Mar 19 02:15:41 PM PDT 24
Finished Mar 19 02:15:47 PM PDT 24
Peak memory 222780 kb
Host smart-f27c6518-b748-47d3-9939-5608f686cc11
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=790289456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_direc
t.790289456
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.1047805776
Short name T166
Test name
Test status
Simulation time 534537611 ps
CPU time 1.21 seconds
Started Mar 19 02:15:41 PM PDT 24
Finished Mar 19 02:15:42 PM PDT 24
Peak memory 207412 kb
Host smart-0bf0f178-74f7-4dd6-8f5b-76f0b479709f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047805776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stres
s_all.1047805776
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.1329049082
Short name T163
Test name
Test status
Simulation time 27711040695 ps
CPU time 43.06 seconds
Started Mar 19 02:15:29 PM PDT 24
Finished Mar 19 02:16:12 PM PDT 24
Peak memory 216792 kb
Host smart-17b85cec-c4dc-4505-bce6-8f06b25f3a62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1329049082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.1329049082
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.3958059576
Short name T742
Test name
Test status
Simulation time 2434051739 ps
CPU time 4.56 seconds
Started Mar 19 02:15:29 PM PDT 24
Finished Mar 19 02:15:34 PM PDT 24
Peak memory 216696 kb
Host smart-8a1c6b5f-912e-4fd3-8716-3a99bbc7ca04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3958059576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.3958059576
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.2278608553
Short name T378
Test name
Test status
Simulation time 456167443 ps
CPU time 2.46 seconds
Started Mar 19 02:15:40 PM PDT 24
Finished Mar 19 02:15:43 PM PDT 24
Peak memory 216924 kb
Host smart-5f35f9c9-c483-4961-9bde-5e232a9e7300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2278608553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.2278608553
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.1240364290
Short name T318
Test name
Test status
Simulation time 199506735 ps
CPU time 0.95 seconds
Started Mar 19 02:15:40 PM PDT 24
Finished Mar 19 02:15:41 PM PDT 24
Peak memory 206876 kb
Host smart-98d4b466-e304-41db-856e-4c887150fc2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1240364290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.1240364290
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.2815865786
Short name T190
Test name
Test status
Simulation time 818140201 ps
CPU time 6.86 seconds
Started Mar 19 02:15:41 PM PDT 24
Finished Mar 19 02:15:48 PM PDT 24
Peak memory 219980 kb
Host smart-4658d143-e411-4070-a44f-0f54b96acdf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815865786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.2815865786
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.4006900471
Short name T703
Test name
Test status
Simulation time 155331115 ps
CPU time 0.7 seconds
Started Mar 19 02:16:06 PM PDT 24
Finished Mar 19 02:16:07 PM PDT 24
Peak memory 205064 kb
Host smart-db66b539-6de2-4661-8a29-88d206ff8b99
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006900471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.4
006900471
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.2363855515
Short name T563
Test name
Test status
Simulation time 2932659359 ps
CPU time 4.34 seconds
Started Mar 19 02:15:51 PM PDT 24
Finished Mar 19 02:15:55 PM PDT 24
Peak memory 234332 kb
Host smart-a6565cef-3240-41df-9d68-f46ba706e6c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2363855515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.2363855515
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.166176901
Short name T20
Test name
Test status
Simulation time 12313566 ps
CPU time 0.77 seconds
Started Mar 19 02:15:40 PM PDT 24
Finished Mar 19 02:15:40 PM PDT 24
Peak memory 205764 kb
Host smart-608e27c9-7194-4d4e-ae10-1f0881378f33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=166176901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.166176901
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.2584309661
Short name T257
Test name
Test status
Simulation time 90679349456 ps
CPU time 163.75 seconds
Started Mar 19 02:15:52 PM PDT 24
Finished Mar 19 02:18:36 PM PDT 24
Peak memory 265412 kb
Host smart-d66768db-c06e-4c0f-9dcb-c9db9190dd74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2584309661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.2584309661
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.1757129666
Short name T450
Test name
Test status
Simulation time 30564308979 ps
CPU time 111.29 seconds
Started Mar 19 02:15:52 PM PDT 24
Finished Mar 19 02:17:44 PM PDT 24
Peak memory 255756 kb
Host smart-f184e39f-4125-48b9-a545-8fb83a2cf046
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1757129666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.1757129666
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.4257589615
Short name T267
Test name
Test status
Simulation time 1101247998499 ps
CPU time 451.32 seconds
Started Mar 19 02:16:08 PM PDT 24
Finished Mar 19 02:23:39 PM PDT 24
Peak memory 252876 kb
Host smart-d14e27af-881d-4b5e-a941-93c61ec9467c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4257589615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle
.4257589615
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.475770957
Short name T886
Test name
Test status
Simulation time 2046344582 ps
CPU time 9.46 seconds
Started Mar 19 02:15:52 PM PDT 24
Finished Mar 19 02:16:01 PM PDT 24
Peak memory 238668 kb
Host smart-625f8245-c6b3-4adb-bb83-60f3b655fa37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=475770957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.475770957
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_intercept.3138862465
Short name T244
Test name
Test status
Simulation time 289400079 ps
CPU time 3.77 seconds
Started Mar 19 02:15:56 PM PDT 24
Finished Mar 19 02:16:00 PM PDT 24
Peak memory 224880 kb
Host smart-55305be5-9ec1-47bb-856c-e0a6fff60f77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3138862465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.3138862465
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.3548607750
Short name T488
Test name
Test status
Simulation time 150286802371 ps
CPU time 48.11 seconds
Started Mar 19 02:15:56 PM PDT 24
Finished Mar 19 02:16:44 PM PDT 24
Peak memory 249160 kb
Host smart-4cd16635-aaf1-4c71-b96d-f1f3d2bf900d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3548607750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.3548607750
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_mem_parity.1997324320
Short name T987
Test name
Test status
Simulation time 45013443 ps
CPU time 1.02 seconds
Started Mar 19 02:15:45 PM PDT 24
Finished Mar 19 02:15:46 PM PDT 24
Peak memory 217132 kb
Host smart-59f152a2-05fe-41f8-b46e-c1bc8eb816fc
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997324320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 8.spi_device_mem_parity.1997324320
Directory /workspace/8.spi_device_mem_parity/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.537081447
Short name T761
Test name
Test status
Simulation time 5529991500 ps
CPU time 11.7 seconds
Started Mar 19 02:15:54 PM PDT 24
Finished Mar 19 02:16:06 PM PDT 24
Peak memory 235144 kb
Host smart-e9220cf8-a6bf-4dc0-b151-e38cad1f56ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=537081447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap.
537081447
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.2319835161
Short name T405
Test name
Test status
Simulation time 3106736844 ps
CPU time 5.86 seconds
Started Mar 19 02:15:52 PM PDT 24
Finished Mar 19 02:15:58 PM PDT 24
Peak memory 234364 kb
Host smart-e5e6c834-5fc5-4108-af10-081e352e8bcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2319835161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.2319835161
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_ram_cfg.2436853719
Short name T805
Test name
Test status
Simulation time 129955968 ps
CPU time 0.74 seconds
Started Mar 19 02:15:41 PM PDT 24
Finished Mar 19 02:15:42 PM PDT 24
Peak memory 216464 kb
Host smart-019c6e4d-f4f0-451c-b9f9-eef0e659237d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2436853719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_ram_cfg.2436853719
Directory /workspace/8.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.1443120205
Short name T145
Test name
Test status
Simulation time 942723321 ps
CPU time 4.21 seconds
Started Mar 19 02:15:52 PM PDT 24
Finished Mar 19 02:15:56 PM PDT 24
Peak memory 222760 kb
Host smart-9c1a8c41-e404-4648-852a-8705d4466b9c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1443120205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_dire
ct.1443120205
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.350058023
Short name T52
Test name
Test status
Simulation time 173206933416 ps
CPU time 390.02 seconds
Started Mar 19 02:16:06 PM PDT 24
Finished Mar 19 02:22:37 PM PDT 24
Peak memory 272716 kb
Host smart-f34da263-00d8-4043-bb47-dc4a9468a2ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350058023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stress
_all.350058023
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.2002247616
Short name T722
Test name
Test status
Simulation time 738898697 ps
CPU time 8.38 seconds
Started Mar 19 02:15:45 PM PDT 24
Finished Mar 19 02:15:53 PM PDT 24
Peak memory 216776 kb
Host smart-97904348-bf77-4246-9c90-8c688ef365a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002247616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.2002247616
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.3999842780
Short name T376
Test name
Test status
Simulation time 6860851494 ps
CPU time 12.26 seconds
Started Mar 19 02:15:40 PM PDT 24
Finished Mar 19 02:15:53 PM PDT 24
Peak memory 216636 kb
Host smart-c88bc81a-0d74-4a80-9af9-b1e8df31cfd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3999842780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.3999842780
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.2046555207
Short name T964
Test name
Test status
Simulation time 64222810 ps
CPU time 1.09 seconds
Started Mar 19 02:15:52 PM PDT 24
Finished Mar 19 02:15:53 PM PDT 24
Peak memory 207260 kb
Host smart-08533950-72b3-41b9-ac93-35e068ce8f0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2046555207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.2046555207
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.3947825427
Short name T510
Test name
Test status
Simulation time 35642505 ps
CPU time 0.83 seconds
Started Mar 19 02:15:49 PM PDT 24
Finished Mar 19 02:15:50 PM PDT 24
Peak memory 205916 kb
Host smart-e7e220ab-bc9e-4f15-bc28-030775385cef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3947825427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.3947825427
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.530220613
Short name T871
Test name
Test status
Simulation time 105339454 ps
CPU time 2.62 seconds
Started Mar 19 02:15:51 PM PDT 24
Finished Mar 19 02:15:54 PM PDT 24
Peak memory 218856 kb
Host smart-2f56e075-ba64-430f-9080-799a640ae5fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=530220613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.530220613
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.115366112
Short name T387
Test name
Test status
Simulation time 16388942 ps
CPU time 0.69 seconds
Started Mar 19 02:16:15 PM PDT 24
Finished Mar 19 02:16:16 PM PDT 24
Peak memory 205972 kb
Host smart-0bfac7cf-f298-4fae-b8d6-649d080caefb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115366112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.115366112
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.499937009
Short name T212
Test name
Test status
Simulation time 1869116008 ps
CPU time 5.05 seconds
Started Mar 19 02:16:15 PM PDT 24
Finished Mar 19 02:16:21 PM PDT 24
Peak memory 220084 kb
Host smart-8240e51c-52a7-421e-a362-606d11cc219a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=499937009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.499937009
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.3545829678
Short name T978
Test name
Test status
Simulation time 21283335 ps
CPU time 0.83 seconds
Started Mar 19 02:16:04 PM PDT 24
Finished Mar 19 02:16:06 PM PDT 24
Peak memory 207064 kb
Host smart-1aba748a-3383-4a42-9e8a-ecffd3c6682b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3545829678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.3545829678
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.896391503
Short name T88
Test name
Test status
Simulation time 36573444241 ps
CPU time 208.47 seconds
Started Mar 19 02:16:17 PM PDT 24
Finished Mar 19 02:19:45 PM PDT 24
Peak memory 257888 kb
Host smart-7ef7a6c8-c825-44ce-9c07-0b628770bf61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=896391503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.896391503
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.2825188436
Short name T809
Test name
Test status
Simulation time 25019688829 ps
CPU time 174.48 seconds
Started Mar 19 02:16:17 PM PDT 24
Finished Mar 19 02:19:11 PM PDT 24
Peak memory 251704 kb
Host smart-6c550df7-34a6-4015-b3b4-e864c6020f25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2825188436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.2825188436
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.734368427
Short name T192
Test name
Test status
Simulation time 17976694978 ps
CPU time 184.77 seconds
Started Mar 19 02:16:15 PM PDT 24
Finished Mar 19 02:19:20 PM PDT 24
Peak memory 271884 kb
Host smart-3e2d26ea-558b-41f6-b038-467e2265b64c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734368427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle.
734368427
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.3337046407
Short name T635
Test name
Test status
Simulation time 19891084187 ps
CPU time 27.9 seconds
Started Mar 19 02:16:15 PM PDT 24
Finished Mar 19 02:16:43 PM PDT 24
Peak memory 248192 kb
Host smart-601a9e13-3989-4137-b695-12abdd62b473
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337046407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.3337046407
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_intercept.3642655340
Short name T979
Test name
Test status
Simulation time 5424507882 ps
CPU time 8.79 seconds
Started Mar 19 02:16:05 PM PDT 24
Finished Mar 19 02:16:14 PM PDT 24
Peak memory 219816 kb
Host smart-2b029661-b70d-4b88-8fc1-6af84a01e208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3642655340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.3642655340
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.2669231356
Short name T183
Test name
Test status
Simulation time 44164453956 ps
CPU time 51.2 seconds
Started Mar 19 02:16:05 PM PDT 24
Finished Mar 19 02:16:57 PM PDT 24
Peak memory 231548 kb
Host smart-e5deb9d0-78a4-4f5b-a902-f29b2fa26fe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2669231356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.2669231356
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_mem_parity.1218801757
Short name T782
Test name
Test status
Simulation time 157539236 ps
CPU time 1.02 seconds
Started Mar 19 02:16:07 PM PDT 24
Finished Mar 19 02:16:09 PM PDT 24
Peak memory 217100 kb
Host smart-a0a51352-1699-43a3-94ae-bec8a85c6c77
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218801757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 9.spi_device_mem_parity.1218801757
Directory /workspace/9.spi_device_mem_parity/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.3186920015
Short name T346
Test name
Test status
Simulation time 2645633085 ps
CPU time 4.44 seconds
Started Mar 19 02:16:07 PM PDT 24
Finished Mar 19 02:16:12 PM PDT 24
Peak memory 234164 kb
Host smart-b5e01755-167f-4213-b767-ed0cf61d6437
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3186920015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap
.3186920015
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.1286507984
Short name T611
Test name
Test status
Simulation time 36120309157 ps
CPU time 26.41 seconds
Started Mar 19 02:16:05 PM PDT 24
Finished Mar 19 02:16:31 PM PDT 24
Peak memory 236352 kb
Host smart-3f07eee7-2bda-4b85-b79b-59fe9869e095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1286507984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.1286507984
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_ram_cfg.451505971
Short name T494
Test name
Test status
Simulation time 18166752 ps
CPU time 0.74 seconds
Started Mar 19 02:16:05 PM PDT 24
Finished Mar 19 02:16:06 PM PDT 24
Peak memory 216468 kb
Host smart-4b56c0ed-b003-44b3-b834-79fed6b8b8a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=451505971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_ram_cfg.451505971
Directory /workspace/9.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.3101380181
Short name T903
Test name
Test status
Simulation time 920713394 ps
CPU time 5.41 seconds
Started Mar 19 02:16:17 PM PDT 24
Finished Mar 19 02:16:23 PM PDT 24
Peak memory 223096 kb
Host smart-c5539940-b15c-4aa7-9a2d-8408f75d5c3d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3101380181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_dire
ct.3101380181
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.1795517001
Short name T914
Test name
Test status
Simulation time 857307848 ps
CPU time 9.35 seconds
Started Mar 19 02:16:06 PM PDT 24
Finished Mar 19 02:16:16 PM PDT 24
Peak memory 216632 kb
Host smart-933e438e-6175-4cd9-9328-bfa73b6cb46e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1795517001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.1795517001
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.49982209
Short name T665
Test name
Test status
Simulation time 1324159208 ps
CPU time 5.45 seconds
Started Mar 19 02:16:06 PM PDT 24
Finished Mar 19 02:16:11 PM PDT 24
Peak memory 216396 kb
Host smart-fba3bf91-65ff-458f-9fea-d4196f0f7b43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49982209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.49982209
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.3471776919
Short name T542
Test name
Test status
Simulation time 439088179 ps
CPU time 2.2 seconds
Started Mar 19 02:16:04 PM PDT 24
Finished Mar 19 02:16:06 PM PDT 24
Peak memory 216764 kb
Host smart-952d9907-45a3-4262-a7b9-1ab489977a46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3471776919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.3471776919
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.3020352065
Short name T578
Test name
Test status
Simulation time 119340125 ps
CPU time 1.11 seconds
Started Mar 19 02:16:08 PM PDT 24
Finished Mar 19 02:16:09 PM PDT 24
Peak memory 206980 kb
Host smart-959c296d-5245-4f6a-9ffc-d0a0d7369ef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3020352065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.3020352065
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.2693492747
Short name T411
Test name
Test status
Simulation time 346891241 ps
CPU time 3.93 seconds
Started Mar 19 02:16:06 PM PDT 24
Finished Mar 19 02:16:10 PM PDT 24
Peak memory 219160 kb
Host smart-47b09745-809e-4a2f-acd2-26f307c4a3f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2693492747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.2693492747
Directory /workspace/9.spi_device_upload/latest
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