SPI_DEVICE/2P Simulation Results

Tuesday March 19 2024 19:02:40 UTC

GitHub Revision: `f7fc348358`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 93166527750821992054916907919379261408154533955814283538537589225972237641118

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	10.094m	294.289ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.500s	97.448us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.730s	95.461us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	38.060s	3.750ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	8.920s	1.265ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	4.180s	222.416us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.730s	95.461us	20	20	100.00
		spi_device_csr_aliasing	8.920s	1.265ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.670s	12.530us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.230s	73.346us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	0.860s	39.794us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	1.160s	160.382us	20	20	100.00
V2	mem_cfg	spi_device_ram_cfg	0.800s	16.487us	20	20	100.00
V2	tpm_read	spi_device_tpm_rw	14.760s	309.380us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	14.760s	309.380us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	32.920s	9.795ms	50	50	100.00
		spi_device_tpm_sts_read	1.240s	194.392us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	1.501m	17.142ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	43.110s	40.355ms	50	50	100.00
		spi_device_flash_all	7.831m	90.879ms	49	50	98.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	38.200s	54.754ms	50	50	100.00
		spi_device_flash_all	7.831m	90.879ms	49	50	98.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	38.200s	54.754ms	50	50	100.00
		spi_device_flash_all	7.831m	90.879ms	49	50	98.00
V2	cmd_info_slots	spi_device_flash_all	7.831m	90.879ms	49	50	98.00
V2	cmd_read_status	spi_device_intercept	15.140s	4.041ms	50	50	100.00
		spi_device_flash_all	7.831m	90.879ms	49	50	98.00
V2	cmd_read_jedec	spi_device_intercept	15.140s	4.041ms	50	50	100.00
		spi_device_flash_all	7.831m	90.879ms	49	50	98.00
V2	cmd_read_sfdp	spi_device_intercept	15.140s	4.041ms	50	50	100.00
		spi_device_flash_all	7.831m	90.879ms	49	50	98.00
V2	cmd_fast_read	spi_device_intercept	15.140s	4.041ms	50	50	100.00
		spi_device_flash_all	7.831m	90.879ms	49	50	98.00
V2	cmd_read_pipeline	spi_device_intercept	15.140s	4.041ms	50	50	100.00
		spi_device_flash_all	7.831m	90.879ms	49	50	98.00
V2	flash_cmd_upload	spi_device_upload	47.670s	81.028ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	54.350s	21.573ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	54.350s	21.573ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	54.350s	21.573ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	1.133m	26.675ms	49	50	98.00
		spi_device_read_buffer_direct	8.390s	8.476ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	54.350s	21.573ms	50	50	100.00
		spi_device_flash_all	7.831m	90.879ms	49	50	98.00
V2	quad_spi	spi_device_flash_all	7.831m	90.879ms	49	50	98.00
V2	dual_spi	spi_device_flash_all	7.831m	90.879ms	49	50	98.00
V2	4b_3b_feature	spi_device_cfg_cmd	8.390s	2.795ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	8.390s	2.795ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	10.094m	294.289ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	11.046m	269.841ms	49	50	98.00
V2	stress_all	spi_device_stress_all	20.997m	412.467ms	47	50	94.00
V2	alert_test	spi_device_alert_test	0.790s	45.331us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.800s	20.500us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	5.550s	722.741us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	5.550s	722.741us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.500s	97.448us	5	5	100.00
		spi_device_csr_rw	2.730s	95.461us	20	20	100.00
		spi_device_csr_aliasing	8.920s	1.265ms	5	5	100.00
		spi_device_same_csr_outstanding	4.170s	290.016us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.500s	97.448us	5	5	100.00
		spi_device_csr_rw	2.730s	95.461us	20	20	100.00
		spi_device_csr_aliasing	8.920s	1.265ms	5	5	100.00
		spi_device_same_csr_outstanding	4.170s	290.016us	20	20	100.00
V2		TOTAL			974	980	99.39
V2S	tl_intg_err	spi_device_sec_cm	1.110s	61.397us	5	5	100.00
		spi_device_tl_intg_err	23.140s	980.743us	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	23.140s	980.743us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
		TOTAL			1114	1120	99.46

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	22	22	18	81.82
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.99	98.39	94.43	98.61	89.36	97.10	95.82	98.22

Failure Buckets

UVM_ERROR (spi_device_scoreboard.sv:1101) [scoreboard] Check failed item.d_data[i] == intr_exp[i] (* [*] vs * [*]) Compare PayloadOverflow mismatch, act (*) != exp * has 2 failures:

Test spi_device_stress_all has 2 failures.

9.spi_device_stress_all.85674673169005899703404078478010933702024304222874855764771602247778932838123
Line 297, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/9.spi_device_stress_all/latest/run.log

  UVM_ERROR @ 39135321463 ps: (spi_device_scoreboard.sv:1101) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp[i] (0 [0x0] vs 1 [0x1]) Compare PayloadOverflow mismatch, act (0x0) != exp 1
  UVM_INFO @ 40214530463 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 5/9
  UVM_INFO @ 41202441463 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.tpm_vseq] starting sequence 6/10
  UVM_INFO @ 42383661463 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 6/9
  UVM_INFO @ 46522755463 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 7/9

18.spi_device_stress_all.52954517641698602771074218388724613658413850939744966686988359747140888302993
Line 267, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/18.spi_device_stress_all/latest/run.log

  UVM_ERROR @ 3987905669 ps: (spi_device_scoreboard.sv:1101) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp[i] (0 [0x0] vs 1 [0x1]) Compare PayloadOverflow mismatch, act (0x0) != exp 1
  UVM_INFO @ 3994406137 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 6/11
  UVM_INFO @ 4419054430 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 7/11
  UVM_INFO @ 4739693606 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 8/11
  UVM_INFO @ 5075539515 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 9/11

UVM_ERROR (spi_device_scoreboard.sv:1070) [scoreboard] Check failed (item.d_data inside {exp_data_q}) act (*) != exp '{'{other_status:*, wel:*, busy:*}} has 2 failures:

Test spi_device_flash_and_tpm_min_idle has 1 failures.

11.spi_device_flash_and_tpm_min_idle.93643622422209938476901388156704436767086157233058356775817491015366682235149
Line 268, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/11.spi_device_flash_and_tpm_min_idle/latest/run.log

  UVM_ERROR @ 4138976828 ps: (spi_device_scoreboard.sv:1070) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xe88b9c) != exp '{'{other_status:'h3a22e7, wel:'h0, busy:'h1}}
  UVM_INFO @ 4511237703 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.flash_vseq] running iteration 8/9
  UVM_INFO @ 4554156828 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.tpm_vseq] starting sequence 12/20
  UVM_INFO @ 4912656828 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.tpm_vseq] starting sequence 13/20
  UVM_INFO @ 5209676828 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.tpm_vseq] starting sequence 14/20

Test spi_device_flash_all has 1 failures.

24.spi_device_flash_all.54595871657322188125009036083740129946819163878532544228917498791968424757062
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/24.spi_device_flash_all/latest/run.log

  UVM_ERROR @ 34894560488 ps: (spi_device_scoreboard.sv:1070) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xc8e9ea) != exp '{'{other_status:'h323a7a, wel:'h0, busy:'h0}}
  UVM_INFO @ 35519880488 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (spi_device_pass_base_vseq.sv:643) [flash_vseq] Check failed busy == * (* [*] vs * [*]) flash_status.busy == * expected to be * has 1 failures:

Test spi_device_stress_all has 1 failures.

39.spi_device_stress_all.91921794284539155319878887982177264648845038296465110711545286325031450831772
Line 277, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/39.spi_device_stress_all/latest/run.log

  UVM_ERROR @ 13281510062 ps: (spi_device_pass_base_vseq.sv:643) [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] Check failed busy == 0 (1 [0x1] vs 0 [0x0]) flash_status.busy == 1 expected to be 0
  UVM_INFO @ 13317793202 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 14/16
  UVM_INFO @ 14946743040 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 15/16
  UVM_INFO @ 16468950062 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (spi_device_scoreboard.sv:921) [scoreboard] timeout occurred! has 1 failures:
- Test spi_device_flash_mode has 1 failures.
  - 44.spi_device_flash_mode.73613973221317688537015606321308517162935781329256528165451828431760571503135
    Line 249, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/44.spi_device_flash_mode/latest/run.log
```
  UVM_FATAL @ 33437117649 ps: (spi_device_scoreboard.sv:921) [uvm_test_top.env.scoreboard] timeout occurred!
  UVM_INFO @ 33437117649 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Past Results

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