SPI_DEVICE/2P Simulation Results

Saturday February 08 2025 05:05:54 UTC

GitHub Revision: 9f20940d49

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 88344288495849993302635329522992994622996067932062874150778031027723701018040

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	11.952m	327.068ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	2.090s	55.414us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	3.820s	450.410us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	33.800s	2.443ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	18.150s	3.147ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	5.520s	864.994us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	3.820s	450.410us	20	20	100.00
		spi_device_csr_aliasing	18.150s	3.147ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	1.050s	12.969us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	3.200s	27.902us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	1.270s	21.937us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	1.660s	32.663us	20	20	100.00
V2	mem_cfg	spi_device_ram_cfg	1.060s	39.727us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	16.320s	312.356us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	16.320s	312.356us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	43.190s	15.725ms	50	50	100.00
		spi_device_tpm_sts_read	1.660s	96.775us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	1.032m	11.661ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	1.190m	133.809ms	50	50	100.00
		spi_device_flash_all	7.682m	376.831ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	48.850s	8.283ms	50	50	100.00
		spi_device_flash_all	7.682m	376.831ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	48.850s	8.283ms	50	50	100.00
		spi_device_flash_all	7.682m	376.831ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	7.682m	376.831ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	27.700s	9.217ms	50	50	100.00
		spi_device_flash_all	7.682m	376.831ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	27.700s	9.217ms	50	50	100.00
		spi_device_flash_all	7.682m	376.831ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	27.700s	9.217ms	50	50	100.00
		spi_device_flash_all	7.682m	376.831ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	27.700s	9.217ms	50	50	100.00
		spi_device_flash_all	7.682m	376.831ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	27.700s	9.217ms	50	50	100.00
		spi_device_flash_all	7.682m	376.831ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	1.224m	14.950ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	1.661m	8.262ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	1.661m	8.262ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	1.661m	8.262ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	1.497m	27.204ms	50	50	100.00
		spi_device_read_buffer_direct	27.330s	2.203ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	1.661m	8.262ms	50	50	100.00
		spi_device_flash_all	7.682m	376.831ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	7.682m	376.831ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	7.682m	376.831ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	27.140s	2.569ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	27.140s	2.569ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	11.952m	327.068ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	13.418m	326.409ms	50	50	100.00
V2	stress_all	spi_device_stress_all	16.477m	97.974ms	50	50	100.00
V2	alert_test	spi_device_alert_test	1.180s	52.271us	50	50	100.00
V2	intr_test	spi_device_intr_test	1.170s	258.486us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	9.380s	580.475us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	9.380s	580.475us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	2.090s	55.414us	5	5	100.00
		spi_device_csr_rw	3.820s	450.410us	20	20	100.00
		spi_device_csr_aliasing	18.150s	3.147ms	5	5	100.00
		spi_device_same_csr_outstanding	6.020s	2.675ms	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	2.090s	55.414us	5	5	100.00
		spi_device_csr_rw	3.820s	450.410us	20	20	100.00
		spi_device_csr_aliasing	18.150s	3.147ms	5	5	100.00
		spi_device_same_csr_outstanding	6.020s	2.675ms	20	20	100.00
V2		TOTAL			961	961	100.00
V2S	tl_intg_err	spi_device_sec_cm	1.800s	305.060us	5	5	100.00
		spi_device_tl_intg_err	22.690s	2.224ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	22.690s	2.224ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
	Unmapped tests	spi_device_flash_mode_ignore_cmds	8.095m	50.833ms	50	50	100.00
		TOTAL			1151	1151	100.00

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	1	100.00
V1	8	8	8	100.00
V2	22	22	22	100.00
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.07	98.44	94.08	98.62	89.36	97.28	95.43	99.26

Past Results

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