SPI_DEVICE/2P Simulation Results

Monday October 14 2024 17:26:15 UTC

GitHub Revision: 12e3b8572e

Branch: os_regression_2024_10_14

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 85025606402499621082521464627961092918263397067038954055071960501195381950243

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke spi_device_flash_and_tpm 12.189m 82.560ms 50 50 100.00
V1 csr_hw_reset spi_device_csr_hw_reset 1.970s 24.118us 5 5 100.00
V1 csr_rw spi_device_csr_rw 33.330s 18 20 90.00
V1 csr_bit_bash spi_device_csr_bit_bash 30.600s 4.887ms 5 5 100.00
V1 csr_aliasing spi_device_csr_aliasing 23.720s 914.419us 5 5 100.00
V1 csr_mem_rw_with_rand_reset spi_device_csr_mem_rw_with_rand_reset 39.476s 16 20 80.00
V1 regwen_csr_and_corresponding_lockable_csr spi_device_csr_rw 33.330s 18 20 90.00
spi_device_csr_aliasing 23.720s 914.419us 5 5 100.00
V1 mem_walk spi_device_mem_walk 1.010s 35.050us 5 5 100.00
V1 mem_partial_access spi_device_mem_partial_access 2.370s 132.182us 5 5 100.00
V1 TOTAL 109 115 94.78
V2 csb_read spi_device_csb_read 1.290s 23.773us 50 50 100.00
V2 mem_parity spi_device_mem_parity 1.770s 227.377us 20 20 100.00
V2 mem_cfg spi_device_ram_cfg 1.200s 15.967us 1 1 100.00
V2 tpm_read spi_device_tpm_rw 9.810s 552.427us 50 50 100.00
V2 tpm_write spi_device_tpm_rw 9.810s 552.427us 50 50 100.00
V2 tpm_hw_reg spi_device_tpm_read_hw_reg 30.170s 11.379ms 50 50 100.00
spi_device_tpm_sts_read 1.660s 436.580us 50 50 100.00
V2 tpm_fully_random_case spi_device_tpm_all 52.230s 9.107ms 50 50 100.00
V2 pass_cmd_filtering spi_device_pass_cmd_filtering 49.670s 30.028ms 50 50 100.00
spi_device_flash_all 8.794m 279.909ms 50 50 100.00
V2 pass_addr_translation spi_device_pass_addr_payload_swap 38.860s 12.166ms 50 50 100.00
spi_device_flash_all 8.794m 279.909ms 50 50 100.00
V2 pass_payload_translation spi_device_pass_addr_payload_swap 38.860s 12.166ms 50 50 100.00
spi_device_flash_all 8.794m 279.909ms 50 50 100.00
V2 cmd_info_slots spi_device_flash_all 8.794m 279.909ms 50 50 100.00
V2 cmd_read_status spi_device_intercept 37.310s 4.340ms 50 50 100.00
spi_device_flash_all 8.794m 279.909ms 50 50 100.00
V2 cmd_read_jedec spi_device_intercept 37.310s 4.340ms 50 50 100.00
spi_device_flash_all 8.794m 279.909ms 50 50 100.00
V2 cmd_read_sfdp spi_device_intercept 37.310s 4.340ms 50 50 100.00
spi_device_flash_all 8.794m 279.909ms 50 50 100.00
V2 cmd_fast_read spi_device_intercept 37.310s 4.340ms 50 50 100.00
spi_device_flash_all 8.794m 279.909ms 50 50 100.00
V2 cmd_read_pipeline spi_device_intercept 37.310s 4.340ms 50 50 100.00
spi_device_flash_all 8.794m 279.909ms 50 50 100.00
V2 flash_cmd_upload spi_device_upload 46.940s 139.734ms 50 50 100.00
V2 mailbox_command spi_device_mailbox 3.796m 209.575ms 50 50 100.00
V2 mailbox_cross_outside_command spi_device_mailbox 3.796m 209.575ms 50 50 100.00
V2 mailbox_cross_inside_command spi_device_mailbox 3.796m 209.575ms 50 50 100.00
V2 cmd_read_buffer spi_device_flash_mode 1.425m 18.674ms 50 50 100.00
spi_device_read_buffer_direct 24.030s 10.770ms 50 50 100.00
V2 cmd_dummy_cycle spi_device_mailbox 3.796m 209.575ms 50 50 100.00
spi_device_flash_all 8.794m 279.909ms 50 50 100.00
V2 quad_spi spi_device_flash_all 8.794m 279.909ms 50 50 100.00
V2 dual_spi spi_device_flash_all 8.794m 279.909ms 50 50 100.00
V2 4b_3b_feature spi_device_cfg_cmd 37.570s 4.616ms 50 50 100.00
V2 write_enable_disable spi_device_cfg_cmd 37.570s 4.616ms 50 50 100.00
V2 TPM_with_flash_or_passthrough_mode spi_device_flash_and_tpm 12.189m 82.560ms 50 50 100.00
V2 tpm_and_flash_trans_with_min_inactive_time spi_device_flash_and_tpm_min_idle 15.274m 188.195ms 50 50 100.00
V2 stress_all spi_device_stress_all 16.010m 1.972s 50 50 100.00
V2 alert_test spi_device_alert_test 1.220s 16.448us 50 50 100.00
V2 intr_test spi_device_intr_test 39.391s 46 50 92.00
V2 tl_d_oob_addr_access spi_device_tl_errors 39.539s 15 20 75.00
V2 tl_d_illegal_access spi_device_tl_errors 39.539s 15 20 75.00
V2 tl_d_outstanding_access spi_device_csr_hw_reset 1.970s 24.118us 5 5 100.00
spi_device_csr_rw 33.330s 18 20 90.00
spi_device_csr_aliasing 23.720s 914.419us 5 5 100.00
spi_device_same_csr_outstanding 39.640s 17 20 85.00
V2 tl_d_partial_access spi_device_csr_hw_reset 1.970s 24.118us 5 5 100.00
spi_device_csr_rw 33.330s 18 20 90.00
spi_device_csr_aliasing 23.720s 914.419us 5 5 100.00
spi_device_same_csr_outstanding 39.640s 17 20 85.00
V2 TOTAL 949 961 98.75
V2S tl_intg_err spi_device_sec_cm 2.000s 148.363us 5 5 100.00
spi_device_tl_intg_err 33.393s 17 20 85.00
V2S sec_cm_bus_integrity spi_device_tl_intg_err 33.393s 17 20 85.00
V2S TOTAL 22 25 88.00
V3 stress_all_with_rand_reset spi_device_stress_all_with_rand_reset 0 0 --
V3 TOTAL 0 0 --
Unmapped tests spi_device_flash_mode_ignore_cmds 7.752m 55.709ms 50 50 100.00
TOTAL 1130 1151 98.18

Testplan Progress

Items Total Written Passing Progress
N.A. 1 1 1 100.00
V1 8 8 6 75.00
V2 22 22 19 86.36
V2S 2 2 1 50.00
V3 1 0 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
96.76 98.70 96.89 99.01 89.36 98.59 95.56 99.21

Failure Buckets

Past Results