Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	6380903	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

6778474

1

T1

3

T2

1124

T3

942

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	8467263	1			T1	1		T2	314		T3	71
values[0x0]	2343840	1			T2	438		T3	485		T4	1309
values[0x1]	2348274	1			T1	4		T2	466		T3	448

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4622857	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

8536520

1

T1

4

T2

1140

T3

962

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	53822	1			T3	1		T4	14		T5	3
valid_sources[0x01]	51080	1			T3	5		T4	11		T5	1
valid_sources[0x02]	48702	1			T4	14		T5	3		T8	4
valid_sources[0x03]	51240	1			T1	1		T3	3		T4	14
valid_sources[0x04]	49485	1			T3	1		T4	16		T5	6
valid_sources[0x05]	49059	1			T3	3		T4	20		T5	2
valid_sources[0x06]	52960	1			T3	10		T4	19		T5	6
valid_sources[0x07]	51031	1			T3	6		T4	16		T5	5
valid_sources[0x08]	50529	1			T4	12		T5	3		T8	2
valid_sources[0x09]	51368	1			T3	4		T4	18		T5	1
valid_sources[0x0a]	50509	1			T3	3		T4	7		T5	4
valid_sources[0x0b]	52351	1			T3	2		T4	11		T5	1
valid_sources[0x0c]	52234	1			T3	1		T4	9		T5	2
valid_sources[0x0d]	55087	1			T3	6		T4	17		T5	3
valid_sources[0x0e]	47692	1			T3	6		T4	18		T5	6
valid_sources[0x0f]	48872	1			T3	4		T4	18		T5	2
valid_sources[0x10]	50749	1			T3	6		T4	11		T5	1
valid_sources[0x11]	55681	1			T2	1		T3	6		T4	13
valid_sources[0x12]	51991	1			T4	17		T5	6		T8	8
valid_sources[0x13]	52572	1			T3	4		T4	18		T5	4
valid_sources[0x14]	50581	1			T3	1		T4	11		T5	3
valid_sources[0x15]	57462	1			T3	3		T4	9		T5	6
valid_sources[0x16]	49892	1			T3	2		T4	10		T5	5
valid_sources[0x17]	51797	1			T3	5		T4	13		T5	2
valid_sources[0x18]	50879	1			T3	4		T4	17		T5	2
valid_sources[0x19]	52839	1			T3	2		T4	11		T5	1
valid_sources[0x1a]	50771	1			T3	5		T4	11		T5	6
valid_sources[0x1b]	49063	1			T3	8		T4	16		T5	4
valid_sources[0x1c]	50721	1			T3	5		T4	20		T5	10
valid_sources[0x1d]	51017	1			T3	4		T4	12		T5	5
valid_sources[0x1e]	51085	1			T3	3		T4	10		T5	1
valid_sources[0x1f]	48157	1			T3	3		T4	20		T5	3
valid_sources[0x20]	54628	1			T2	1		T3	1		T4	11
valid_sources[0x21]	55155	1			T3	5		T4	16		T5	3
valid_sources[0x22]	53921	1			T3	3		T4	8		T5	3
valid_sources[0x23]	57107	1			T3	3		T4	14		T5	3
valid_sources[0x24]	51499	1			T3	11		T4	19		T5	1
valid_sources[0x25]	52966	1			T1	4		T3	1		T4	13
valid_sources[0x26]	50857	1			T3	6		T4	21		T5	5
valid_sources[0x27]	48372	1			T3	4		T4	7		T5	3
valid_sources[0x28]	52694	1			T2	2		T3	6		T4	15
valid_sources[0x29]	52012	1			T3	2		T4	13		T5	6
valid_sources[0x2a]	52277	1			T3	3		T4	15		T5	8
valid_sources[0x2b]	48298	1			T3	3		T4	12		T5	2
valid_sources[0x2c]	55641	1			T2	85		T3	9		T4	12
valid_sources[0x2d]	52644	1			T3	5		T4	13		T5	1
valid_sources[0x2e]	50289	1			T3	2		T4	18		T5	3
valid_sources[0x2f]	53495	1			T3	2		T4	15		T8	1
valid_sources[0x30]	48783	1			T3	9		T4	11		T5	5
valid_sources[0x31]	50286	1			T3	3		T4	22		T5	4
valid_sources[0x32]	50694	1			T3	9		T4	7		T5	4
valid_sources[0x33]	52854	1			T3	2		T4	21		T5	3
valid_sources[0x34]	50654	1			T3	7		T4	16		T5	2
valid_sources[0x35]	55930	1			T3	2		T4	11		T5	1
valid_sources[0x36]	54405	1			T3	2		T4	12		T9	28
valid_sources[0x37]	54134	1			T3	4		T4	22		T5	4
valid_sources[0x38]	49832	1			T3	5		T4	13		T5	1
valid_sources[0x39]	50809	1			T2	1		T3	6		T4	8
valid_sources[0x3a]	49258	1			T3	3		T4	15		T5	2
valid_sources[0x3b]	47898	1			T3	4		T4	11		T5	3
valid_sources[0x3c]	52043	1			T3	6		T4	18		T5	3
valid_sources[0x3d]	49993	1			T3	3		T4	20		T5	4
valid_sources[0x3e]	47562	1			T3	8		T4	15		T5	3
valid_sources[0x3f]	49656	1			T3	4		T4	20		T8	4
valid_sources[0x40]	47991	1			T3	3		T4	16		T5	3
valid_sources[0x41]	50696	1			T3	1		T4	15		T5	4
valid_sources[0x42]	49959	1			T3	6		T4	13		T5	4
valid_sources[0x43]	52155	1			T3	4		T4	16		T5	1
valid_sources[0x44]	57671	1			T3	3		T4	17		T5	4
valid_sources[0x45]	52966	1			T3	4		T4	15		T5	2
valid_sources[0x46]	53633	1			T3	2		T4	10		T5	11
valid_sources[0x47]	50335	1			T3	3		T4	20		T5	2
valid_sources[0x48]	54368	1			T3	7		T4	16		T5	2
valid_sources[0x49]	54475	1			T3	5		T4	21		T5	1
valid_sources[0x4a]	51313	1			T3	6		T4	20		T5	4
valid_sources[0x4b]	49350	1			T3	4		T4	12		T5	10
valid_sources[0x4c]	48718	1			T2	1		T3	8		T4	12
valid_sources[0x4d]	53243	1			T3	3		T4	14		T5	3
valid_sources[0x4e]	49060	1			T3	2		T4	12		T5	7
valid_sources[0x4f]	47266	1			T3	13		T4	15		T5	3
valid_sources[0x50]	48710	1			T3	3		T4	14		T5	1
valid_sources[0x51]	49843	1			T3	2		T4	16		T5	2
valid_sources[0x52]	52614	1			T3	3		T4	15		T5	5
valid_sources[0x53]	51669	1			T3	3		T4	10		T5	4
valid_sources[0x54]	49109	1			T3	2		T4	7		T5	1
valid_sources[0x55]	49129	1			T3	3		T4	8		T6	15
valid_sources[0x56]	49072	1			T3	1		T4	17		T5	3
valid_sources[0x57]	53039	1			T4	17		T5	1		T8	1
valid_sources[0x58]	52401	1			T3	5		T4	11		T5	4
valid_sources[0x59]	46621	1			T3	4		T4	19		T5	3
valid_sources[0x5a]	52377	1			T3	5		T4	13		T5	5
valid_sources[0x5b]	57876	1			T3	4		T4	16		T5	6
valid_sources[0x5c]	51565	1			T3	6		T4	16		T5	3
valid_sources[0x5d]	48788	1			T3	7		T4	15		T5	4
valid_sources[0x5e]	53102	1			T3	5		T4	16		T5	1
valid_sources[0x5f]	50388	1			T3	3		T4	18		T9	90
valid_sources[0x60]	50386	1			T3	3		T4	18		T5	6
valid_sources[0x61]	54202	1			T3	1		T4	12		T5	4
valid_sources[0x62]	51965	1			T3	6		T4	14		T5	1
valid_sources[0x63]	49308	1			T3	4		T4	16		T5	2
valid_sources[0x64]	49267	1			T3	6		T4	10		T7	2
valid_sources[0x65]	50158	1			T3	5		T4	17		T5	6
valid_sources[0x66]	50646	1			T3	7		T4	26		T5	4
valid_sources[0x67]	48075	1			T3	5		T4	13		T8	2
valid_sources[0x68]	50013	1			T3	8		T4	12		T5	9
valid_sources[0x69]	50540	1			T3	6		T4	17		T5	5
valid_sources[0x6a]	49709	1			T3	3		T4	18		T5	2
valid_sources[0x6b]	49647	1			T3	1		T4	10		T5	1
valid_sources[0x6c]	50323	1			T3	14		T4	17		T5	5
valid_sources[0x6d]	51498	1			T3	1		T4	18		T5	6
valid_sources[0x6e]	47885	1			T3	4		T4	16		T5	4
valid_sources[0x6f]	50544	1			T2	81		T3	5		T4	9
valid_sources[0x70]	50118	1			T3	7		T4	15		T5	1
valid_sources[0x71]	51536	1			T2	1		T3	2		T4	16
valid_sources[0x72]	55534	1			T3	4		T4	15		T5	8
valid_sources[0x73]	49198	1			T3	8		T4	12		T5	1
valid_sources[0x74]	50570	1			T3	2		T4	10		T5	2
valid_sources[0x75]	52543	1			T3	1		T4	20		T5	10
valid_sources[0x76]	50613	1			T3	1		T4	12		T8	3
valid_sources[0x77]	49279	1			T3	3		T4	21		T5	3
valid_sources[0x78]	51530	1			T3	7		T4	16		T5	7
valid_sources[0x79]	53027	1			T3	2		T4	13		T5	3
valid_sources[0x7a]	54554	1			T3	4		T4	8		T5	7
valid_sources[0x7b]	48227	1			T3	3		T4	15		T5	1
valid_sources[0x7c]	45914	1			T3	5		T4	7		T5	3
valid_sources[0x7d]	52531	1			T3	7		T4	15		T5	2
valid_sources[0x7e]	51841	1			T3	6		T4	15		T5	2
valid_sources[0x7f]	49763	1			T3	6		T4	16		T5	4
valid_sources[0x80]	49228	1			T4	14		T5	6		T8	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

2580739

1

T1

1

T2

225

T3

15

values[0x0]

all_enables

biggest_size

2114885

1

T2

436

T3

485

T4

1306

values[0x1]

all_enables

biggest_size

2082850

1

T1

2

T2

463

T3

442