Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

6404600

1

T1

2

T2

94

T3

62

full_word

6777759

1

T1

3

T2

1124

T3

942

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	13181899	1			T1	5		T2	1218		T3	1004
auto[TlIntgErrCmd]	159	1			T103	11		T106	11		T107	8
auto[TlIntgErrData]	146	1			T103	8		T106	10		T107	8
auto[TlIntgErrBoth]	155	1			T103	11		T106	9		T107	14

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8469622

1

T1

1

T2

314

T3

71

auto[1]

4712737

1

T1

4

T2

904

T3

933

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	5888517	1			T2	89		T3	56		T4	516
auto[TlIntgErrNone]	partial	auto[1]	515657	1			T1	2		T2	5		T3	6
auto[TlIntgErrNone]	full_word	auto[0]	2580887	1			T1	1		T2	225		T3	15
auto[TlIntgErrNone]	full_word	auto[1]	4196838	1			T1	2		T2	899		T3	927
auto[TlIntgErrCmd]	partial	auto[0]	62	1			T103	4		T106	3		T107	1
auto[TlIntgErrCmd]	partial	auto[1]	85	1			T103	6		T106	7		T107	6
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T188	1		T115	1		T190	2
auto[TlIntgErrCmd]	full_word	auto[1]	8	1			T103	1		T106	1		T107	1
auto[TlIntgErrData]	partial	auto[0]	78	1			T103	4		T106	5		T107	4
auto[TlIntgErrData]	partial	auto[1]	57	1			T103	4		T106	4		T107	3
auto[TlIntgErrData]	full_word	auto[0]	3	1			T188	1		T191	1		T119	1
auto[TlIntgErrData]	full_word	auto[1]	8	1			T106	1		T107	1		T188	1
auto[TlIntgErrBoth]	partial	auto[0]	63	1			T103	2		T106	2		T107	8
auto[TlIntgErrBoth]	partial	auto[1]	81	1			T103	8		T106	5		T107	5
auto[TlIntgErrBoth]	full_word	auto[0]	8	1			T103	1		T106	1		T107	1
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T106	1		T192	2		-	-