Module Definition
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Module : prim_generic_ram_2p
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_2p_0/rtl/prim_generic_ram_2p.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_mem


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : prim_generic_ram_2p
Line No.TotalCoveredPercent
TOTAL2121100.00
CONT_ASSIGN4911100.00
CONT_ASSIGN6011100.00
CONT_ASSIGN6011100.00
CONT_ASSIGN6011100.00
CONT_ASSIGN6011100.00
CONT_ASSIGN6111100.00
CONT_ASSIGN6111100.00
CONT_ASSIGN6111100.00
CONT_ASSIGN6111100.00
ALWAYS7666100.00
ALWAYS9166100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_2p_0/rtl/prim_generic_ram_2p.sv' or '../src/lowrisc_prim_generic_ram_2p_0/rtl/prim_generic_ram_2p.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
49 1 1
60 4 4
61 4 4
76 1 1
77 1 1
78 1 1
79 1 1
80 1 1
==> MISSING_ELSE
85 1 1
MISSING_ELSE
91 1 1
92 1 1
93 1 1
94 1 1
95 1 1
MISSING_ELSE
100 1 1
MISSING_ELSE


Branch Coverage for Module : prim_generic_ram_2p
Line No.TotalCoveredPercent
Branches 6 6 100.00
IF 76 3 3 100.00
IF 91 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_2p_0/rtl/prim_generic_ram_2p.sv' or '../src/lowrisc_prim_generic_ram_2p_0/rtl/prim_generic_ram_2p.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 76 if (a_req_i) -2-: 77 if (a_write_i)

Branches:
-1--2-StatusTests
1 1 Covered T2,T3,T4
1 0 Covered T2,T7,T9
0 - Covered T1,T2,T3


LineNo. Expression -1-: 91 if (b_req_i) -2-: 92 if (b_write_i)

Branches:
-1--2-StatusTests
1 1 Covered T2,T7,T9
1 0 Covered T2,T4,T5
0 - Covered T1,T2,T3


Assert Coverage for Module : prim_generic_ram_2p
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 8 8 100.00 8 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 8 8 100.00 8 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_wmask[0].MaskCheckPortA_A 577462541 2585856 0 0
gen_wmask[0].MaskCheckPortB_A 190835312 1274838 0 0
gen_wmask[1].MaskCheckPortA_A 577462541 2585856 0 0
gen_wmask[1].MaskCheckPortB_A 190835312 1274838 0 0
gen_wmask[2].MaskCheckPortA_A 577462541 2585856 0 0
gen_wmask[2].MaskCheckPortB_A 190835312 1274838 0 0
gen_wmask[3].MaskCheckPortA_A 577462541 2585856 0 0
gen_wmask[3].MaskCheckPortB_A 190835312 1274838 0 0


gen_wmask[0].MaskCheckPortA_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 577462541 2585856 0 0
T2 121054 832 0 0
T3 288370 832 0 0
T4 116540 2624 0 0
T5 10599 832 0 0
T6 39508 0 0 0
T7 5337 23 0 0
T8 59916 832 0 0
T9 307521 10816 0 0
T10 38001 832 0 0
T11 538743 9155 0 0
T12 0 832 0 0

gen_wmask[0].MaskCheckPortB_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 190835312 1274838 0 0
T2 99678 516 0 0
T3 41349 0 0 0
T4 110688 0 0 0
T5 21341 0 0 0
T6 102617 0 0 0
T7 1432 25 0 0
T8 56992 0 0 0
T9 396939 3986 0 0
T10 4256 0 0 0
T11 471336 5198 0 0
T16 0 1028 0 0
T17 0 5643 0 0
T22 0 520 0 0
T29 0 17 0 0
T30 0 5805 0 0
T31 0 6031 0 0

gen_wmask[1].MaskCheckPortA_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 577462541 2585856 0 0
T2 121054 832 0 0
T3 288370 832 0 0
T4 116540 2624 0 0
T5 10599 832 0 0
T6 39508 0 0 0
T7 5337 23 0 0
T8 59916 832 0 0
T9 307521 10816 0 0
T10 38001 832 0 0
T11 538743 9155 0 0
T12 0 832 0 0

gen_wmask[1].MaskCheckPortB_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 190835312 1274838 0 0
T2 99678 516 0 0
T3 41349 0 0 0
T4 110688 0 0 0
T5 21341 0 0 0
T6 102617 0 0 0
T7 1432 25 0 0
T8 56992 0 0 0
T9 396939 3986 0 0
T10 4256 0 0 0
T11 471336 5198 0 0
T16 0 1028 0 0
T17 0 5643 0 0
T22 0 520 0 0
T29 0 17 0 0
T30 0 5805 0 0
T31 0 6031 0 0

gen_wmask[2].MaskCheckPortA_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 577462541 2585856 0 0
T2 121054 832 0 0
T3 288370 832 0 0
T4 116540 2624 0 0
T5 10599 832 0 0
T6 39508 0 0 0
T7 5337 23 0 0
T8 59916 832 0 0
T9 307521 10816 0 0
T10 38001 832 0 0
T11 538743 9155 0 0
T12 0 832 0 0

gen_wmask[2].MaskCheckPortB_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 190835312 1274838 0 0
T2 99678 516 0 0
T3 41349 0 0 0
T4 110688 0 0 0
T5 21341 0 0 0
T6 102617 0 0 0
T7 1432 25 0 0
T8 56992 0 0 0
T9 396939 3986 0 0
T10 4256 0 0 0
T11 471336 5198 0 0
T16 0 1028 0 0
T17 0 5643 0 0
T22 0 520 0 0
T29 0 17 0 0
T30 0 5805 0 0
T31 0 6031 0 0

gen_wmask[3].MaskCheckPortA_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 577462541 2585856 0 0
T2 121054 832 0 0
T3 288370 832 0 0
T4 116540 2624 0 0
T5 10599 832 0 0
T6 39508 0 0 0
T7 5337 23 0 0
T8 59916 832 0 0
T9 307521 10816 0 0
T10 38001 832 0 0
T11 538743 9155 0 0
T12 0 832 0 0

gen_wmask[3].MaskCheckPortB_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 190835312 1274838 0 0
T2 99678 516 0 0
T3 41349 0 0 0
T4 110688 0 0 0
T5 21341 0 0 0
T6 102617 0 0 0
T7 1432 25 0 0
T8 56992 0 0 0
T9 396939 3986 0 0
T10 4256 0 0 0
T11 471336 5198 0 0
T16 0 1028 0 0
T17 0 5643 0 0
T22 0 520 0 0
T29 0 17 0 0
T30 0 5805 0 0
T31 0 6031 0 0

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