Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T11,T16
1	0	Covered	T7,T11,T16

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T7
1	0	Unreachable
1	1	Covered	T7,T11,T16

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T9,T11

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T9,T11
1	0	Covered	T2,T9,T11

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Unreachable
1	1	Covered	T2,T9,T11

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T7,T9

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T7,T9
1	0	Covered	T2,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T2,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T7,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T4
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	959133165	766292104	0	0
CheckNGreaterZero_A	2814	2814	0	0
GntImpliesReady_A	959133165	4414635	0	0
GntImpliesValid_A	959133165	4414635	0	0
GrantKnown_A	959133165	766292104	0	0
IdxKnown_A	959133165	766292104	0	0
IndexIsCorrect_A	959133165	4414635	0	0
LockArbDecision_A	959133165	0	0	0
NoReadyValidNoGrant_A	959133165	0	0	0
ReadyAndValidImplyGrant_A	959133165	4414635	0	0
ReqAndReadyImplyGrant_A	959133165	4414635	0	0
ReqImpliesValid_A	959133165	4414635	0	0
ReqStaysHighUntilGranted0_M	959133165	0	0	0
RoundRobin_A	959133165	3	0	938
ValidKnown_A	959133165	766292104	0	0
gen_data_port_assertion.DataFlow_A	959133165	4414635	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	959133165	766292104	0	0
T1	1416	1359	0	0
T2	320410	219920	0	0
T3	371068	328340	0	0
T4	337916	226547	0	0
T5	53281	31883	0	0
T6	244742	138800	0	0
T7	8201	6704	0	0
T8	173900	116821	0	0
T9	1101399	700701	0	0
T10	46513	42190	0	0
T11	471336	464465	0	0
T12	0	42590	0	0
T13	0	135368	0	0
T14	0	8600	0	0
T15	0	1440	0	0
T16	0	38296	0	0
T17	0	610376	0	0
T18	0	64880	0	0
T19	0	70896	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2814	2814	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	959133165	4414635	0	0
T2	220732	1480	0	0
T3	329719	832	0	0
T4	227228	2624	0	0
T5	31940	832	0	0
T6	142125	0	0	0
T7	8201	84	0	0
T8	173900	832	0	0
T9	1101399	15211	0	0
T10	46513	832	0	0
T11	1481415	17392	0	0
T12	43312	832	0	0
T13	135693	0	0	0
T14	8663	0	0	0
T15	1994	0	0	0
T16	39335	1451	0	0
T17	0	8028	0	0
T22	0	520	0	0
T29	0	17	0	0
T30	0	7195	0	0
T31	0	8987	0	0
T36	0	4	0	0
T51	0	6027	0	0
T54	0	564	0	0
T55	0	7225	0	0
T56	0	116	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	959133165	4414635	0	0
T2	220732	1480	0	0
T3	329719	832	0	0
T4	227228	2624	0	0
T5	31940	832	0	0
T6	142125	0	0	0
T7	8201	84	0	0
T8	173900	832	0	0
T9	1101399	15211	0	0
T10	46513	832	0	0
T11	1481415	17392	0	0
T12	43312	832	0	0
T13	135693	0	0	0
T14	8663	0	0	0
T15	1994	0	0	0
T16	39335	1451	0	0
T17	0	8028	0	0
T22	0	520	0	0
T29	0	17	0	0
T30	0	7195	0	0
T31	0	8987	0	0
T36	0	4	0	0
T51	0	6027	0	0
T54	0	564	0	0
T55	0	7225	0	0
T56	0	116	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	959133165	766292104	0	0
T1	1416	1359	0	0
T2	320410	219920	0	0
T3	371068	328340	0	0
T4	337916	226547	0	0
T5	53281	31883	0	0
T6	244742	138800	0	0
T7	8201	6704	0	0
T8	173900	116821	0	0
T9	1101399	700701	0	0
T10	46513	42190	0	0
T11	471336	464465	0	0
T12	0	42590	0	0
T13	0	135368	0	0
T14	0	8600	0	0
T15	0	1440	0	0
T16	0	38296	0	0
T17	0	610376	0	0
T18	0	64880	0	0
T19	0	70896	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	959133165	766292104	0	0
T1	1416	1359	0	0
T2	320410	219920	0	0
T3	371068	328340	0	0
T4	337916	226547	0	0
T5	53281	31883	0	0
T6	244742	138800	0	0
T7	8201	6704	0	0
T8	173900	116821	0	0
T9	1101399	700701	0	0
T10	46513	42190	0	0
T11	471336	464465	0	0
T12	0	42590	0	0
T13	0	135368	0	0
T14	0	8600	0	0
T15	0	1440	0	0
T16	0	38296	0	0
T17	0	610376	0	0
T18	0	64880	0	0
T19	0	70896	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	959133165	4414635	0	0
T2	220732	1480	0	0
T3	329719	832	0	0
T4	227228	2624	0	0
T5	31940	832	0	0
T6	142125	0	0	0
T7	8201	84	0	0
T8	173900	832	0	0
T9	1101399	15211	0	0
T10	46513	832	0	0
T11	1481415	17392	0	0
T12	43312	832	0	0
T13	135693	0	0	0
T14	8663	0	0	0
T15	1994	0	0	0
T16	39335	1451	0	0
T17	0	8028	0	0
T22	0	520	0	0
T29	0	17	0	0
T30	0	7195	0	0
T31	0	8987	0	0
T36	0	4	0	0
T51	0	6027	0	0
T54	0	564	0	0
T55	0	7225	0	0
T56	0	116	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	959133165	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	959133165	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	959133165	4414635	0	0
T2	220732	1480	0	0
T3	329719	832	0	0
T4	227228	2624	0	0
T5	31940	832	0	0
T6	142125	0	0	0
T7	8201	84	0	0
T8	173900	832	0	0
T9	1101399	15211	0	0
T10	46513	832	0	0
T11	1481415	17392	0	0
T12	43312	832	0	0
T13	135693	0	0	0
T14	8663	0	0	0
T15	1994	0	0	0
T16	39335	1451	0	0
T17	0	8028	0	0
T22	0	520	0	0
T29	0	17	0	0
T30	0	7195	0	0
T31	0	8987	0	0
T36	0	4	0	0
T51	0	6027	0	0
T54	0	564	0	0
T55	0	7225	0	0
T56	0	116	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	959133165	4414635	0	0
T2	220732	1480	0	0
T3	329719	832	0	0
T4	227228	2624	0	0
T5	31940	832	0	0
T6	142125	0	0	0
T7	8201	84	0	0
T8	173900	832	0	0
T9	1101399	15211	0	0
T10	46513	832	0	0
T11	1481415	17392	0	0
T12	43312	832	0	0
T13	135693	0	0	0
T14	8663	0	0	0
T15	1994	0	0	0
T16	39335	1451	0	0
T17	0	8028	0	0
T22	0	520	0	0
T29	0	17	0	0
T30	0	7195	0	0
T31	0	8987	0	0
T36	0	4	0	0
T51	0	6027	0	0
T54	0	564	0	0
T55	0	7225	0	0
T56	0	116	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	959133165	4414635	0	0
T2	220732	1480	0	0
T3	329719	832	0	0
T4	227228	2624	0	0
T5	31940	832	0	0
T6	142125	0	0	0
T7	8201	84	0	0
T8	173900	832	0	0
T9	1101399	15211	0	0
T10	46513	832	0	0
T11	1481415	17392	0	0
T12	43312	832	0	0
T13	135693	0	0	0
T14	8663	0	0	0
T15	1994	0	0	0
T16	39335	1451	0	0
T17	0	8028	0	0
T22	0	520	0	0
T29	0	17	0	0
T30	0	7195	0	0
T31	0	8987	0	0
T36	0	4	0	0
T51	0	6027	0	0
T54	0	564	0	0
T55	0	7225	0	0
T56	0	116	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	959133165	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	959133165	3	0	938
T57	403296	1	0	1
T58	0	1	0	0
T59	0	1	0	0
T60	118313	0	0	1
T61	78327	0	0	1
T62	513430	0	0	1
T63	329941	0	0	1
T64	7744	0	0	1
T65	643534	0	0	1
T66	2495	0	0	1
T67	256995	0	0	1
T68	3451	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	959133165	766292104	0	0
T1	1416	1359	0	0
T2	320410	219920	0	0
T3	371068	328340	0	0
T4	337916	226547	0	0
T5	53281	31883	0	0
T6	244742	138800	0	0
T7	8201	6704	0	0
T8	173900	116821	0	0
T9	1101399	700701	0	0
T10	46513	42190	0	0
T11	471336	464465	0	0
T12	0	42590	0	0
T13	0	135368	0	0
T14	0	8600	0	0
T15	0	1440	0	0
T16	0	38296	0	0
T17	0	610376	0	0
T18	0	64880	0	0
T19	0	70896	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	959133165	4414635	0	0
T2	220732	1480	0	0
T3	329719	832	0	0
T4	227228	2624	0	0
T5	31940	832	0	0
T6	142125	0	0	0
T7	8201	84	0	0
T8	173900	832	0	0
T9	1101399	15211	0	0
T10	46513	832	0	0
T11	1481415	17392	0	0
T12	43312	832	0	0
T13	135693	0	0	0
T14	8663	0	0	0
T15	1994	0	0	0
T16	39335	1451	0	0
T17	0	8028	0	0
T22	0	520	0	0
T29	0	17	0	0
T30	0	7195	0	0
T31	0	8987	0	0
T36	0	4	0	0
T51	0	6027	0	0
T54	0	564	0	0
T55	0	7225	0	0
T56	0	116	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T11,T16
1	0	Covered	T7,T11,T16

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T7
1	0	Unreachable
1	1	Covered	T7,T11,T16

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T7,T11,T16
0	0	1	Unreachable
0	0	0	Covered	T1,T6,T7

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T7,T11,T16
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T7,T11,T16
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	190835312	45074144	0	0
CheckNGreaterZero_A	938	938	0	0
GntImpliesReady_A	190835312	982079	0	0
GntImpliesValid_A	190835312	982079	0	0
GrantKnown_A	190835312	45074144	0	0
IdxKnown_A	190835312	45074144	0	0
IndexIsCorrect_A	190835312	982079	0	0
LockArbDecision_A	190835312	0	0	0
NoReadyValidNoGrant_A	190835312	0	0	0
ReadyAndValidImplyGrant_A	190835312	982079	0	0
ReqAndReadyImplyGrant_A	190835312	982079	0	0
ReqImpliesValid_A	190835312	982079	0	0
ReqStaysHighUntilGranted0_M	190835312	0	0	0
RoundRobin_A	190835312	0	0	0
ValidKnown_A	190835312	45074144	0	0
gen_data_port_assertion.DataFlow_A	190835312	982079	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	190835312	45074144	0	0
T1	72	72	0	0
T2	99678	0	0	0
T3	41349	0	0	0
T4	110688	0	0	0
T5	21341	0	0	0
T6	102617	99392	0	0
T7	1432	1432	0	0
T8	56992	0	0	0
T9	396939	0	0	0
T10	4256	0	0	0
T11	0	203088	0	0
T14	0	8600	0	0
T15	0	1440	0	0
T16	0	38296	0	0
T17	0	610376	0	0
T18	0	64880	0	0
T19	0	70896	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	938	938	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	190835312	982079	0	0
T7	1432	54	0	0
T8	56992	0	0	0
T9	396939	0	0	0
T10	4256	0	0	0
T11	471336	4781	0	0
T12	43312	0	0	0
T13	135693	0	0	0
T14	8663	0	0	0
T15	1994	0	0	0
T16	39335	1451	0	0
T17	0	8010	0	0
T30	0	4026	0	0
T31	0	8599	0	0
T51	0	3583	0	0
T54	0	564	0	0
T55	0	7225	0	0
T56	0	116	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	190835312	982079	0	0
T7	1432	54	0	0
T8	56992	0	0	0
T9	396939	0	0	0
T10	4256	0	0	0
T11	471336	4781	0	0
T12	43312	0	0	0
T13	135693	0	0	0
T14	8663	0	0	0
T15	1994	0	0	0
T16	39335	1451	0	0
T17	0	8010	0	0
T30	0	4026	0	0
T31	0	8599	0	0
T51	0	3583	0	0
T54	0	564	0	0
T55	0	7225	0	0
T56	0	116	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	190835312	45074144	0	0
T1	72	72	0	0
T2	99678	0	0	0
T3	41349	0	0	0
T4	110688	0	0	0
T5	21341	0	0	0
T6	102617	99392	0	0
T7	1432	1432	0	0
T8	56992	0	0	0
T9	396939	0	0	0
T10	4256	0	0	0
T11	0	203088	0	0
T14	0	8600	0	0
T15	0	1440	0	0
T16	0	38296	0	0
T17	0	610376	0	0
T18	0	64880	0	0
T19	0	70896	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	190835312	45074144	0	0
T1	72	72	0	0
T2	99678	0	0	0
T3	41349	0	0	0
T4	110688	0	0	0
T5	21341	0	0	0
T6	102617	99392	0	0
T7	1432	1432	0	0
T8	56992	0	0	0
T9	396939	0	0	0
T10	4256	0	0	0
T11	0	203088	0	0
T14	0	8600	0	0
T15	0	1440	0	0
T16	0	38296	0	0
T17	0	610376	0	0
T18	0	64880	0	0
T19	0	70896	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	190835312	982079	0	0
T7	1432	54	0	0
T8	56992	0	0	0
T9	396939	0	0	0
T10	4256	0	0	0
T11	471336	4781	0	0
T12	43312	0	0	0
T13	135693	0	0	0
T14	8663	0	0	0
T15	1994	0	0	0
T16	39335	1451	0	0
T17	0	8010	0	0
T30	0	4026	0	0
T31	0	8599	0	0
T51	0	3583	0	0
T54	0	564	0	0
T55	0	7225	0	0
T56	0	116	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	190835312	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	190835312	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	190835312	982079	0	0
T7	1432	54	0	0
T8	56992	0	0	0
T9	396939	0	0	0
T10	4256	0	0	0
T11	471336	4781	0	0
T12	43312	0	0	0
T13	135693	0	0	0
T14	8663	0	0	0
T15	1994	0	0	0
T16	39335	1451	0	0
T17	0	8010	0	0
T30	0	4026	0	0
T31	0	8599	0	0
T51	0	3583	0	0
T54	0	564	0	0
T55	0	7225	0	0
T56	0	116	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	190835312	982079	0	0
T7	1432	54	0	0
T8	56992	0	0	0
T9	396939	0	0	0
T10	4256	0	0	0
T11	471336	4781	0	0
T12	43312	0	0	0
T13	135693	0	0	0
T14	8663	0	0	0
T15	1994	0	0	0
T16	39335	1451	0	0
T17	0	8010	0	0
T30	0	4026	0	0
T31	0	8599	0	0
T51	0	3583	0	0
T54	0	564	0	0
T55	0	7225	0	0
T56	0	116	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	190835312	982079	0	0
T7	1432	54	0	0
T8	56992	0	0	0
T9	396939	0	0	0
T10	4256	0	0	0
T11	471336	4781	0	0
T12	43312	0	0	0
T13	135693	0	0	0
T14	8663	0	0	0
T15	1994	0	0	0
T16	39335	1451	0	0
T17	0	8010	0	0
T30	0	4026	0	0
T31	0	8599	0	0
T51	0	3583	0	0
T54	0	564	0	0
T55	0	7225	0	0
T56	0	116	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	190835312	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	190835312	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	190835312	45074144	0	0
T1	72	72	0	0
T2	99678	0	0	0
T3	41349	0	0	0
T4	110688	0	0	0
T5	21341	0	0	0
T6	102617	99392	0	0
T7	1432	1432	0	0
T8	56992	0	0	0
T9	396939	0	0	0
T10	4256	0	0	0
T11	0	203088	0	0
T14	0	8600	0	0
T15	0	1440	0	0
T16	0	38296	0	0
T17	0	610376	0	0
T18	0	64880	0	0
T19	0	70896	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	190835312	982079	0	0
T7	1432	54	0	0
T8	56992	0	0	0
T9	396939	0	0	0
T10	4256	0	0	0
T11	471336	4781	0	0
T12	43312	0	0	0
T13	135693	0	0	0
T14	8663	0	0	0
T15	1994	0	0	0
T16	39335	1451	0	0
T17	0	8010	0	0
T30	0	4026	0	0
T31	0	8599	0	0
T51	0	3583	0	0
T54	0	564	0	0
T55	0	7225	0	0
T56	0	116	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T9,T11

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T9,T11
1	0	Covered	T2,T9,T11

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Unreachable
1	1	Covered	T2,T9,T11

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T9,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T9,T11
0	0	1	Unreachable
0	0	0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T9,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T9,T11
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	190835312	143836975	0	0
CheckNGreaterZero_A	938	938	0	0
GntImpliesReady_A	190835312	617912	0	0
GntImpliesValid_A	190835312	617912	0	0
GrantKnown_A	190835312	143836975	0	0
IdxKnown_A	190835312	143836975	0	0
IndexIsCorrect_A	190835312	617912	0	0
LockArbDecision_A	190835312	0	0	0
NoReadyValidNoGrant_A	190835312	0	0	0
ReadyAndValidImplyGrant_A	190835312	617912	0	0
ReqAndReadyImplyGrant_A	190835312	617912	0	0
ReqImpliesValid_A	190835312	617912	0	0
ReqStaysHighUntilGranted0_M	190835312	0	0	0
RoundRobin_A	190835312	0	0	0
ValidKnown_A	190835312	143836975	0	0
gen_data_port_assertion.DataFlow_A	190835312	617912	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	190835312	143836975	0	0
T2	99678	98958	0	0
T3	41349	40064	0	0
T4	110688	110088	0	0
T5	21341	21341	0	0
T6	102617	0	0	0
T7	1432	0	0	0
T8	56992	56992	0	0
T9	396939	393270	0	0
T10	4256	4256	0	0
T11	471336	261377	0	0
T12	0	42590	0	0
T13	0	135368	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	938	938	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	190835312	617912	0	0
T2	99678	516	0	0
T3	41349	0	0	0
T4	110688	0	0	0
T5	21341	0	0	0
T6	102617	0	0	0
T7	1432	0	0	0
T8	56992	0	0	0
T9	396939	3986	0	0
T10	4256	0	0	0
T11	471336	2243	0	0
T17	0	18	0	0
T22	0	520	0	0
T29	0	17	0	0
T30	0	3169	0	0
T31	0	388	0	0
T36	0	4	0	0
T51	0	2444	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	190835312	617912	0	0
T2	99678	516	0	0
T3	41349	0	0	0
T4	110688	0	0	0
T5	21341	0	0	0
T6	102617	0	0	0
T7	1432	0	0	0
T8	56992	0	0	0
T9	396939	3986	0	0
T10	4256	0	0	0
T11	471336	2243	0	0
T17	0	18	0	0
T22	0	520	0	0
T29	0	17	0	0
T30	0	3169	0	0
T31	0	388	0	0
T36	0	4	0	0
T51	0	2444	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	190835312	143836975	0	0
T2	99678	98958	0	0
T3	41349	40064	0	0
T4	110688	110088	0	0
T5	21341	21341	0	0
T6	102617	0	0	0
T7	1432	0	0	0
T8	56992	56992	0	0
T9	396939	393270	0	0
T10	4256	4256	0	0
T11	471336	261377	0	0
T12	0	42590	0	0
T13	0	135368	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	190835312	143836975	0	0
T2	99678	98958	0	0
T3	41349	40064	0	0
T4	110688	110088	0	0
T5	21341	21341	0	0
T6	102617	0	0	0
T7	1432	0	0	0
T8	56992	56992	0	0
T9	396939	393270	0	0
T10	4256	4256	0	0
T11	471336	261377	0	0
T12	0	42590	0	0
T13	0	135368	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	190835312	617912	0	0
T2	99678	516	0	0
T3	41349	0	0	0
T4	110688	0	0	0
T5	21341	0	0	0
T6	102617	0	0	0
T7	1432	0	0	0
T8	56992	0	0	0
T9	396939	3986	0	0
T10	4256	0	0	0
T11	471336	2243	0	0
T17	0	18	0	0
T22	0	520	0	0
T29	0	17	0	0
T30	0	3169	0	0
T31	0	388	0	0
T36	0	4	0	0
T51	0	2444	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	190835312	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	190835312	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	190835312	617912	0	0
T2	99678	516	0	0
T3	41349	0	0	0
T4	110688	0	0	0
T5	21341	0	0	0
T6	102617	0	0	0
T7	1432	0	0	0
T8	56992	0	0	0
T9	396939	3986	0	0
T10	4256	0	0	0
T11	471336	2243	0	0
T17	0	18	0	0
T22	0	520	0	0
T29	0	17	0	0
T30	0	3169	0	0
T31	0	388	0	0
T36	0	4	0	0
T51	0	2444	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	190835312	617912	0	0
T2	99678	516	0	0
T3	41349	0	0	0
T4	110688	0	0	0
T5	21341	0	0	0
T6	102617	0	0	0
T7	1432	0	0	0
T8	56992	0	0	0
T9	396939	3986	0	0
T10	4256	0	0	0
T11	471336	2243	0	0
T17	0	18	0	0
T22	0	520	0	0
T29	0	17	0	0
T30	0	3169	0	0
T31	0	388	0	0
T36	0	4	0	0
T51	0	2444	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	190835312	617912	0	0
T2	99678	516	0	0
T3	41349	0	0	0
T4	110688	0	0	0
T5	21341	0	0	0
T6	102617	0	0	0
T7	1432	0	0	0
T8	56992	0	0	0
T9	396939	3986	0	0
T10	4256	0	0	0
T11	471336	2243	0	0
T17	0	18	0	0
T22	0	520	0	0
T29	0	17	0	0
T30	0	3169	0	0
T31	0	388	0	0
T36	0	4	0	0
T51	0	2444	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	190835312	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	190835312	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	190835312	143836975	0	0
T2	99678	98958	0	0
T3	41349	40064	0	0
T4	110688	110088	0	0
T5	21341	21341	0	0
T6	102617	0	0	0
T7	1432	0	0	0
T8	56992	56992	0	0
T9	396939	393270	0	0
T10	4256	4256	0	0
T11	471336	261377	0	0
T12	0	42590	0	0
T13	0	135368	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	190835312	617912	0	0
T2	99678	516	0	0
T3	41349	0	0	0
T4	110688	0	0	0
T5	21341	0	0	0
T6	102617	0	0	0
T7	1432	0	0	0
T8	56992	0	0	0
T9	396939	3986	0	0
T10	4256	0	0	0
T11	471336	2243	0	0
T17	0	18	0	0
T22	0	520	0	0
T29	0	17	0	0
T30	0	3169	0	0
T31	0	388	0	0
T36	0	4	0	0
T51	0	2444	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T7,T9

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T7,T9
1	0	Covered	T2,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T2,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T7,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T4
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	577462541	577380985	0	0
CheckNGreaterZero_A	938	938	0	0
GntImpliesReady_A	577462541	2814644	0	0
GntImpliesValid_A	577462541	2814644	0	0
GrantKnown_A	577462541	577380985	0	0
IdxKnown_A	577462541	577380985	0	0
IndexIsCorrect_A	577462541	2814644	0	0
LockArbDecision_A	577462541	0	0	0
NoReadyValidNoGrant_A	577462541	0	0	0
ReadyAndValidImplyGrant_A	577462541	2814644	0	0
ReqAndReadyImplyGrant_A	577462541	2814644	0	0
ReqImpliesValid_A	577462541	2814644	0	0
ReqStaysHighUntilGranted0_M	577462541	0	0	0
RoundRobin_A	577462541	3	0	938
ValidKnown_A	577462541	577380985	0	0
gen_data_port_assertion.DataFlow_A	577462541	2814644	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577462541	577380985	0	0
T1	1344	1287	0	0
T2	121054	120962	0	0
T3	288370	288276	0	0
T4	116540	116459	0	0
T5	10599	10542	0	0
T6	39508	39408	0	0
T7	5337	5272	0	0
T8	59916	59829	0	0
T9	307521	307431	0	0
T10	38001	37934	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	938	938	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577462541	2814644	0	0
T2	121054	964	0	0
T3	288370	832	0	0
T4	116540	2624	0	0
T5	10599	832	0	0
T6	39508	0	0	0
T7	5337	30	0	0
T8	59916	832	0	0
T9	307521	11225	0	0
T10	38001	832	0	0
T11	538743	10368	0	0
T12	0	832	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577462541	2814644	0	0
T2	121054	964	0	0
T3	288370	832	0	0
T4	116540	2624	0	0
T5	10599	832	0	0
T6	39508	0	0	0
T7	5337	30	0	0
T8	59916	832	0	0
T9	307521	11225	0	0
T10	38001	832	0	0
T11	538743	10368	0	0
T12	0	832	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577462541	577380985	0	0
T1	1344	1287	0	0
T2	121054	120962	0	0
T3	288370	288276	0	0
T4	116540	116459	0	0
T5	10599	10542	0	0
T6	39508	39408	0	0
T7	5337	5272	0	0
T8	59916	59829	0	0
T9	307521	307431	0	0
T10	38001	37934	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577462541	577380985	0	0
T1	1344	1287	0	0
T2	121054	120962	0	0
T3	288370	288276	0	0
T4	116540	116459	0	0
T5	10599	10542	0	0
T6	39508	39408	0	0
T7	5337	5272	0	0
T8	59916	59829	0	0
T9	307521	307431	0	0
T10	38001	37934	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577462541	2814644	0	0
T2	121054	964	0	0
T3	288370	832	0	0
T4	116540	2624	0	0
T5	10599	832	0	0
T6	39508	0	0	0
T7	5337	30	0	0
T8	59916	832	0	0
T9	307521	11225	0	0
T10	38001	832	0	0
T11	538743	10368	0	0
T12	0	832	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577462541	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577462541	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577462541	2814644	0	0
T2	121054	964	0	0
T3	288370	832	0	0
T4	116540	2624	0	0
T5	10599	832	0	0
T6	39508	0	0	0
T7	5337	30	0	0
T8	59916	832	0	0
T9	307521	11225	0	0
T10	38001	832	0	0
T11	538743	10368	0	0
T12	0	832	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577462541	2814644	0	0
T2	121054	964	0	0
T3	288370	832	0	0
T4	116540	2624	0	0
T5	10599	832	0	0
T6	39508	0	0	0
T7	5337	30	0	0
T8	59916	832	0	0
T9	307521	11225	0	0
T10	38001	832	0	0
T11	538743	10368	0	0
T12	0	832	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577462541	2814644	0	0
T2	121054	964	0	0
T3	288370	832	0	0
T4	116540	2624	0	0
T5	10599	832	0	0
T6	39508	0	0	0
T7	5337	30	0	0
T8	59916	832	0	0
T9	307521	11225	0	0
T10	38001	832	0	0
T11	538743	10368	0	0
T12	0	832	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	577462541	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577462541	3	0	938
T57	403296	1	0	1
T58	0	1	0	0
T59	0	1	0	0
T60	118313	0	0	1
T61	78327	0	0	1
T62	513430	0	0	1
T63	329941	0	0	1
T64	7744	0	0	1
T65	643534	0	0	1
T66	2495	0	0	1
T67	256995	0	0	1
T68	3451	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577462541	577380985	0	0
T1	1344	1287	0	0
T2	121054	120962	0	0
T3	288370	288276	0	0
T4	116540	116459	0	0
T5	10599	10542	0	0
T6	39508	39408	0	0
T7	5337	5272	0	0
T8	59916	59829	0	0
T9	307521	307431	0	0
T10	38001	37934	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577462541	2814644	0	0
T2	121054	964	0	0
T3	288370	832	0	0
T4	116540	2624	0	0
T5	10599	832	0	0
T6	39508	0	0	0
T7	5337	30	0	0
T8	59916	832	0	0
T9	307521	11225	0	0
T10	38001	832	0	0
T11	538743	10368	0	0
T12	0	832	0	0