| T814 |
/workspace/coverage/default/26.spi_device_mailbox.1574313941 |
|
|
Mar 21 02:25:33 PM PDT 24 |
Mar 21 02:25:42 PM PDT 24 |
1874022779 ps |
| T815 |
/workspace/coverage/default/37.spi_device_cfg_cmd.2663267099 |
|
|
Mar 21 02:26:31 PM PDT 24 |
Mar 21 02:26:33 PM PDT 24 |
147684674 ps |
| T816 |
/workspace/coverage/default/19.spi_device_flash_all.2936622304 |
|
|
Mar 21 02:25:09 PM PDT 24 |
Mar 21 02:26:48 PM PDT 24 |
16995016444 ps |
| T817 |
/workspace/coverage/default/14.spi_device_flash_all.228527907 |
|
|
Mar 21 02:24:28 PM PDT 24 |
Mar 21 02:25:46 PM PDT 24 |
30126369226 ps |
| T59 |
/workspace/coverage/default/36.spi_device_stress_all.3992494146 |
|
|
Mar 21 02:26:27 PM PDT 24 |
Mar 21 02:33:27 PM PDT 24 |
60570137941 ps |
| T818 |
/workspace/coverage/default/0.spi_device_cfg_cmd.1152973435 |
|
|
Mar 21 02:23:05 PM PDT 24 |
Mar 21 02:23:10 PM PDT 24 |
490734747 ps |
| T819 |
/workspace/coverage/default/0.spi_device_tpm_all.3323044732 |
|
|
Mar 21 02:22:57 PM PDT 24 |
Mar 21 02:23:20 PM PDT 24 |
19018968442 ps |
| T820 |
/workspace/coverage/default/13.spi_device_cfg_cmd.370411984 |
|
|
Mar 21 02:24:30 PM PDT 24 |
Mar 21 02:24:35 PM PDT 24 |
429654933 ps |
| T821 |
/workspace/coverage/default/7.spi_device_tpm_read_hw_reg.2111361263 |
|
|
Mar 21 02:23:51 PM PDT 24 |
Mar 21 02:23:56 PM PDT 24 |
1833498593 ps |
| T822 |
/workspace/coverage/default/6.spi_device_alert_test.2349245389 |
|
|
Mar 21 02:23:50 PM PDT 24 |
Mar 21 02:23:51 PM PDT 24 |
20350006 ps |
| T823 |
/workspace/coverage/default/41.spi_device_tpm_sts_read.3754955419 |
|
|
Mar 21 02:26:49 PM PDT 24 |
Mar 21 02:26:50 PM PDT 24 |
23910817 ps |
| T824 |
/workspace/coverage/default/18.spi_device_alert_test.1181100234 |
|
|
Mar 21 02:24:55 PM PDT 24 |
Mar 21 02:24:57 PM PDT 24 |
14984545 ps |
| T825 |
/workspace/coverage/default/0.spi_device_tpm_rw.246037333 |
|
|
Mar 21 02:23:00 PM PDT 24 |
Mar 21 02:23:03 PM PDT 24 |
85509981 ps |
| T826 |
/workspace/coverage/default/14.spi_device_stress_all.2850509191 |
|
|
Mar 21 02:24:30 PM PDT 24 |
Mar 21 02:27:02 PM PDT 24 |
90363709598 ps |
| T827 |
/workspace/coverage/default/47.spi_device_tpm_all.3112234383 |
|
|
Mar 21 02:27:22 PM PDT 24 |
Mar 21 02:27:54 PM PDT 24 |
3259118309 ps |
| T828 |
/workspace/coverage/default/2.spi_device_stress_all.1457129682 |
|
|
Mar 21 02:23:17 PM PDT 24 |
Mar 21 02:26:25 PM PDT 24 |
26714462798 ps |
| T829 |
/workspace/coverage/default/46.spi_device_csb_read.4107795131 |
|
|
Mar 21 02:27:21 PM PDT 24 |
Mar 21 02:27:22 PM PDT 24 |
43722393 ps |
| T830 |
/workspace/coverage/default/22.spi_device_read_buffer_direct.2571184621 |
|
|
Mar 21 02:25:20 PM PDT 24 |
Mar 21 02:25:26 PM PDT 24 |
584985913 ps |
| T831 |
/workspace/coverage/default/23.spi_device_tpm_rw.1746813880 |
|
|
Mar 21 02:25:20 PM PDT 24 |
Mar 21 02:25:22 PM PDT 24 |
18179418 ps |
| T832 |
/workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.2183952969 |
|
|
Mar 21 02:24:05 PM PDT 24 |
Mar 21 02:25:00 PM PDT 24 |
8474426264 ps |
| T833 |
/workspace/coverage/default/21.spi_device_tpm_rw.4005184998 |
|
|
Mar 21 02:25:07 PM PDT 24 |
Mar 21 02:25:08 PM PDT 24 |
62893774 ps |
| T834 |
/workspace/coverage/default/2.spi_device_mailbox.1369542608 |
|
|
Mar 21 02:23:17 PM PDT 24 |
Mar 21 02:23:20 PM PDT 24 |
174939605 ps |
| T835 |
/workspace/coverage/default/5.spi_device_tpm_all.1500023042 |
|
|
Mar 21 02:23:36 PM PDT 24 |
Mar 21 02:23:38 PM PDT 24 |
229016089 ps |
| T836 |
/workspace/coverage/default/26.spi_device_tpm_sts_read.1655248212 |
|
|
Mar 21 02:25:38 PM PDT 24 |
Mar 21 02:25:39 PM PDT 24 |
75328133 ps |
| T837 |
/workspace/coverage/default/0.spi_device_ram_cfg.326160411 |
|
|
Mar 21 02:22:57 PM PDT 24 |
Mar 21 02:22:58 PM PDT 24 |
16605263 ps |
| T838 |
/workspace/coverage/default/48.spi_device_tpm_rw.2654862094 |
|
|
Mar 21 02:27:29 PM PDT 24 |
Mar 21 02:27:33 PM PDT 24 |
78613894 ps |
| T839 |
/workspace/coverage/default/37.spi_device_read_buffer_direct.2948436070 |
|
|
Mar 21 02:26:28 PM PDT 24 |
Mar 21 02:26:35 PM PDT 24 |
1650954345 ps |
| T840 |
/workspace/coverage/default/6.spi_device_tpm_all.425225781 |
|
|
Mar 21 02:23:38 PM PDT 24 |
Mar 21 02:24:04 PM PDT 24 |
4356550048 ps |
| T841 |
/workspace/coverage/default/21.spi_device_read_buffer_direct.3486437274 |
|
|
Mar 21 02:25:09 PM PDT 24 |
Mar 21 02:25:13 PM PDT 24 |
120030914 ps |
| T842 |
/workspace/coverage/default/28.spi_device_flash_mode.2237825109 |
|
|
Mar 21 02:25:42 PM PDT 24 |
Mar 21 02:25:56 PM PDT 24 |
495647477 ps |
| T843 |
/workspace/coverage/default/49.spi_device_tpm_all.3388991531 |
|
|
Mar 21 02:27:28 PM PDT 24 |
Mar 21 02:28:36 PM PDT 24 |
14072238863 ps |
| T844 |
/workspace/coverage/default/28.spi_device_cfg_cmd.479467641 |
|
|
Mar 21 02:25:42 PM PDT 24 |
Mar 21 02:25:45 PM PDT 24 |
585649916 ps |
| T845 |
/workspace/coverage/default/24.spi_device_tpm_read_hw_reg.2812645059 |
|
|
Mar 21 02:25:22 PM PDT 24 |
Mar 21 02:25:38 PM PDT 24 |
3428951686 ps |
| T846 |
/workspace/coverage/default/39.spi_device_pass_addr_payload_swap.1895084449 |
|
|
Mar 21 02:26:45 PM PDT 24 |
Mar 21 02:26:50 PM PDT 24 |
14373378258 ps |
| T847 |
/workspace/coverage/default/6.spi_device_pass_cmd_filtering.1050277705 |
|
|
Mar 21 02:23:38 PM PDT 24 |
Mar 21 02:23:41 PM PDT 24 |
50126207 ps |
| T848 |
/workspace/coverage/default/12.spi_device_tpm_read_hw_reg.3324019568 |
|
|
Mar 21 02:24:18 PM PDT 24 |
Mar 21 02:24:31 PM PDT 24 |
17388824945 ps |
| T301 |
/workspace/coverage/default/27.spi_device_flash_and_tpm.1886969194 |
|
|
Mar 21 02:25:42 PM PDT 24 |
Mar 21 02:26:52 PM PDT 24 |
6623711878 ps |
| T849 |
/workspace/coverage/default/6.spi_device_stress_all.854030891 |
|
|
Mar 21 02:23:50 PM PDT 24 |
Mar 21 02:24:51 PM PDT 24 |
4403437233 ps |
| T850 |
/workspace/coverage/default/8.spi_device_cfg_cmd.883420604 |
|
|
Mar 21 02:24:01 PM PDT 24 |
Mar 21 02:24:07 PM PDT 24 |
6837439459 ps |
| T851 |
/workspace/coverage/default/24.spi_device_flash_and_tpm.586128325 |
|
|
Mar 21 02:25:22 PM PDT 24 |
Mar 21 02:27:45 PM PDT 24 |
94198729960 ps |
| T852 |
/workspace/coverage/default/5.spi_device_alert_test.1154910078 |
|
|
Mar 21 02:23:35 PM PDT 24 |
Mar 21 02:23:36 PM PDT 24 |
20587041 ps |
| T853 |
/workspace/coverage/default/47.spi_device_pass_addr_payload_swap.3843171756 |
|
|
Mar 21 02:27:23 PM PDT 24 |
Mar 21 02:28:12 PM PDT 24 |
81594913580 ps |
| T854 |
/workspace/coverage/default/8.spi_device_csb_read.2694244999 |
|
|
Mar 21 02:23:51 PM PDT 24 |
Mar 21 02:23:52 PM PDT 24 |
23219405 ps |
| T855 |
/workspace/coverage/default/4.spi_device_pass_addr_payload_swap.3687870844 |
|
|
Mar 21 02:23:29 PM PDT 24 |
Mar 21 02:23:50 PM PDT 24 |
5067522915 ps |
| T856 |
/workspace/coverage/default/18.spi_device_tpm_all.2299372333 |
|
|
Mar 21 02:24:48 PM PDT 24 |
Mar 21 02:25:07 PM PDT 24 |
2390482017 ps |
| T857 |
/workspace/coverage/default/32.spi_device_read_buffer_direct.3587856194 |
|
|
Mar 21 02:26:11 PM PDT 24 |
Mar 21 02:26:18 PM PDT 24 |
4814457720 ps |
| T858 |
/workspace/coverage/default/8.spi_device_pass_addr_payload_swap.2300862994 |
|
|
Mar 21 02:24:04 PM PDT 24 |
Mar 21 02:24:10 PM PDT 24 |
3263679245 ps |
| T859 |
/workspace/coverage/default/1.spi_device_pass_addr_payload_swap.2323611303 |
|
|
Mar 21 02:23:07 PM PDT 24 |
Mar 21 02:23:16 PM PDT 24 |
2170784109 ps |
| T860 |
/workspace/coverage/default/15.spi_device_tpm_all.973167882 |
|
|
Mar 21 02:24:38 PM PDT 24 |
Mar 21 02:25:32 PM PDT 24 |
10513220187 ps |
| T861 |
/workspace/coverage/default/24.spi_device_tpm_all.1299920116 |
|
|
Mar 21 02:25:22 PM PDT 24 |
Mar 21 02:26:06 PM PDT 24 |
22842653251 ps |
| T862 |
/workspace/coverage/default/43.spi_device_upload.2781315043 |
|
|
Mar 21 02:27:01 PM PDT 24 |
Mar 21 02:27:04 PM PDT 24 |
2197338240 ps |
| T863 |
/workspace/coverage/default/17.spi_device_csb_read.983568705 |
|
|
Mar 21 02:24:48 PM PDT 24 |
Mar 21 02:24:49 PM PDT 24 |
18265789 ps |
| T864 |
/workspace/coverage/default/8.spi_device_ram_cfg.3855700177 |
|
|
Mar 21 02:23:50 PM PDT 24 |
Mar 21 02:23:51 PM PDT 24 |
17819942 ps |
| T865 |
/workspace/coverage/default/36.spi_device_read_buffer_direct.3947848211 |
|
|
Mar 21 02:26:30 PM PDT 24 |
Mar 21 02:26:36 PM PDT 24 |
1361509070 ps |
| T866 |
/workspace/coverage/default/29.spi_device_tpm_rw.170379409 |
|
|
Mar 21 02:25:45 PM PDT 24 |
Mar 21 02:25:47 PM PDT 24 |
266343331 ps |
| T867 |
/workspace/coverage/default/18.spi_device_stress_all.584334187 |
|
|
Mar 21 02:24:59 PM PDT 24 |
Mar 21 02:30:09 PM PDT 24 |
42754865898 ps |
| T868 |
/workspace/coverage/default/27.spi_device_alert_test.576063923 |
|
|
Mar 21 02:25:33 PM PDT 24 |
Mar 21 02:25:34 PM PDT 24 |
55042108 ps |
| T869 |
/workspace/coverage/default/15.spi_device_pass_cmd_filtering.1116610032 |
|
|
Mar 21 02:24:38 PM PDT 24 |
Mar 21 02:25:05 PM PDT 24 |
11571014097 ps |
| T870 |
/workspace/coverage/default/47.spi_device_csb_read.2405723990 |
|
|
Mar 21 02:27:21 PM PDT 24 |
Mar 21 02:27:22 PM PDT 24 |
24806403 ps |
| T871 |
/workspace/coverage/default/35.spi_device_tpm_sts_read.623412415 |
|
|
Mar 21 02:26:17 PM PDT 24 |
Mar 21 02:26:17 PM PDT 24 |
55324034 ps |
| T872 |
/workspace/coverage/default/0.spi_device_flash_all.3216638345 |
|
|
Mar 21 02:23:06 PM PDT 24 |
Mar 21 02:23:34 PM PDT 24 |
3845948962 ps |
| T873 |
/workspace/coverage/default/12.spi_device_intercept.1178328663 |
|
|
Mar 21 02:24:16 PM PDT 24 |
Mar 21 02:24:22 PM PDT 24 |
1276456449 ps |
| T874 |
/workspace/coverage/default/45.spi_device_tpm_read_hw_reg.650580123 |
|
|
Mar 21 02:27:08 PM PDT 24 |
Mar 21 02:27:22 PM PDT 24 |
2474399932 ps |
| T875 |
/workspace/coverage/default/13.spi_device_alert_test.295865166 |
|
|
Mar 21 02:24:51 PM PDT 24 |
Mar 21 02:24:53 PM PDT 24 |
22580906 ps |
| T876 |
/workspace/coverage/default/10.spi_device_pass_cmd_filtering.3531703376 |
|
|
Mar 21 02:24:04 PM PDT 24 |
Mar 21 02:24:20 PM PDT 24 |
9800642727 ps |
| T877 |
/workspace/coverage/default/10.spi_device_tpm_rw.326540507 |
|
|
Mar 21 02:24:05 PM PDT 24 |
Mar 21 02:24:06 PM PDT 24 |
500715976 ps |
| T878 |
/workspace/coverage/default/42.spi_device_read_buffer_direct.920147935 |
|
|
Mar 21 02:27:03 PM PDT 24 |
Mar 21 02:27:07 PM PDT 24 |
1588948667 ps |
| T879 |
/workspace/coverage/default/48.spi_device_pass_cmd_filtering.2419604303 |
|
|
Mar 21 02:27:34 PM PDT 24 |
Mar 21 02:27:37 PM PDT 24 |
609229425 ps |
| T880 |
/workspace/coverage/default/23.spi_device_tpm_all.1817277087 |
|
|
Mar 21 02:25:23 PM PDT 24 |
Mar 21 02:25:45 PM PDT 24 |
9618282769 ps |
| T881 |
/workspace/coverage/default/47.spi_device_tpm_sts_read.491806772 |
|
|
Mar 21 02:27:23 PM PDT 24 |
Mar 21 02:27:24 PM PDT 24 |
251920416 ps |
| T882 |
/workspace/coverage/default/38.spi_device_tpm_sts_read.3294412379 |
|
|
Mar 21 02:26:39 PM PDT 24 |
Mar 21 02:26:40 PM PDT 24 |
431160623 ps |
| T883 |
/workspace/coverage/default/26.spi_device_tpm_rw.3042052746 |
|
|
Mar 21 02:25:33 PM PDT 24 |
Mar 21 02:25:36 PM PDT 24 |
102499821 ps |
| T884 |
/workspace/coverage/default/1.spi_device_csb_read.702005897 |
|
|
Mar 21 02:23:07 PM PDT 24 |
Mar 21 02:23:08 PM PDT 24 |
51274975 ps |
| T885 |
/workspace/coverage/default/10.spi_device_tpm_read_hw_reg.3539818058 |
|
|
Mar 21 02:24:03 PM PDT 24 |
Mar 21 02:24:18 PM PDT 24 |
5243918148 ps |
| T886 |
/workspace/coverage/default/16.spi_device_ram_cfg.4006604593 |
|
|
Mar 21 02:24:39 PM PDT 24 |
Mar 21 02:24:40 PM PDT 24 |
23459169 ps |
| T887 |
/workspace/coverage/default/6.spi_device_flash_mode.2601616877 |
|
|
Mar 21 02:23:37 PM PDT 24 |
Mar 21 02:24:08 PM PDT 24 |
4490269224 ps |
| T888 |
/workspace/coverage/default/0.spi_device_mem_parity.2773993667 |
|
|
Mar 21 02:22:59 PM PDT 24 |
Mar 21 02:23:00 PM PDT 24 |
125262174 ps |
| T889 |
/workspace/coverage/default/31.spi_device_upload.1134892162 |
|
|
Mar 21 02:25:57 PM PDT 24 |
Mar 21 02:25:59 PM PDT 24 |
72509337 ps |
| T890 |
/workspace/coverage/default/33.spi_device_alert_test.2248354030 |
|
|
Mar 21 02:26:14 PM PDT 24 |
Mar 21 02:26:15 PM PDT 24 |
15093407 ps |
| T891 |
/workspace/coverage/default/39.spi_device_tpm_sts_read.1056172128 |
|
|
Mar 21 02:26:37 PM PDT 24 |
Mar 21 02:26:38 PM PDT 24 |
84799746 ps |
| T892 |
/workspace/coverage/default/15.spi_device_read_buffer_direct.1105874304 |
|
|
Mar 21 02:24:36 PM PDT 24 |
Mar 21 02:24:41 PM PDT 24 |
1378789674 ps |
| T893 |
/workspace/coverage/default/6.spi_device_ram_cfg.4082575817 |
|
|
Mar 21 02:23:36 PM PDT 24 |
Mar 21 02:23:37 PM PDT 24 |
16159781 ps |
| T894 |
/workspace/coverage/default/37.spi_device_pass_cmd_filtering.3045641197 |
|
|
Mar 21 02:26:24 PM PDT 24 |
Mar 21 02:26:31 PM PDT 24 |
1143923543 ps |
| T895 |
/workspace/coverage/default/3.spi_device_mailbox.877274167 |
|
|
Mar 21 02:23:16 PM PDT 24 |
Mar 21 02:23:23 PM PDT 24 |
342746085 ps |
| T896 |
/workspace/coverage/default/6.spi_device_read_buffer_direct.2252264635 |
|
|
Mar 21 02:23:36 PM PDT 24 |
Mar 21 02:23:40 PM PDT 24 |
380603038 ps |
| T897 |
/workspace/coverage/default/0.spi_device_tpm_sts_read.4294934029 |
|
|
Mar 21 02:23:00 PM PDT 24 |
Mar 21 02:23:01 PM PDT 24 |
112677153 ps |
| T898 |
/workspace/coverage/default/29.spi_device_pass_cmd_filtering.2862217430 |
|
|
Mar 21 02:25:43 PM PDT 24 |
Mar 21 02:25:46 PM PDT 24 |
194808500 ps |
| T899 |
/workspace/coverage/default/3.spi_device_tpm_sts_read.77895918 |
|
|
Mar 21 02:23:17 PM PDT 24 |
Mar 21 02:23:18 PM PDT 24 |
102482674 ps |
| T900 |
/workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.347969431 |
|
|
Mar 21 02:26:15 PM PDT 24 |
Mar 21 02:27:31 PM PDT 24 |
11545795388 ps |
| T901 |
/workspace/coverage/default/18.spi_device_mailbox.2258636176 |
|
|
Mar 21 02:24:56 PM PDT 24 |
Mar 21 02:25:04 PM PDT 24 |
2223137470 ps |
| T902 |
/workspace/coverage/default/18.spi_device_pass_addr_payload_swap.2950677102 |
|
|
Mar 21 02:24:44 PM PDT 24 |
Mar 21 02:24:52 PM PDT 24 |
3940777861 ps |
| T903 |
/workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.2136352059 |
|
|
Mar 21 02:24:17 PM PDT 24 |
Mar 21 02:25:02 PM PDT 24 |
3092011796 ps |
| T904 |
/workspace/coverage/default/8.spi_device_tpm_read_hw_reg.2661135789 |
|
|
Mar 21 02:23:52 PM PDT 24 |
Mar 21 02:23:56 PM PDT 24 |
760141323 ps |
| T905 |
/workspace/coverage/default/6.spi_device_mem_parity.4176765226 |
|
|
Mar 21 02:23:38 PM PDT 24 |
Mar 21 02:23:40 PM PDT 24 |
31355766 ps |
| T906 |
/workspace/coverage/default/12.spi_device_pass_addr_payload_swap.2161181104 |
|
|
Mar 21 02:24:16 PM PDT 24 |
Mar 21 02:24:38 PM PDT 24 |
16448065489 ps |
| T907 |
/workspace/coverage/default/31.spi_device_cfg_cmd.3495530791 |
|
|
Mar 21 02:25:58 PM PDT 24 |
Mar 21 02:26:01 PM PDT 24 |
197182858 ps |
| T908 |
/workspace/coverage/default/22.spi_device_alert_test.1515832666 |
|
|
Mar 21 02:25:19 PM PDT 24 |
Mar 21 02:25:21 PM PDT 24 |
25047073 ps |
| T909 |
/workspace/coverage/default/21.spi_device_cfg_cmd.1259209718 |
|
|
Mar 21 02:25:09 PM PDT 24 |
Mar 21 02:25:13 PM PDT 24 |
2272693499 ps |
| T910 |
/workspace/coverage/default/37.spi_device_tpm_all.207067711 |
|
|
Mar 21 02:26:25 PM PDT 24 |
Mar 21 02:27:32 PM PDT 24 |
53687810457 ps |
| T911 |
/workspace/coverage/default/40.spi_device_pass_cmd_filtering.1672942827 |
|
|
Mar 21 02:26:39 PM PDT 24 |
Mar 21 02:26:44 PM PDT 24 |
5187287253 ps |
| T912 |
/workspace/coverage/default/5.spi_device_csb_read.3936860035 |
|
|
Mar 21 02:23:34 PM PDT 24 |
Mar 21 02:23:35 PM PDT 24 |
21482886 ps |
| T913 |
/workspace/coverage/default/34.spi_device_tpm_sts_read.238694630 |
|
|
Mar 21 02:26:16 PM PDT 24 |
Mar 21 02:26:17 PM PDT 24 |
60200927 ps |
| T914 |
/workspace/coverage/default/41.spi_device_pass_cmd_filtering.2722385918 |
|
|
Mar 21 02:26:52 PM PDT 24 |
Mar 21 02:26:57 PM PDT 24 |
843383635 ps |
| T915 |
/workspace/coverage/default/18.spi_device_csb_read.3749925846 |
|
|
Mar 21 02:24:48 PM PDT 24 |
Mar 21 02:24:49 PM PDT 24 |
72842601 ps |
| T916 |
/workspace/coverage/default/18.spi_device_mem_parity.1432110509 |
|
|
Mar 21 02:24:45 PM PDT 24 |
Mar 21 02:24:46 PM PDT 24 |
109344475 ps |
| T917 |
/workspace/coverage/default/48.spi_device_mailbox.2253949838 |
|
|
Mar 21 02:27:28 PM PDT 24 |
Mar 21 02:27:51 PM PDT 24 |
31257457928 ps |
| T918 |
/workspace/coverage/default/34.spi_device_tpm_all.3351377867 |
|
|
Mar 21 02:26:13 PM PDT 24 |
Mar 21 02:26:37 PM PDT 24 |
6433390280 ps |
| T919 |
/workspace/coverage/default/25.spi_device_alert_test.2166885631 |
|
|
Mar 21 02:25:33 PM PDT 24 |
Mar 21 02:25:34 PM PDT 24 |
15957910 ps |
| T920 |
/workspace/coverage/default/14.spi_device_tpm_sts_read.985127175 |
|
|
Mar 21 02:24:28 PM PDT 24 |
Mar 21 02:24:29 PM PDT 24 |
29937028 ps |
| T921 |
/workspace/coverage/default/23.spi_device_read_buffer_direct.155872467 |
|
|
Mar 21 02:25:22 PM PDT 24 |
Mar 21 02:25:30 PM PDT 24 |
3970904487 ps |
| T922 |
/workspace/coverage/default/15.spi_device_csb_read.250044273 |
|
|
Mar 21 02:24:27 PM PDT 24 |
Mar 21 02:24:27 PM PDT 24 |
66949878 ps |
| T923 |
/workspace/coverage/default/40.spi_device_tpm_all.1144810163 |
|
|
Mar 21 02:26:38 PM PDT 24 |
Mar 21 02:26:41 PM PDT 24 |
476083053 ps |
| T924 |
/workspace/coverage/default/1.spi_device_alert_test.3778914849 |
|
|
Mar 21 02:23:17 PM PDT 24 |
Mar 21 02:23:18 PM PDT 24 |
12304360 ps |
| T925 |
/workspace/coverage/default/49.spi_device_upload.3754848049 |
|
|
Mar 21 02:27:26 PM PDT 24 |
Mar 21 02:27:52 PM PDT 24 |
6638035233 ps |
| T926 |
/workspace/coverage/default/11.spi_device_alert_test.4043938760 |
|
|
Mar 21 02:24:18 PM PDT 24 |
Mar 21 02:24:19 PM PDT 24 |
40302880 ps |
| T927 |
/workspace/coverage/default/21.spi_device_intercept.3918870808 |
|
|
Mar 21 02:25:18 PM PDT 24 |
Mar 21 02:25:30 PM PDT 24 |
5617735147 ps |
| T307 |
/workspace/coverage/default/23.spi_device_stress_all.3889226532 |
|
|
Mar 21 02:25:21 PM PDT 24 |
Mar 21 02:28:06 PM PDT 24 |
26648796978 ps |
| T928 |
/workspace/coverage/default/8.spi_device_flash_and_tpm.1158146359 |
|
|
Mar 21 02:24:03 PM PDT 24 |
Mar 21 02:28:45 PM PDT 24 |
59457760961 ps |
| T929 |
/workspace/coverage/default/38.spi_device_intercept.137323151 |
|
|
Mar 21 02:26:41 PM PDT 24 |
Mar 21 02:26:45 PM PDT 24 |
199027573 ps |
| T930 |
/workspace/coverage/default/21.spi_device_pass_addr_payload_swap.3157670654 |
|
|
Mar 21 02:25:19 PM PDT 24 |
Mar 21 02:25:26 PM PDT 24 |
1760835026 ps |
| T931 |
/workspace/coverage/default/16.spi_device_csb_read.1147026391 |
|
|
Mar 21 02:24:34 PM PDT 24 |
Mar 21 02:24:35 PM PDT 24 |
20201241 ps |
| T932 |
/workspace/coverage/default/32.spi_device_pass_addr_payload_swap.2875308787 |
|
|
Mar 21 02:26:12 PM PDT 24 |
Mar 21 02:26:25 PM PDT 24 |
9320381150 ps |
| T933 |
/workspace/coverage/default/17.spi_device_flash_all.419944713 |
|
|
Mar 21 02:24:44 PM PDT 24 |
Mar 21 02:25:26 PM PDT 24 |
6701656647 ps |
| T293 |
/workspace/coverage/default/42.spi_device_flash_and_tpm.69500986 |
|
|
Mar 21 02:27:02 PM PDT 24 |
Mar 21 02:34:03 PM PDT 24 |
141087863880 ps |
| T934 |
/workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.1279952807 |
|
|
Mar 21 02:25:42 PM PDT 24 |
Mar 21 02:29:22 PM PDT 24 |
47192818663 ps |
| T935 |
/workspace/coverage/default/9.spi_device_tpm_all.4165802735 |
|
|
Mar 21 02:24:05 PM PDT 24 |
Mar 21 02:24:19 PM PDT 24 |
10400047672 ps |
| T936 |
/workspace/coverage/default/41.spi_device_stress_all.4115603431 |
|
|
Mar 21 02:26:52 PM PDT 24 |
Mar 21 02:27:15 PM PDT 24 |
1647408375 ps |
| T937 |
/workspace/coverage/default/45.spi_device_pass_cmd_filtering.2531463703 |
|
|
Mar 21 02:27:15 PM PDT 24 |
Mar 21 02:28:05 PM PDT 24 |
76873241653 ps |
| T938 |
/workspace/coverage/default/6.spi_device_flash_and_tpm.3498723387 |
|
|
Mar 21 02:23:48 PM PDT 24 |
Mar 21 02:28:45 PM PDT 24 |
33499693036 ps |
| T939 |
/workspace/coverage/default/19.spi_device_tpm_read_hw_reg.3850053382 |
|
|
Mar 21 02:24:55 PM PDT 24 |
Mar 21 02:25:15 PM PDT 24 |
4251396711 ps |
| T940 |
/workspace/coverage/default/29.spi_device_flash_all.3922371224 |
|
|
Mar 21 02:25:43 PM PDT 24 |
Mar 21 02:26:42 PM PDT 24 |
4205056935 ps |
| T941 |
/workspace/coverage/default/33.spi_device_flash_mode.1295650053 |
|
|
Mar 21 02:26:14 PM PDT 24 |
Mar 21 02:26:31 PM PDT 24 |
1436668811 ps |
| T942 |
/workspace/coverage/default/44.spi_device_tpm_all.3130080789 |
|
|
Mar 21 02:27:01 PM PDT 24 |
Mar 21 02:28:06 PM PDT 24 |
10866308906 ps |
| T943 |
/workspace/coverage/default/46.spi_device_tpm_all.439589833 |
|
|
Mar 21 02:27:19 PM PDT 24 |
Mar 21 02:28:00 PM PDT 24 |
9018694484 ps |
| T944 |
/workspace/coverage/default/45.spi_device_flash_mode.2083560233 |
|
|
Mar 21 02:27:21 PM PDT 24 |
Mar 21 02:28:11 PM PDT 24 |
18316864104 ps |
| T945 |
/workspace/coverage/default/17.spi_device_upload.1192676865 |
|
|
Mar 21 02:24:44 PM PDT 24 |
Mar 21 02:25:16 PM PDT 24 |
39502111494 ps |
| T946 |
/workspace/coverage/default/13.spi_device_tpm_sts_read.3816055200 |
|
|
Mar 21 02:24:26 PM PDT 24 |
Mar 21 02:24:27 PM PDT 24 |
222521695 ps |
| T291 |
/workspace/coverage/default/14.spi_device_flash_and_tpm.1166197884 |
|
|
Mar 21 02:24:25 PM PDT 24 |
Mar 21 02:25:39 PM PDT 24 |
7748601782 ps |
| T947 |
/workspace/coverage/default/39.spi_device_cfg_cmd.1176555668 |
|
|
Mar 21 02:26:39 PM PDT 24 |
Mar 21 02:26:45 PM PDT 24 |
2691249705 ps |
| T948 |
/workspace/coverage/default/3.spi_device_alert_test.723668064 |
|
|
Mar 21 02:23:29 PM PDT 24 |
Mar 21 02:23:31 PM PDT 24 |
32713373 ps |
| T949 |
/workspace/coverage/default/4.spi_device_ram_cfg.3150815965 |
|
|
Mar 21 02:23:28 PM PDT 24 |
Mar 21 02:23:30 PM PDT 24 |
18321051 ps |
| T950 |
/workspace/coverage/default/3.spi_device_mem_parity.2590365491 |
|
|
Mar 21 02:23:17 PM PDT 24 |
Mar 21 02:23:19 PM PDT 24 |
18036301 ps |
| T951 |
/workspace/coverage/default/35.spi_device_pass_cmd_filtering.42036770 |
|
|
Mar 21 02:26:16 PM PDT 24 |
Mar 21 02:26:31 PM PDT 24 |
45801424992 ps |
| T952 |
/workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.1464823380 |
|
|
Mar 21 02:24:19 PM PDT 24 |
Mar 21 02:30:22 PM PDT 24 |
130329461231 ps |
| T953 |
/workspace/coverage/default/4.spi_device_tpm_sts_read.1765655650 |
|
|
Mar 21 02:23:28 PM PDT 24 |
Mar 21 02:23:29 PM PDT 24 |
32762757 ps |
| T954 |
/workspace/coverage/default/40.spi_device_tpm_read_hw_reg.2356472271 |
|
|
Mar 21 02:26:38 PM PDT 24 |
Mar 21 02:26:56 PM PDT 24 |
80943567234 ps |
| T955 |
/workspace/coverage/default/14.spi_device_tpm_all.1114244583 |
|
|
Mar 21 02:24:32 PM PDT 24 |
Mar 21 02:25:06 PM PDT 24 |
4575106550 ps |
| T956 |
/workspace/coverage/default/14.spi_device_csb_read.2924429161 |
|
|
Mar 21 02:24:30 PM PDT 24 |
Mar 21 02:24:31 PM PDT 24 |
28561015 ps |
| T957 |
/workspace/coverage/default/18.spi_device_flash_mode.220148817 |
|
|
Mar 21 02:24:56 PM PDT 24 |
Mar 21 02:25:29 PM PDT 24 |
6355315386 ps |
| T958 |
/workspace/coverage/default/13.spi_device_ram_cfg.4242174706 |
|
|
Mar 21 02:24:19 PM PDT 24 |
Mar 21 02:24:19 PM PDT 24 |
20210445 ps |
| T959 |
/workspace/coverage/default/13.spi_device_tpm_rw.807944252 |
|
|
Mar 21 02:24:28 PM PDT 24 |
Mar 21 02:24:30 PM PDT 24 |
29892471 ps |
| T960 |
/workspace/coverage/default/30.spi_device_pass_cmd_filtering.854030158 |
|
|
Mar 21 02:26:03 PM PDT 24 |
Mar 21 02:26:09 PM PDT 24 |
302911612 ps |
| T961 |
/workspace/coverage/default/11.spi_device_csb_read.999064638 |
|
|
Mar 21 02:24:17 PM PDT 24 |
Mar 21 02:24:18 PM PDT 24 |
63329211 ps |
| T962 |
/workspace/coverage/default/42.spi_device_cfg_cmd.108978080 |
|
|
Mar 21 02:26:50 PM PDT 24 |
Mar 21 02:26:54 PM PDT 24 |
2758216057 ps |
| T963 |
/workspace/coverage/default/33.spi_device_intercept.3922545802 |
|
|
Mar 21 02:26:16 PM PDT 24 |
Mar 21 02:26:33 PM PDT 24 |
18071479641 ps |
| T964 |
/workspace/coverage/default/34.spi_device_tpm_rw.767412123 |
|
|
Mar 21 02:26:14 PM PDT 24 |
Mar 21 02:26:22 PM PDT 24 |
204553466 ps |
| T303 |
/workspace/coverage/default/42.spi_device_stress_all.3322761160 |
|
|
Mar 21 02:27:07 PM PDT 24 |
Mar 21 02:33:49 PM PDT 24 |
176714387758 ps |
| T965 |
/workspace/coverage/default/27.spi_device_tpm_rw.4134840349 |
|
|
Mar 21 02:25:32 PM PDT 24 |
Mar 21 02:25:36 PM PDT 24 |
266928405 ps |
| T966 |
/workspace/coverage/default/36.spi_device_alert_test.1420621942 |
|
|
Mar 21 02:26:26 PM PDT 24 |
Mar 21 02:26:27 PM PDT 24 |
47472696 ps |
| T967 |
/workspace/coverage/default/13.spi_device_stress_all.3051653322 |
|
|
Mar 21 02:24:25 PM PDT 24 |
Mar 21 02:25:08 PM PDT 24 |
3387048643 ps |
| T968 |
/workspace/coverage/default/8.spi_device_read_buffer_direct.3085914615 |
|
|
Mar 21 02:24:03 PM PDT 24 |
Mar 21 02:24:09 PM PDT 24 |
1382366895 ps |
| T969 |
/workspace/coverage/default/26.spi_device_tpm_all.1919134902 |
|
|
Mar 21 02:25:32 PM PDT 24 |
Mar 21 02:25:58 PM PDT 24 |
2801501949 ps |
| T970 |
/workspace/coverage/default/25.spi_device_csb_read.595961672 |
|
|
Mar 21 02:25:32 PM PDT 24 |
Mar 21 02:25:33 PM PDT 24 |
16012847 ps |
| T971 |
/workspace/coverage/default/15.spi_device_upload.1980351076 |
|
|
Mar 21 02:24:36 PM PDT 24 |
Mar 21 02:25:11 PM PDT 24 |
10442871639 ps |
| T972 |
/workspace/coverage/default/24.spi_device_stress_all.1636876123 |
|
|
Mar 21 02:25:23 PM PDT 24 |
Mar 21 02:38:13 PM PDT 24 |
112485806471 ps |
| T973 |
/workspace/coverage/default/10.spi_device_upload.1805621424 |
|
|
Mar 21 02:24:05 PM PDT 24 |
Mar 21 02:24:11 PM PDT 24 |
1208483514 ps |
| T974 |
/workspace/coverage/default/49.spi_device_flash_and_tpm.1895496083 |
|
|
Mar 21 02:27:28 PM PDT 24 |
Mar 21 02:28:54 PM PDT 24 |
10417918592 ps |
| T975 |
/workspace/coverage/default/29.spi_device_upload.2943390185 |
|
|
Mar 21 02:25:44 PM PDT 24 |
Mar 21 02:26:15 PM PDT 24 |
10045765816 ps |
| T976 |
/workspace/coverage/default/3.spi_device_flash_mode.109314835 |
|
|
Mar 21 02:23:17 PM PDT 24 |
Mar 21 02:23:49 PM PDT 24 |
62654192670 ps |
| T977 |
/workspace/coverage/default/23.spi_device_tpm_sts_read.1952122841 |
|
|
Mar 21 02:25:21 PM PDT 24 |
Mar 21 02:25:22 PM PDT 24 |
77885713 ps |
| T978 |
/workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.2172482054 |
|
|
Mar 21 02:26:27 PM PDT 24 |
Mar 21 02:27:20 PM PDT 24 |
16222601335 ps |
| T979 |
/workspace/coverage/default/25.spi_device_cfg_cmd.4246591202 |
|
|
Mar 21 02:25:35 PM PDT 24 |
Mar 21 02:25:39 PM PDT 24 |
107812472 ps |
| T980 |
/workspace/coverage/default/11.spi_device_pass_addr_payload_swap.4268898871 |
|
|
Mar 21 02:24:17 PM PDT 24 |
Mar 21 02:24:32 PM PDT 24 |
24438409147 ps |
| T981 |
/workspace/coverage/default/12.spi_device_tpm_all.1291218514 |
|
|
Mar 21 02:24:19 PM PDT 24 |
Mar 21 02:24:27 PM PDT 24 |
1484268269 ps |
| T982 |
/workspace/coverage/default/19.spi_device_tpm_all.3426906350 |
|
|
Mar 21 02:24:59 PM PDT 24 |
Mar 21 02:25:43 PM PDT 24 |
31877796741 ps |
| T983 |
/workspace/coverage/default/34.spi_device_intercept.2959432245 |
|
|
Mar 21 02:26:16 PM PDT 24 |
Mar 21 02:26:25 PM PDT 24 |
10215600985 ps |
| T304 |
/workspace/coverage/default/9.spi_device_flash_all.72973277 |
|
|
Mar 21 02:24:03 PM PDT 24 |
Mar 21 02:26:57 PM PDT 24 |
117238650474 ps |
| T984 |
/workspace/coverage/default/14.spi_device_ram_cfg.24326045 |
|
|
Mar 21 02:24:25 PM PDT 24 |
Mar 21 02:24:26 PM PDT 24 |
39592001 ps |
| T985 |
/workspace/coverage/default/27.spi_device_mailbox.3391546891 |
|
|
Mar 21 02:25:36 PM PDT 24 |
Mar 21 02:26:08 PM PDT 24 |
17155981895 ps |
| T986 |
/workspace/coverage/default/0.spi_device_csb_read.2862065600 |
|
|
Mar 21 02:22:59 PM PDT 24 |
Mar 21 02:23:00 PM PDT 24 |
245220634 ps |
| T987 |
/workspace/coverage/default/13.spi_device_pass_addr_payload_swap.277883522 |
|
|
Mar 21 02:24:27 PM PDT 24 |
Mar 21 02:24:45 PM PDT 24 |
7054571991 ps |
| T988 |
/workspace/coverage/default/35.spi_device_tpm_rw.1603837672 |
|
|
Mar 21 02:26:16 PM PDT 24 |
Mar 21 02:26:18 PM PDT 24 |
23501237 ps |
| T989 |
/workspace/coverage/default/11.spi_device_read_buffer_direct.2541984593 |
|
|
Mar 21 02:24:21 PM PDT 24 |
Mar 21 02:24:26 PM PDT 24 |
602000216 ps |
| T990 |
/workspace/coverage/default/8.spi_device_mem_parity.1065444925 |
|
|
Mar 21 02:23:50 PM PDT 24 |
Mar 21 02:23:51 PM PDT 24 |
18073125 ps |
| T991 |
/workspace/coverage/default/19.spi_device_stress_all.2945949512 |
|
|
Mar 21 02:25:08 PM PDT 24 |
Mar 21 02:25:09 PM PDT 24 |
49472263 ps |
| T992 |
/workspace/coverage/default/37.spi_device_flash_mode.1447419402 |
|
|
Mar 21 02:26:25 PM PDT 24 |
Mar 21 02:26:49 PM PDT 24 |
5864166479 ps |
| T993 |
/workspace/coverage/default/44.spi_device_read_buffer_direct.1143019557 |
|
|
Mar 21 02:27:08 PM PDT 24 |
Mar 21 02:27:11 PM PDT 24 |
106925508 ps |
| T994 |
/workspace/coverage/default/5.spi_device_flash_mode.2334112355 |
|
|
Mar 21 02:23:37 PM PDT 24 |
Mar 21 02:24:58 PM PDT 24 |
18731366623 ps |
| T995 |
/workspace/coverage/cover_reg_top/33.spi_device_intr_test.1771361476 |
|
|
Mar 21 02:02:51 PM PDT 24 |
Mar 21 02:02:52 PM PDT 24 |
16667677 ps |
| T996 |
/workspace/coverage/cover_reg_top/40.spi_device_intr_test.1797974049 |
|
|
Mar 21 02:02:55 PM PDT 24 |
Mar 21 02:02:56 PM PDT 24 |
13251311 ps |
| T154 |
/workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.3914950170 |
|
|
Mar 21 02:02:45 PM PDT 24 |
Mar 21 02:02:48 PM PDT 24 |
131054840 ps |
| T102 |
/workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.577768011 |
|
|
Mar 21 02:02:41 PM PDT 24 |
Mar 21 02:02:44 PM PDT 24 |
163557419 ps |
| T997 |
/workspace/coverage/cover_reg_top/3.spi_device_mem_walk.3137881372 |
|
|
Mar 21 02:02:43 PM PDT 24 |
Mar 21 02:02:44 PM PDT 24 |
17966538 ps |
| T103 |
/workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.2402299325 |
|
|
Mar 21 02:02:47 PM PDT 24 |
Mar 21 02:03:06 PM PDT 24 |
15722361183 ps |
| T998 |
/workspace/coverage/cover_reg_top/41.spi_device_intr_test.550784636 |
|
|
Mar 21 02:02:54 PM PDT 24 |
Mar 21 02:02:56 PM PDT 24 |
47427247 ps |
| T104 |
/workspace/coverage/cover_reg_top/14.spi_device_tl_errors.1495595172 |
|
|
Mar 21 02:02:49 PM PDT 24 |
Mar 21 02:02:53 PM PDT 24 |
714758498 ps |
| T105 |
/workspace/coverage/cover_reg_top/7.spi_device_tl_errors.2151378327 |
|
|
Mar 21 02:02:49 PM PDT 24 |
Mar 21 02:02:52 PM PDT 24 |
65109860 ps |
| T999 |
/workspace/coverage/cover_reg_top/26.spi_device_intr_test.2046616001 |
|
|
Mar 21 02:02:55 PM PDT 24 |
Mar 21 02:02:56 PM PDT 24 |
68744925 ps |
| T1000 |
/workspace/coverage/cover_reg_top/10.spi_device_intr_test.1528434142 |
|
|
Mar 21 02:02:46 PM PDT 24 |
Mar 21 02:02:47 PM PDT 24 |
43610767 ps |
| T123 |
/workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.3319065994 |
|
|
Mar 21 02:02:40 PM PDT 24 |
Mar 21 02:02:42 PM PDT 24 |
477253519 ps |
| T146 |
/workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.1622551961 |
|
|
Mar 21 02:02:50 PM PDT 24 |
Mar 21 02:02:53 PM PDT 24 |
317696570 ps |
| T1001 |
/workspace/coverage/cover_reg_top/4.spi_device_intr_test.4157986951 |
|
|
Mar 21 02:02:45 PM PDT 24 |
Mar 21 02:02:46 PM PDT 24 |
34120778 ps |
| T1002 |
/workspace/coverage/cover_reg_top/0.spi_device_mem_walk.2791546646 |
|
|
Mar 21 02:02:41 PM PDT 24 |
Mar 21 02:02:42 PM PDT 24 |
42009884 ps |
| T1003 |
/workspace/coverage/cover_reg_top/25.spi_device_intr_test.977700808 |
|
|
Mar 21 02:02:53 PM PDT 24 |
Mar 21 02:02:54 PM PDT 24 |
22842442 ps |
| T108 |
/workspace/coverage/cover_reg_top/15.spi_device_tl_errors.1268306139 |
|
|
Mar 21 02:02:50 PM PDT 24 |
Mar 21 02:02:54 PM PDT 24 |
383745941 ps |
| T1004 |
/workspace/coverage/cover_reg_top/20.spi_device_intr_test.133954029 |
|
|
Mar 21 02:02:50 PM PDT 24 |
Mar 21 02:02:51 PM PDT 24 |
178983621 ps |
| T1005 |
/workspace/coverage/cover_reg_top/2.spi_device_csr_rw.399502994 |
|
|
Mar 21 02:02:49 PM PDT 24 |
Mar 21 02:02:51 PM PDT 24 |
128002009 ps |
| T1006 |
/workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.786703576 |
|
|
Mar 21 02:02:50 PM PDT 24 |
Mar 21 02:02:54 PM PDT 24 |
104988596 ps |
| T114 |
/workspace/coverage/cover_reg_top/11.spi_device_tl_errors.1575065019 |
|
|
Mar 21 02:02:46 PM PDT 24 |
Mar 21 02:02:48 PM PDT 24 |
226919831 ps |
| T106 |
/workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.1049293 |
|
|
Mar 21 02:02:48 PM PDT 24 |
Mar 21 02:03:06 PM PDT 24 |
1197988222 ps |
| T111 |
/workspace/coverage/cover_reg_top/0.spi_device_tl_errors.3806923748 |
|
|
Mar 21 02:02:40 PM PDT 24 |
Mar 21 02:02:43 PM PDT 24 |
1129861321 ps |
| T1007 |
/workspace/coverage/cover_reg_top/9.spi_device_csr_rw.1230398349 |
|
|
Mar 21 02:02:43 PM PDT 24 |
Mar 21 02:02:45 PM PDT 24 |
25421792 ps |
| T1008 |
/workspace/coverage/cover_reg_top/18.spi_device_intr_test.1201425926 |
|
|
Mar 21 02:02:53 PM PDT 24 |
Mar 21 02:02:54 PM PDT 24 |
19585351 ps |
| T147 |
/workspace/coverage/cover_reg_top/13.spi_device_csr_rw.4198013312 |
|
|
Mar 21 02:02:46 PM PDT 24 |
Mar 21 02:02:49 PM PDT 24 |
166525425 ps |
| T1009 |
/workspace/coverage/cover_reg_top/23.spi_device_intr_test.609184856 |
|
|
Mar 21 02:02:50 PM PDT 24 |
Mar 21 02:02:51 PM PDT 24 |
54797308 ps |
| T124 |
/workspace/coverage/cover_reg_top/16.spi_device_csr_rw.2337631866 |
|
|
Mar 21 02:02:49 PM PDT 24 |
Mar 21 02:02:51 PM PDT 24 |
35934392 ps |
| T121 |
/workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.1141101875 |
|
|
Mar 21 02:02:47 PM PDT 24 |
Mar 21 02:02:51 PM PDT 24 |
129813309 ps |
| T116 |
/workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.3129468889 |
|
|
Mar 21 02:02:47 PM PDT 24 |
Mar 21 02:02:50 PM PDT 24 |
84197492 ps |
| T1010 |
/workspace/coverage/cover_reg_top/4.spi_device_mem_walk.1636732916 |
|
|
Mar 21 02:02:45 PM PDT 24 |
Mar 21 02:02:46 PM PDT 24 |
14196188 ps |
| T1011 |
/workspace/coverage/cover_reg_top/36.spi_device_intr_test.2073823057 |
|
|
Mar 21 02:02:48 PM PDT 24 |
Mar 21 02:02:49 PM PDT 24 |
37836469 ps |
| T155 |
/workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.2927092098 |
|
|
Mar 21 02:02:55 PM PDT 24 |
Mar 21 02:02:57 PM PDT 24 |
65396818 ps |
| T1012 |
/workspace/coverage/cover_reg_top/7.spi_device_intr_test.2537162760 |
|
|
Mar 21 02:02:45 PM PDT 24 |
Mar 21 02:02:47 PM PDT 24 |
14944979 ps |
| T1013 |
/workspace/coverage/cover_reg_top/0.spi_device_csr_rw.2190761305 |
|
|
Mar 21 02:02:41 PM PDT 24 |
Mar 21 02:02:42 PM PDT 24 |
143831470 ps |
| T122 |
/workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.4262903098 |
|
|
Mar 21 02:02:49 PM PDT 24 |
Mar 21 02:02:51 PM PDT 24 |
58218742 ps |
| T1014 |
/workspace/coverage/cover_reg_top/43.spi_device_intr_test.124221350 |
|
|
Mar 21 02:02:51 PM PDT 24 |
Mar 21 02:02:52 PM PDT 24 |
11593197 ps |
| T117 |
/workspace/coverage/cover_reg_top/16.spi_device_tl_errors.3355652091 |
|
|
Mar 21 02:02:41 PM PDT 24 |
Mar 21 02:02:43 PM PDT 24 |
119502086 ps |
| T1015 |
/workspace/coverage/cover_reg_top/1.spi_device_intr_test.1377468292 |
|
|
Mar 21 02:02:42 PM PDT 24 |
Mar 21 02:02:43 PM PDT 24 |
27040113 ps |
| T125 |
/workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.2139254443 |
|
|
Mar 21 02:02:45 PM PDT 24 |
Mar 21 02:03:20 PM PDT 24 |
1064593802 ps |
| T1016 |
/workspace/coverage/cover_reg_top/27.spi_device_intr_test.3625196919 |
|
|
Mar 21 02:02:49 PM PDT 24 |
Mar 21 02:02:50 PM PDT 24 |
17154064 ps |
| T112 |
/workspace/coverage/cover_reg_top/17.spi_device_tl_errors.316872029 |
|
|
Mar 21 02:02:51 PM PDT 24 |
Mar 21 02:02:54 PM PDT 24 |
146023981 ps |
| T1017 |
/workspace/coverage/cover_reg_top/15.spi_device_intr_test.136282394 |
|
|
Mar 21 02:02:42 PM PDT 24 |
Mar 21 02:02:43 PM PDT 24 |
12623004 ps |
| T96 |
/workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.227131141 |
|
|
Mar 21 02:02:43 PM PDT 24 |
Mar 21 02:02:45 PM PDT 24 |
38826921 ps |
| T107 |
/workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.1874447176 |
|
|
Mar 21 02:02:50 PM PDT 24 |
Mar 21 02:03:08 PM PDT 24 |
316453175 ps |
| T1018 |
/workspace/coverage/cover_reg_top/48.spi_device_intr_test.3812117893 |
|
|
Mar 21 02:02:49 PM PDT 24 |
Mar 21 02:02:51 PM PDT 24 |
46204621 ps |
| T1019 |
/workspace/coverage/cover_reg_top/9.spi_device_intr_test.2602919002 |
|
|
Mar 21 02:02:44 PM PDT 24 |
Mar 21 02:02:45 PM PDT 24 |
69724679 ps |
| T148 |
/workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.1626000170 |
|
|
Mar 21 02:02:48 PM PDT 24 |
Mar 21 02:02:52 PM PDT 24 |
547818100 ps |
| T1020 |
/workspace/coverage/cover_reg_top/31.spi_device_intr_test.1729117451 |
|
|
Mar 21 02:02:52 PM PDT 24 |
Mar 21 02:02:53 PM PDT 24 |
38999414 ps |
| T1021 |
/workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.1869689881 |
|
|
Mar 21 02:02:49 PM PDT 24 |
Mar 21 02:02:52 PM PDT 24 |
309840952 ps |
| T126 |
/workspace/coverage/cover_reg_top/5.spi_device_csr_rw.2554240784 |
|
|
Mar 21 02:02:50 PM PDT 24 |
Mar 21 02:02:54 PM PDT 24 |
328188007 ps |
| T1022 |
/workspace/coverage/cover_reg_top/47.spi_device_intr_test.3014889834 |
|
|
Mar 21 02:02:52 PM PDT 24 |
Mar 21 02:02:53 PM PDT 24 |
70110237 ps |
| T1023 |
/workspace/coverage/cover_reg_top/42.spi_device_intr_test.3158503744 |
|
|
Mar 21 02:02:50 PM PDT 24 |
Mar 21 02:02:51 PM PDT 24 |
34779731 ps |
| T97 |
/workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.221904264 |
|
|
Mar 21 02:02:42 PM PDT 24 |
Mar 21 02:02:43 PM PDT 24 |
177399571 ps |
| T113 |
/workspace/coverage/cover_reg_top/12.spi_device_tl_errors.3121772377 |
|
|
Mar 21 02:02:47 PM PDT 24 |
Mar 21 02:02:52 PM PDT 24 |
133393079 ps |
| T1024 |
/workspace/coverage/cover_reg_top/17.spi_device_intr_test.1524533791 |
|
|
Mar 21 02:02:54 PM PDT 24 |
Mar 21 02:02:56 PM PDT 24 |
38569847 ps |
| T1025 |
/workspace/coverage/cover_reg_top/30.spi_device_intr_test.2402180752 |
|
|
Mar 21 02:02:51 PM PDT 24 |
Mar 21 02:02:52 PM PDT 24 |
31315263 ps |
| T149 |
/workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.560119793 |
|
|
Mar 21 02:02:51 PM PDT 24 |
Mar 21 02:02:54 PM PDT 24 |
116616783 ps |
| T1026 |
/workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.3907937407 |
|
|
Mar 21 02:02:48 PM PDT 24 |
Mar 21 02:03:00 PM PDT 24 |
187224154 ps |
| T1027 |
/workspace/coverage/cover_reg_top/49.spi_device_intr_test.575582898 |
|
|
Mar 21 02:02:52 PM PDT 24 |
Mar 21 02:02:53 PM PDT 24 |
53142827 ps |
| T187 |
/workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.249479480 |
|
|
Mar 21 02:02:50 PM PDT 24 |
Mar 21 02:03:09 PM PDT 24 |
299318660 ps |
| T1028 |
/workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.798016442 |
|
|
Mar 21 02:02:42 PM PDT 24 |
Mar 21 02:02:45 PM PDT 24 |
1474454468 ps |