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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.99 98.36 94.45 98.61 89.36 97.09 95.82 98.22


Total test records in report: 1113
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T118 /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.2078651135 Mar 21 02:02:45 PM PDT 24 Mar 21 02:02:49 PM PDT 24 116707913 ps
T1029 /workspace/coverage/cover_reg_top/6.spi_device_intr_test.3396490726 Mar 21 02:02:50 PM PDT 24 Mar 21 02:02:51 PM PDT 24 166409397 ps
T1030 /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.1601639735 Mar 21 02:02:55 PM PDT 24 Mar 21 02:02:58 PM PDT 24 46446007 ps
T1031 /workspace/coverage/cover_reg_top/3.spi_device_intr_test.1323988820 Mar 21 02:02:43 PM PDT 24 Mar 21 02:02:45 PM PDT 24 44004563 ps
T156 /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.4154178528 Mar 21 02:02:42 PM PDT 24 Mar 21 02:02:45 PM PDT 24 386902943 ps
T120 /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.778052110 Mar 21 02:02:46 PM PDT 24 Mar 21 02:02:50 PM PDT 24 106407496 ps
T127 /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.2805578413 Mar 21 02:02:40 PM PDT 24 Mar 21 02:02:42 PM PDT 24 126965903 ps
T1032 /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.2075679141 Mar 21 02:02:47 PM PDT 24 Mar 21 02:02:50 PM PDT 24 133433312 ps
T1033 /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.1669845221 Mar 21 02:02:50 PM PDT 24 Mar 21 02:02:52 PM PDT 24 41740462 ps
T1034 /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.4001903813 Mar 21 02:02:51 PM PDT 24 Mar 21 02:02:53 PM PDT 24 64549020 ps
T1035 /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.2988885211 Mar 21 02:02:45 PM PDT 24 Mar 21 02:02:51 PM PDT 24 909719227 ps
T1036 /workspace/coverage/cover_reg_top/45.spi_device_intr_test.4060233081 Mar 21 02:02:48 PM PDT 24 Mar 21 02:02:49 PM PDT 24 13597918 ps
T150 /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.4111531058 Mar 21 02:02:44 PM PDT 24 Mar 21 02:02:46 PM PDT 24 81851149 ps
T1037 /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.3861577100 Mar 21 02:02:41 PM PDT 24 Mar 21 02:02:43 PM PDT 24 61264779 ps
T1038 /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.3065338546 Mar 21 02:02:41 PM PDT 24 Mar 21 02:02:44 PM PDT 24 171598451 ps
T1039 /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.1640198487 Mar 21 02:02:47 PM PDT 24 Mar 21 02:02:50 PM PDT 24 74241616 ps
T188 /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.746085563 Mar 21 02:02:40 PM PDT 24 Mar 21 02:02:58 PM PDT 24 1142434311 ps
T1040 /workspace/coverage/cover_reg_top/16.spi_device_intr_test.1000575287 Mar 21 02:02:49 PM PDT 24 Mar 21 02:02:50 PM PDT 24 59783119 ps
T173 /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.1334102943 Mar 21 02:02:45 PM PDT 24 Mar 21 02:02:47 PM PDT 24 65680534 ps
T151 /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.2912836014 Mar 21 02:02:45 PM PDT 24 Mar 21 02:03:08 PM PDT 24 2095105593 ps
T1041 /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.3332229587 Mar 21 02:02:47 PM PDT 24 Mar 21 02:03:03 PM PDT 24 855315919 ps
T1042 /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.3953144809 Mar 21 02:02:50 PM PDT 24 Mar 21 02:02:53 PM PDT 24 141825422 ps
T128 /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.3718122984 Mar 21 02:02:46 PM PDT 24 Mar 21 02:02:50 PM PDT 24 387400367 ps
T152 /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.3178641751 Mar 21 02:02:53 PM PDT 24 Mar 21 02:03:00 PM PDT 24 2403409421 ps
T1043 /workspace/coverage/cover_reg_top/39.spi_device_intr_test.2709264163 Mar 21 02:02:52 PM PDT 24 Mar 21 02:02:53 PM PDT 24 25773583 ps
T1044 /workspace/coverage/cover_reg_top/35.spi_device_intr_test.1267976253 Mar 21 02:02:50 PM PDT 24 Mar 21 02:02:52 PM PDT 24 14545858 ps
T1045 /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.2698179059 Mar 21 02:02:44 PM PDT 24 Mar 21 02:03:03 PM PDT 24 383990300 ps
T1046 /workspace/coverage/cover_reg_top/37.spi_device_intr_test.3161223532 Mar 21 02:02:49 PM PDT 24 Mar 21 02:02:50 PM PDT 24 13499819 ps
T1047 /workspace/coverage/cover_reg_top/24.spi_device_intr_test.378621524 Mar 21 02:02:53 PM PDT 24 Mar 21 02:02:54 PM PDT 24 37010145 ps
T1048 /workspace/coverage/cover_reg_top/32.spi_device_intr_test.2146456998 Mar 21 02:02:48 PM PDT 24 Mar 21 02:02:49 PM PDT 24 14405323 ps
T1049 /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.1316510328 Mar 21 02:02:47 PM PDT 24 Mar 21 02:02:52 PM PDT 24 138140284 ps
T153 /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.1838474684 Mar 21 02:02:45 PM PDT 24 Mar 21 02:02:49 PM PDT 24 142750553 ps
T1050 /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.3246766657 Mar 21 02:02:50 PM PDT 24 Mar 21 02:02:54 PM PDT 24 46699555 ps
T129 /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.3302438562 Mar 21 02:02:45 PM PDT 24 Mar 21 02:02:47 PM PDT 24 478554207 ps
T1051 /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.3205398600 Mar 21 02:02:40 PM PDT 24 Mar 21 02:02:45 PM PDT 24 63271020 ps
T1052 /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.2068472650 Mar 21 02:02:49 PM PDT 24 Mar 21 02:02:54 PM PDT 24 917004144 ps
T1053 /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.3972507328 Mar 21 02:02:54 PM PDT 24 Mar 21 02:02:55 PM PDT 24 71757279 ps
T1054 /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.1085251142 Mar 21 02:02:44 PM PDT 24 Mar 21 02:02:48 PM PDT 24 59139147 ps
T189 /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.3906809763 Mar 21 02:02:41 PM PDT 24 Mar 21 02:02:55 PM PDT 24 820581998 ps
T98 /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.54660441 Mar 21 02:02:43 PM PDT 24 Mar 21 02:02:44 PM PDT 24 184137722 ps
T1055 /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.3609972032 Mar 21 02:02:45 PM PDT 24 Mar 21 02:02:48 PM PDT 24 66932233 ps
T1056 /workspace/coverage/cover_reg_top/38.spi_device_intr_test.1818680907 Mar 21 02:02:50 PM PDT 24 Mar 21 02:02:51 PM PDT 24 43455742 ps
T1057 /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.3228795683 Mar 21 02:02:43 PM PDT 24 Mar 21 02:02:49 PM PDT 24 71194562 ps
T130 /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.563660738 Mar 21 02:02:40 PM PDT 24 Mar 21 02:02:43 PM PDT 24 59593779 ps
T1058 /workspace/coverage/cover_reg_top/2.spi_device_intr_test.4104622660 Mar 21 02:02:42 PM PDT 24 Mar 21 02:02:44 PM PDT 24 29606342 ps
T131 /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.3664639812 Mar 21 02:02:44 PM PDT 24 Mar 21 02:02:48 PM PDT 24 34927985 ps
T1059 /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.2519870622 Mar 21 02:02:55 PM PDT 24 Mar 21 02:02:59 PM PDT 24 63746656 ps
T99 /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.761267186 Mar 21 02:02:40 PM PDT 24 Mar 21 02:02:42 PM PDT 24 78629531 ps
T1060 /workspace/coverage/cover_reg_top/5.spi_device_intr_test.4034883567 Mar 21 02:02:48 PM PDT 24 Mar 21 02:02:49 PM PDT 24 53150024 ps
T1061 /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.2013550056 Mar 21 02:02:50 PM PDT 24 Mar 21 02:02:52 PM PDT 24 120828561 ps
T132 /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.1057562518 Mar 21 02:02:49 PM PDT 24 Mar 21 02:02:51 PM PDT 24 96394456 ps
T1062 /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.1889194412 Mar 21 02:03:11 PM PDT 24 Mar 21 02:03:25 PM PDT 24 792383743 ps
T1063 /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.2172867545 Mar 21 02:02:45 PM PDT 24 Mar 21 02:02:48 PM PDT 24 133784223 ps
T100 /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.1775193457 Mar 21 02:02:37 PM PDT 24 Mar 21 02:02:38 PM PDT 24 178048500 ps
T1064 /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.4102896033 Mar 21 02:02:42 PM PDT 24 Mar 21 02:02:48 PM PDT 24 413400593 ps
T1065 /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.3759623321 Mar 21 02:02:51 PM PDT 24 Mar 21 02:02:54 PM PDT 24 275881063 ps
T1066 /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.2263345903 Mar 21 02:02:41 PM PDT 24 Mar 21 02:02:42 PM PDT 24 36591979 ps
T1067 /workspace/coverage/cover_reg_top/19.spi_device_intr_test.674750987 Mar 21 02:02:51 PM PDT 24 Mar 21 02:02:52 PM PDT 24 11150683 ps
T1068 /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.1851209458 Mar 21 02:02:48 PM PDT 24 Mar 21 02:02:51 PM PDT 24 358723571 ps
T192 /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.2754040992 Mar 21 02:02:41 PM PDT 24 Mar 21 02:02:59 PM PDT 24 1208563690 ps
T1069 /workspace/coverage/cover_reg_top/11.spi_device_intr_test.3278835276 Mar 21 02:02:47 PM PDT 24 Mar 21 02:02:48 PM PDT 24 38209247 ps
T191 /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.367192740 Mar 21 02:02:46 PM PDT 24 Mar 21 02:03:02 PM PDT 24 1158522144 ps
T1070 /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.2922198782 Mar 21 02:02:44 PM PDT 24 Mar 21 02:02:46 PM PDT 24 22618727 ps
T1071 /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.3302395792 Mar 21 02:02:44 PM PDT 24 Mar 21 02:02:51 PM PDT 24 222709559 ps
T184 /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.3054609246 Mar 21 02:02:43 PM PDT 24 Mar 21 02:02:48 PM PDT 24 249621288 ps
T1072 /workspace/coverage/cover_reg_top/8.spi_device_intr_test.578513392 Mar 21 02:02:42 PM PDT 24 Mar 21 02:02:44 PM PDT 24 15160635 ps
T1073 /workspace/coverage/cover_reg_top/44.spi_device_intr_test.601525465 Mar 21 02:02:51 PM PDT 24 Mar 21 02:02:52 PM PDT 24 11563595 ps
T133 /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.658461659 Mar 21 02:02:42 PM PDT 24 Mar 21 02:02:46 PM PDT 24 142577043 ps
T1074 /workspace/coverage/cover_reg_top/46.spi_device_intr_test.193129394 Mar 21 02:02:51 PM PDT 24 Mar 21 02:02:52 PM PDT 24 50067515 ps
T1075 /workspace/coverage/cover_reg_top/21.spi_device_intr_test.1801037097 Mar 21 02:02:49 PM PDT 24 Mar 21 02:02:50 PM PDT 24 42717174 ps
T115 /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.1645001809 Mar 21 02:02:45 PM PDT 24 Mar 21 02:02:55 PM PDT 24 367236071 ps
T1076 /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.4193063954 Mar 21 02:02:42 PM PDT 24 Mar 21 02:02:43 PM PDT 24 37422105 ps
T1077 /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.1118519586 Mar 21 02:02:47 PM PDT 24 Mar 21 02:02:48 PM PDT 24 64800959 ps
T1078 /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.3665501431 Mar 21 02:02:39 PM PDT 24 Mar 21 02:02:41 PM PDT 24 159478247 ps
T185 /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.2756920059 Mar 21 02:02:48 PM PDT 24 Mar 21 02:02:52 PM PDT 24 283787416 ps
T1079 /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.3883984654 Mar 21 02:02:43 PM PDT 24 Mar 21 02:03:18 PM PDT 24 5213495332 ps
T1080 /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.485727713 Mar 21 02:02:41 PM PDT 24 Mar 21 02:02:43 PM PDT 24 50712412 ps
T1081 /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.329036738 Mar 21 02:02:44 PM PDT 24 Mar 21 02:03:17 PM PDT 24 1680863371 ps
T1082 /workspace/coverage/cover_reg_top/29.spi_device_intr_test.3449380555 Mar 21 02:02:55 PM PDT 24 Mar 21 02:02:57 PM PDT 24 32623907 ps
T1083 /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.1882868583 Mar 21 02:02:47 PM PDT 24 Mar 21 02:02:49 PM PDT 24 38820222 ps
T1084 /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.4217090495 Mar 21 02:02:39 PM PDT 24 Mar 21 02:02:54 PM PDT 24 424095457 ps
T1085 /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.2175399284 Mar 21 02:02:46 PM PDT 24 Mar 21 02:02:50 PM PDT 24 148909013 ps
T190 /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.1419673999 Mar 21 02:02:50 PM PDT 24 Mar 21 02:03:06 PM PDT 24 7992859349 ps
T1086 /workspace/coverage/cover_reg_top/14.spi_device_intr_test.2198199307 Mar 21 02:02:50 PM PDT 24 Mar 21 02:02:51 PM PDT 24 43215917 ps
T119 /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.1692316392 Mar 21 02:02:50 PM PDT 24 Mar 21 02:03:08 PM PDT 24 623705622 ps
T1087 /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.273557056 Mar 21 02:02:41 PM PDT 24 Mar 21 02:02:44 PM PDT 24 452144600 ps
T1088 /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.131960788 Mar 21 02:02:40 PM PDT 24 Mar 21 02:02:41 PM PDT 24 41612287 ps
T1089 /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.45522749 Mar 21 02:02:47 PM PDT 24 Mar 21 02:03:08 PM PDT 24 2075814133 ps
T1090 /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.2962816087 Mar 21 02:02:50 PM PDT 24 Mar 21 02:02:54 PM PDT 24 80641248 ps
T1091 /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.146297816 Mar 21 02:02:47 PM PDT 24 Mar 21 02:03:02 PM PDT 24 525432934 ps
T1092 /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.2524910499 Mar 21 02:02:47 PM PDT 24 Mar 21 02:02:55 PM PDT 24 1485854818 ps
T1093 /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.3099521965 Mar 21 02:02:50 PM PDT 24 Mar 21 02:02:52 PM PDT 24 37884999 ps
T1094 /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.1454354734 Mar 21 02:02:47 PM PDT 24 Mar 21 02:02:49 PM PDT 24 82241537 ps
T1095 /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.2457169879 Mar 21 02:02:41 PM PDT 24 Mar 21 02:02:43 PM PDT 24 53785415 ps
T1096 /workspace/coverage/cover_reg_top/13.spi_device_intr_test.244840494 Mar 21 02:02:58 PM PDT 24 Mar 21 02:03:01 PM PDT 24 13487029 ps
T1097 /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.2014907428 Mar 21 02:02:46 PM PDT 24 Mar 21 02:02:48 PM PDT 24 88613812 ps
T1098 /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.34967820 Mar 21 02:02:51 PM PDT 24 Mar 21 02:02:54 PM PDT 24 2026009637 ps
T1099 /workspace/coverage/cover_reg_top/34.spi_device_intr_test.2675019637 Mar 21 02:02:55 PM PDT 24 Mar 21 02:02:57 PM PDT 24 13987091 ps
T1100 /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.3508574507 Mar 21 02:02:49 PM PDT 24 Mar 21 02:02:52 PM PDT 24 483657494 ps
T186 /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.852778969 Mar 21 02:02:45 PM PDT 24 Mar 21 02:02:49 PM PDT 24 488061215 ps
T1101 /workspace/coverage/cover_reg_top/0.spi_device_intr_test.4234290643 Mar 21 02:02:43 PM PDT 24 Mar 21 02:02:45 PM PDT 24 49393852 ps
T1102 /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.4216405745 Mar 21 02:02:47 PM PDT 24 Mar 21 02:02:49 PM PDT 24 36752405 ps
T1103 /workspace/coverage/cover_reg_top/28.spi_device_intr_test.952333076 Mar 21 02:02:52 PM PDT 24 Mar 21 02:02:53 PM PDT 24 14213465 ps
T1104 /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.2031953071 Mar 21 02:02:41 PM PDT 24 Mar 21 02:02:56 PM PDT 24 2703374171 ps
T1105 /workspace/coverage/cover_reg_top/12.spi_device_intr_test.2206131407 Mar 21 02:02:45 PM PDT 24 Mar 21 02:02:46 PM PDT 24 19589880 ps
T1106 /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.2020575372 Mar 21 02:02:50 PM PDT 24 Mar 21 02:02:55 PM PDT 24 237389614 ps
T1107 /workspace/coverage/cover_reg_top/22.spi_device_intr_test.3096104594 Mar 21 02:02:50 PM PDT 24 Mar 21 02:02:52 PM PDT 24 35315375 ps
T1108 /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.4068794877 Mar 21 02:02:48 PM PDT 24 Mar 21 02:02:49 PM PDT 24 27522250 ps
T1109 /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.1210734152 Mar 21 02:02:45 PM PDT 24 Mar 21 02:03:22 PM PDT 24 11310388852 ps
T1110 /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.2497377614 Mar 21 02:02:42 PM PDT 24 Mar 21 02:03:02 PM PDT 24 301837683 ps
T1111 /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.3339995335 Mar 21 02:02:44 PM PDT 24 Mar 21 02:02:50 PM PDT 24 308190051 ps
T1112 /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.1886716263 Mar 21 02:02:45 PM PDT 24 Mar 21 02:03:07 PM PDT 24 1793359325 ps
T1113 /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.2045894617 Mar 21 02:02:42 PM PDT 24 Mar 21 02:02:45 PM PDT 24 181783752 ps

Test location /workspace/coverage/default/13.spi_device_flash_all.305779128
Short name T9
Test name
Test status
Simulation time 30752313537 ps
CPU time 47.57 seconds
Started Mar 21 02:24:24 PM PDT 24
Finished Mar 21 02:25:12 PM PDT 24
Peak memory 249204 kb
Host smart-6b8c0f1d-43ae-4cf7-994e-15af05d506e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305779128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.305779128
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.2722413636
Short name T17
Test name
Test status
Simulation time 7873749024 ps
CPU time 62.61 seconds
Started Mar 21 02:27:03 PM PDT 24
Finished Mar 21 02:28:06 PM PDT 24
Peak memory 239492 kb
Host smart-be18a6ea-f0fa-413c-b078-d014fdb41e50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2722413636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idl
e.2722413636
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.2007687705
Short name T33
Test name
Test status
Simulation time 4128520800 ps
CPU time 20.12 seconds
Started Mar 21 02:23:08 PM PDT 24
Finished Mar 21 02:23:29 PM PDT 24
Peak memory 232972 kb
Host smart-1cdc213c-8446-4dc8-a61b-86284623ffb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007687705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap
.2007687705
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.2542985268
Short name T35
Test name
Test status
Simulation time 97543135254 ps
CPU time 230.71 seconds
Started Mar 21 02:25:34 PM PDT 24
Finished Mar 21 02:29:25 PM PDT 24
Peak memory 250476 kb
Host smart-3ba4cf81-522d-4764-a329-25e5743c4769
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542985268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stre
ss_all.2542985268
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.1469083062
Short name T46
Test name
Test status
Simulation time 152991985810 ps
CPU time 587.81 seconds
Started Mar 21 02:24:39 PM PDT 24
Finished Mar 21 02:34:27 PM PDT 24
Peak memory 281636 kb
Host smart-077b54f8-d972-4ff5-b916-fc54638b8be1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469083062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stre
ss_all.1469083062
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.2912836014
Short name T151
Test name
Test status
Simulation time 2095105593 ps
CPU time 22.4 seconds
Started Mar 21 02:02:45 PM PDT 24
Finished Mar 21 02:03:08 PM PDT 24
Peak memory 219964 kb
Host smart-18070d77-97cd-4141-ad77-08e21dd998b6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912836014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device
_tl_intg_err.2912836014
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.3701062942
Short name T45
Test name
Test status
Simulation time 99469372046 ps
CPU time 484.69 seconds
Started Mar 21 02:27:06 PM PDT 24
Finished Mar 21 02:35:11 PM PDT 24
Peak memory 273300 kb
Host smart-d0fab53c-5464-48ea-ba00-b28326b4cbb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3701062942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.3701062942
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_upload.2265967910
Short name T2
Test name
Test status
Simulation time 2421112395 ps
CPU time 9.12 seconds
Started Mar 21 02:23:35 PM PDT 24
Finished Mar 21 02:23:44 PM PDT 24
Peak memory 229804 kb
Host smart-8f595c35-f18f-43ad-b824-889422142aa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2265967910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.2265967910
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_ram_cfg.1515862895
Short name T496
Test name
Test status
Simulation time 20087994 ps
CPU time 0.74 seconds
Started Mar 21 02:24:04 PM PDT 24
Finished Mar 21 02:24:05 PM PDT 24
Peak memory 216440 kb
Host smart-9a9a2030-ed05-468a-a9ac-ca121cd23f78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1515862895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_ram_cfg.1515862895
Directory /workspace/10.spi_device_ram_cfg/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.1495595172
Short name T104
Test name
Test status
Simulation time 714758498 ps
CPU time 3.64 seconds
Started Mar 21 02:02:49 PM PDT 24
Finished Mar 21 02:02:53 PM PDT 24
Peak memory 215352 kb
Host smart-52b3768e-35b5-47b8-8454-7a7a9709e1a1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495595172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.
1495595172
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.1795032363
Short name T137
Test name
Test status
Simulation time 15211855812 ps
CPU time 170.4 seconds
Started Mar 21 02:27:07 PM PDT 24
Finished Mar 21 02:29:58 PM PDT 24
Peak memory 256372 kb
Host smart-5364443c-224c-4d9e-8942-d601930d0b31
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795032363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stre
ss_all.1795032363
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.3412331659
Short name T34
Test name
Test status
Simulation time 17305770144 ps
CPU time 172.82 seconds
Started Mar 21 02:27:29 PM PDT 24
Finished Mar 21 02:30:23 PM PDT 24
Peak memory 266248 kb
Host smart-3e118d10-965b-411d-b2af-dbbbddc78cf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412331659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idl
e.3412331659
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.1768500967
Short name T178
Test name
Test status
Simulation time 20439566579 ps
CPU time 118.51 seconds
Started Mar 21 02:24:36 PM PDT 24
Finished Mar 21 02:26:34 PM PDT 24
Peak memory 253584 kb
Host smart-83db4129-d984-45a6-86ab-9432f4e2d168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1768500967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.1768500967
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.3555381951
Short name T24
Test name
Test status
Simulation time 83629112250 ps
CPU time 626.29 seconds
Started Mar 21 02:25:17 PM PDT 24
Finished Mar 21 02:35:44 PM PDT 24
Peak memory 282176 kb
Host smart-97656227-c06f-455f-96ad-b019bd9820b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555381951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stre
ss_all.3555381951
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.811220665
Short name T326
Test name
Test status
Simulation time 13633192 ps
CPU time 0.74 seconds
Started Mar 21 02:25:08 PM PDT 24
Finished Mar 21 02:25:09 PM PDT 24
Peak memory 205400 kb
Host smart-098dfb60-5630-4a77-a31c-90e865266e4b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811220665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.811220665
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.1395724631
Short name T52
Test name
Test status
Simulation time 865314702 ps
CPU time 9.85 seconds
Started Mar 21 02:24:12 PM PDT 24
Finished Mar 21 02:24:22 PM PDT 24
Peak memory 224580 kb
Host smart-c49dc241-a817-4302-ae5a-7fb6bd00f845
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395724631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.1395724631
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.984991680
Short name T197
Test name
Test status
Simulation time 103699309030 ps
CPU time 192.48 seconds
Started Mar 21 02:24:30 PM PDT 24
Finished Mar 21 02:27:43 PM PDT 24
Peak memory 269556 kb
Host smart-665e04a5-eecc-402e-93da-a2bb4a7498ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=984991680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idle
.984991680
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.4167196486
Short name T79
Test name
Test status
Simulation time 155401649 ps
CPU time 0.96 seconds
Started Mar 21 02:23:06 PM PDT 24
Finished Mar 21 02:23:07 PM PDT 24
Peak memory 235216 kb
Host smart-b2edd36a-72bc-4910-80dc-2da8e6ffbf32
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167196486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.4167196486
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.3817330400
Short name T277
Test name
Test status
Simulation time 14792292744 ps
CPU time 134.08 seconds
Started Mar 21 02:27:00 PM PDT 24
Finished Mar 21 02:29:15 PM PDT 24
Peak memory 273952 kb
Host smart-e7fa37de-02ec-4e8a-ab06-2019663f3cb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3817330400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idl
e.3817330400
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.227131141
Short name T96
Test name
Test status
Simulation time 38826921 ps
CPU time 0.95 seconds
Started Mar 21 02:02:43 PM PDT 24
Finished Mar 21 02:02:45 PM PDT 24
Peak memory 206756 kb
Host smart-b4f90daa-6a70-495e-9e20-254e697c7972
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227131141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr
_hw_reset.227131141
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.1734805654
Short name T44
Test name
Test status
Simulation time 39077499706 ps
CPU time 194.76 seconds
Started Mar 21 02:26:53 PM PDT 24
Finished Mar 21 02:30:08 PM PDT 24
Peak memory 257640 kb
Host smart-35fdc8a8-ae04-4ed8-8f3a-0765dcf03d9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1734805654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idl
e.1734805654
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_mem_parity.3641130706
Short name T479
Test name
Test status
Simulation time 90366352 ps
CPU time 1.06 seconds
Started Mar 21 02:23:07 PM PDT 24
Finished Mar 21 02:23:08 PM PDT 24
Peak memory 216972 kb
Host smart-88ecd518-83b8-4285-9e73-7085e58a34f6
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641130706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 1.spi_device_mem_parity.3641130706
Directory /workspace/1.spi_device_mem_parity/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.304938149
Short name T236
Test name
Test status
Simulation time 7005751461 ps
CPU time 128.97 seconds
Started Mar 21 02:23:19 PM PDT 24
Finished Mar 21 02:25:28 PM PDT 24
Peak memory 271252 kb
Host smart-0f8d5379-9d8d-486e-a737-d4d1a22eccab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304938149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.304938149
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.2468952322
Short name T138
Test name
Test status
Simulation time 62197787873 ps
CPU time 132.85 seconds
Started Mar 21 02:25:59 PM PDT 24
Finished Mar 21 02:28:12 PM PDT 24
Peak memory 257644 kb
Host smart-c661e515-5bce-4eb8-bd04-db615c904839
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468952322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stre
ss_all.2468952322
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.2301479431
Short name T274
Test name
Test status
Simulation time 70871464723 ps
CPU time 128.73 seconds
Started Mar 21 02:26:50 PM PDT 24
Finished Mar 21 02:28:59 PM PDT 24
Peak memory 257256 kb
Host smart-5d2443a3-05aa-4b4d-ac50-b645edb07cb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2301479431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.2301479431
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.553104940
Short name T221
Test name
Test status
Simulation time 7955618599 ps
CPU time 133.94 seconds
Started Mar 21 02:25:23 PM PDT 24
Finished Mar 21 02:27:37 PM PDT 24
Peak memory 265068 kb
Host smart-b8e65491-adf4-4e26-9e6e-2fb39d929323
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553104940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idle
.553104940
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.3992494146
Short name T59
Test name
Test status
Simulation time 60570137941 ps
CPU time 419.8 seconds
Started Mar 21 02:26:27 PM PDT 24
Finished Mar 21 02:33:27 PM PDT 24
Peak memory 266224 kb
Host smart-a4cb6b87-0a40-4390-866e-72839c83a2ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992494146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stre
ss_all.3992494146
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.4237283013
Short name T16
Test name
Test status
Simulation time 2548449429 ps
CPU time 14.19 seconds
Started Mar 21 02:24:02 PM PDT 24
Finished Mar 21 02:24:16 PM PDT 24
Peak memory 216544 kb
Host smart-37f22490-eb39-4acf-8703-0370a7471615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4237283013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.4237283013
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.746085563
Short name T188
Test name
Test status
Simulation time 1142434311 ps
CPU time 17.5 seconds
Started Mar 21 02:02:40 PM PDT 24
Finished Mar 21 02:02:58 PM PDT 24
Peak memory 216564 kb
Host smart-c1871463-d50b-4b80-86c4-9f00eef8c192
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746085563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_
tl_intg_err.746085563
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.2918620141
Short name T31
Test name
Test status
Simulation time 4328621854 ps
CPU time 53.65 seconds
Started Mar 21 02:26:12 PM PDT 24
Finished Mar 21 02:27:06 PM PDT 24
Peak memory 234376 kb
Host smart-c2fac6dd-a62a-4415-b18b-54df6f798e78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2918620141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idl
e.2918620141
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.2872597573
Short name T290
Test name
Test status
Simulation time 18322513887 ps
CPU time 170.52 seconds
Started Mar 21 02:27:26 PM PDT 24
Finished Mar 21 02:30:17 PM PDT 24
Peak memory 286152 kb
Host smart-a72613e5-f611-4bee-b5e9-b33313a7062a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872597573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stre
ss_all.2872597573
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.3054609246
Short name T184
Test name
Test status
Simulation time 249621288 ps
CPU time 4.82 seconds
Started Mar 21 02:02:43 PM PDT 24
Finished Mar 21 02:02:48 PM PDT 24
Peak memory 215252 kb
Host smart-528ec8a8-a500-4e41-8c91-c85f4fb4a769
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054609246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.3
054609246
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.3797726640
Short name T449
Test name
Test status
Simulation time 25605432955 ps
CPU time 36.45 seconds
Started Mar 21 02:25:37 PM PDT 24
Finished Mar 21 02:26:14 PM PDT 24
Peak memory 232944 kb
Host smart-d997534c-3918-4e8c-a0a1-ba2b1cfcfde6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3797726640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.3797726640
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.3135456548
Short name T297
Test name
Test status
Simulation time 80925101872 ps
CPU time 204.54 seconds
Started Mar 21 02:25:09 PM PDT 24
Finished Mar 21 02:28:33 PM PDT 24
Peak memory 249424 kb
Host smart-cecf0a3f-f9c8-4e22-959f-927db40e79f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3135456548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idl
e.3135456548
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.1049293
Short name T106
Test name
Test status
Simulation time 1197988222 ps
CPU time 18.13 seconds
Started Mar 21 02:02:48 PM PDT 24
Finished Mar 21 02:03:06 PM PDT 24
Peak memory 215384 kb
Host smart-fc21aa02-c6c0-4f04-97e4-b31a23b84246
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_t
l_intg_err.1049293
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.2019843938
Short name T136
Test name
Test status
Simulation time 3630352232 ps
CPU time 67.46 seconds
Started Mar 21 02:23:06 PM PDT 24
Finished Mar 21 02:24:13 PM PDT 24
Peak memory 249860 kb
Host smart-2d6176bf-ba92-4773-b3f1-aadd8f386fd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2019843938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle
.2019843938
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.847990972
Short name T200
Test name
Test status
Simulation time 262018229854 ps
CPU time 332.27 seconds
Started Mar 21 02:25:45 PM PDT 24
Finished Mar 21 02:31:18 PM PDT 24
Peak memory 265716 kb
Host smart-51303c12-3274-43aa-b8bb-aa08bdc85d78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847990972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.847990972
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.1203673525
Short name T300
Test name
Test status
Simulation time 212243443373 ps
CPU time 404.06 seconds
Started Mar 21 02:26:02 PM PDT 24
Finished Mar 21 02:32:46 PM PDT 24
Peak memory 254280 kb
Host smart-f9fc2e38-4a2a-4ad7-b553-df0b6c70bb5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1203673525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idl
e.1203673525
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.2871881659
Short name T286
Test name
Test status
Simulation time 294272476338 ps
CPU time 442.88 seconds
Started Mar 21 02:26:29 PM PDT 24
Finished Mar 21 02:33:52 PM PDT 24
Peak memory 267580 kb
Host smart-f66ff0c3-76bc-41fb-aeca-67d7faa062db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2871881659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.2871881659
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.3604521727
Short name T219
Test name
Test status
Simulation time 7180823449 ps
CPU time 94.8 seconds
Started Mar 21 02:26:52 PM PDT 24
Finished Mar 21 02:28:27 PM PDT 24
Peak memory 266180 kb
Host smart-ba9bf381-c30f-49a8-a0e3-d15aea42d9fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3604521727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.3604521727
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.3982603085
Short name T306
Test name
Test status
Simulation time 135669511355 ps
CPU time 452.86 seconds
Started Mar 21 02:24:06 PM PDT 24
Finished Mar 21 02:31:39 PM PDT 24
Peak memory 256896 kb
Host smart-b3d19cd1-b880-45d0-ae72-0dacbdc45f14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982603085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle
.3982603085
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.2898303987
Short name T4
Test name
Test status
Simulation time 6855504081 ps
CPU time 17.08 seconds
Started Mar 21 02:26:53 PM PDT 24
Finished Mar 21 02:27:10 PM PDT 24
Peak memory 248964 kb
Host smart-d2914bc0-2e83-4ab2-89df-89266a887407
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898303987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.2898303987
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.1166197884
Short name T291
Test name
Test status
Simulation time 7748601782 ps
CPU time 73.92 seconds
Started Mar 21 02:24:25 PM PDT 24
Finished Mar 21 02:25:39 PM PDT 24
Peak memory 250580 kb
Host smart-66575f2d-8575-4d51-a15c-dce308853580
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166197884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.1166197884
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.3863151653
Short name T285
Test name
Test status
Simulation time 123099255333 ps
CPU time 297.44 seconds
Started Mar 21 02:25:23 PM PDT 24
Finished Mar 21 02:30:21 PM PDT 24
Peak memory 254456 kb
Host smart-2c8f1695-cc3d-45dc-8a62-4fb289f6becd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3863151653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.3863151653
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.72973277
Short name T304
Test name
Test status
Simulation time 117238650474 ps
CPU time 173.61 seconds
Started Mar 21 02:24:03 PM PDT 24
Finished Mar 21 02:26:57 PM PDT 24
Peak memory 240680 kb
Host smart-bd87da3a-2153-40d9-858d-eaf3fea1c170
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72973277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.72973277
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.2988885211
Short name T1035
Test name
Test status
Simulation time 909719227 ps
CPU time 5.31 seconds
Started Mar 21 02:02:45 PM PDT 24
Finished Mar 21 02:02:51 PM PDT 24
Peak memory 216344 kb
Host smart-1674120a-d441-44da-8602-ba9b73abf7e9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988885211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.
2988885211
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.1775193457
Short name T100
Test name
Test status
Simulation time 178048500 ps
CPU time 0.96 seconds
Started Mar 21 02:02:37 PM PDT 24
Finished Mar 21 02:02:38 PM PDT 24
Peak memory 206716 kb
Host smart-9985124b-de7d-4cb8-8f42-4545d632ba3b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775193457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_hw_reset.1775193457
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.1645001809
Short name T115
Test name
Test status
Simulation time 367236071 ps
CPU time 9 seconds
Started Mar 21 02:02:45 PM PDT 24
Finished Mar 21 02:02:55 PM PDT 24
Peak memory 215204 kb
Host smart-9b9fba22-77ad-4147-95ae-86463be5d617
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645001809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_devic
e_tl_intg_err.1645001809
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.1692316392
Short name T119
Test name
Test status
Simulation time 623705622 ps
CPU time 17.46 seconds
Started Mar 21 02:02:50 PM PDT 24
Finished Mar 21 02:03:08 PM PDT 24
Peak memory 215196 kb
Host smart-125564bb-e0c5-4a21-8563-02b7765037ba
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692316392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_devic
e_tl_intg_err.1692316392
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.4217090495
Short name T1084
Test name
Test status
Simulation time 424095457 ps
CPU time 14.3 seconds
Started Mar 21 02:02:39 PM PDT 24
Finished Mar 21 02:02:54 PM PDT 24
Peak memory 206980 kb
Host smart-f5d20758-3b61-4ab1-baff-44f96e561987
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217090495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_aliasing.4217090495
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.1210734152
Short name T1109
Test name
Test status
Simulation time 11310388852 ps
CPU time 36.7 seconds
Started Mar 21 02:02:45 PM PDT 24
Finished Mar 21 02:03:22 PM PDT 24
Peak memory 207216 kb
Host smart-db63c819-cc9e-4906-8947-a8ed13b0b23d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210734152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_bit_bash.1210734152
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.485727713
Short name T1080
Test name
Test status
Simulation time 50712412 ps
CPU time 1.85 seconds
Started Mar 21 02:02:41 PM PDT 24
Finished Mar 21 02:02:43 PM PDT 24
Peak memory 215152 kb
Host smart-32b463ef-34f6-4aa5-b88c-52f867977110
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485727713 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.485727713
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.2190761305
Short name T1013
Test name
Test status
Simulation time 143831470 ps
CPU time 1.27 seconds
Started Mar 21 02:02:41 PM PDT 24
Finished Mar 21 02:02:42 PM PDT 24
Peak memory 206892 kb
Host smart-00c9423a-7f77-403c-8486-64fb7b40e888
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190761305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.2
190761305
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.4234290643
Short name T1101
Test name
Test status
Simulation time 49393852 ps
CPU time 0.72 seconds
Started Mar 21 02:02:43 PM PDT 24
Finished Mar 21 02:02:45 PM PDT 24
Peak memory 203300 kb
Host smart-7fdc4c26-2d81-4039-b8ad-7837e90690f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234290643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.4
234290643
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.2805578413
Short name T127
Test name
Test status
Simulation time 126965903 ps
CPU time 2.19 seconds
Started Mar 21 02:02:40 PM PDT 24
Finished Mar 21 02:02:42 PM PDT 24
Peak memory 215128 kb
Host smart-b08d27d7-2ccf-49b8-a196-b70de7154ad6
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805578413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi
_device_mem_partial_access.2805578413
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.2791546646
Short name T1002
Test name
Test status
Simulation time 42009884 ps
CPU time 0.66 seconds
Started Mar 21 02:02:41 PM PDT 24
Finished Mar 21 02:02:42 PM PDT 24
Peak memory 203256 kb
Host smart-219feff1-5dec-485f-aaf8-da913783edbc
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791546646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_me
m_walk.2791546646
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.273557056
Short name T1087
Test name
Test status
Simulation time 452144600 ps
CPU time 2.8 seconds
Started Mar 21 02:02:41 PM PDT 24
Finished Mar 21 02:02:44 PM PDT 24
Peak memory 215112 kb
Host smart-6147f48b-8079-4e93-9d69-5ba2a14b2ec5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273557056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sp
i_device_same_csr_outstanding.273557056
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.3806923748
Short name T111
Test name
Test status
Simulation time 1129861321 ps
CPU time 3.44 seconds
Started Mar 21 02:02:40 PM PDT 24
Finished Mar 21 02:02:43 PM PDT 24
Peak memory 215204 kb
Host smart-1e8fb83c-e29d-45d5-a498-56fbe91c2584
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806923748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.3
806923748
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.3906809763
Short name T189
Test name
Test status
Simulation time 820581998 ps
CPU time 13.3 seconds
Started Mar 21 02:02:41 PM PDT 24
Finished Mar 21 02:02:55 PM PDT 24
Peak memory 215568 kb
Host smart-34011430-8304-454f-ba72-a15e9807d69e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906809763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.3906809763
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.3302395792
Short name T1071
Test name
Test status
Simulation time 222709559 ps
CPU time 7.03 seconds
Started Mar 21 02:02:44 PM PDT 24
Finished Mar 21 02:02:51 PM PDT 24
Peak memory 215212 kb
Host smart-1ab75a07-4244-48d8-9bee-7073b3b28688
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302395792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_aliasing.3302395792
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.3883984654
Short name T1079
Test name
Test status
Simulation time 5213495332 ps
CPU time 35.13 seconds
Started Mar 21 02:02:43 PM PDT 24
Finished Mar 21 02:03:18 PM PDT 24
Peak memory 206972 kb
Host smart-9ef21d25-2dd6-4d97-9cf6-ed3b2f70dfcf
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883984654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_bit_bash.3883984654
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.761267186
Short name T99
Test name
Test status
Simulation time 78629531 ps
CPU time 1.12 seconds
Started Mar 21 02:02:40 PM PDT 24
Finished Mar 21 02:02:42 PM PDT 24
Peak memory 206904 kb
Host smart-06d6e98e-08cf-4d4d-89c0-87192851e912
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761267186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr
_hw_reset.761267186
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.4154178528
Short name T156
Test name
Test status
Simulation time 386902943 ps
CPU time 2.73 seconds
Started Mar 21 02:02:42 PM PDT 24
Finished Mar 21 02:02:45 PM PDT 24
Peak memory 216632 kb
Host smart-a9222eea-ab76-451e-b76d-23d046c3488f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154178528 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.4154178528
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.3665501431
Short name T1078
Test name
Test status
Simulation time 159478247 ps
CPU time 2.24 seconds
Started Mar 21 02:02:39 PM PDT 24
Finished Mar 21 02:02:41 PM PDT 24
Peak memory 215108 kb
Host smart-ebe425b7-c88f-4ac8-b7ba-29bdb32cc894
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665501431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.3
665501431
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.1377468292
Short name T1015
Test name
Test status
Simulation time 27040113 ps
CPU time 0.78 seconds
Started Mar 21 02:02:42 PM PDT 24
Finished Mar 21 02:02:43 PM PDT 24
Peak memory 203268 kb
Host smart-2b563d8f-2413-4d46-ad4e-353ae1d51ec0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377468292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.1
377468292
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.3319065994
Short name T123
Test name
Test status
Simulation time 477253519 ps
CPU time 1.34 seconds
Started Mar 21 02:02:40 PM PDT 24
Finished Mar 21 02:02:42 PM PDT 24
Peak memory 215028 kb
Host smart-203aeb7b-e4e5-4299-8704-86047cd960c8
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319065994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi
_device_mem_partial_access.3319065994
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.131960788
Short name T1088
Test name
Test status
Simulation time 41612287 ps
CPU time 0.66 seconds
Started Mar 21 02:02:40 PM PDT 24
Finished Mar 21 02:02:41 PM PDT 24
Peak memory 203296 kb
Host smart-cbfd3578-bfbd-4fbf-b697-ccd3f16bf674
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131960788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_mem
_walk.131960788
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.2457169879
Short name T1095
Test name
Test status
Simulation time 53785415 ps
CPU time 1.81 seconds
Started Mar 21 02:02:41 PM PDT 24
Finished Mar 21 02:02:43 PM PDT 24
Peak memory 215108 kb
Host smart-1032e259-fd55-4110-8d48-6ebae25f16fb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457169879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s
pi_device_same_csr_outstanding.2457169879
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.3228795683
Short name T1057
Test name
Test status
Simulation time 71194562 ps
CPU time 4.91 seconds
Started Mar 21 02:02:43 PM PDT 24
Finished Mar 21 02:02:49 PM PDT 24
Peak memory 216208 kb
Host smart-9fe613a5-1ff7-4d93-b1fe-1138f2630eef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228795683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.3
228795683
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.3129468889
Short name T116
Test name
Test status
Simulation time 84197492 ps
CPU time 3.18 seconds
Started Mar 21 02:02:47 PM PDT 24
Finished Mar 21 02:02:50 PM PDT 24
Peak memory 216184 kb
Host smart-ce477f5d-b116-4f6a-b1e9-02cc8a8c66a2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129468889 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.3129468889
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.3664639812
Short name T131
Test name
Test status
Simulation time 34927985 ps
CPU time 2.51 seconds
Started Mar 21 02:02:44 PM PDT 24
Finished Mar 21 02:02:48 PM PDT 24
Peak memory 206864 kb
Host smart-7b001103-c97c-4bd4-a8c4-666db00f314c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664639812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.
3664639812
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.1528434142
Short name T1000
Test name
Test status
Simulation time 43610767 ps
CPU time 0.71 seconds
Started Mar 21 02:02:46 PM PDT 24
Finished Mar 21 02:02:47 PM PDT 24
Peak memory 203288 kb
Host smart-57168837-df03-47cf-9cd9-d03857daa338
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528434142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.
1528434142
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.3065338546
Short name T1038
Test name
Test status
Simulation time 171598451 ps
CPU time 2.84 seconds
Started Mar 21 02:02:41 PM PDT 24
Finished Mar 21 02:02:44 PM PDT 24
Peak memory 215152 kb
Host smart-73a9675a-12fd-46b7-b81c-f163ca664e45
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065338546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
spi_device_same_csr_outstanding.3065338546
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.367192740
Short name T191
Test name
Test status
Simulation time 1158522144 ps
CPU time 15.42 seconds
Started Mar 21 02:02:46 PM PDT 24
Finished Mar 21 02:03:02 PM PDT 24
Peak memory 215268 kb
Host smart-98b066db-1c86-4b7d-ae78-4a750944f407
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367192740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device
_tl_intg_err.367192740
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.1851209458
Short name T1068
Test name
Test status
Simulation time 358723571 ps
CPU time 2.7 seconds
Started Mar 21 02:02:48 PM PDT 24
Finished Mar 21 02:02:51 PM PDT 24
Peak memory 216132 kb
Host smart-8da8fb6b-8a5d-4ec8-be87-2e7e6e7a2f16
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851209458 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.1851209458
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.1882868583
Short name T1083
Test name
Test status
Simulation time 38820222 ps
CPU time 1.31 seconds
Started Mar 21 02:02:47 PM PDT 24
Finished Mar 21 02:02:49 PM PDT 24
Peak memory 206844 kb
Host smart-51e9db98-4f04-44c5-a63b-91ca3c6b94fb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882868583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.
1882868583
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.3278835276
Short name T1069
Test name
Test status
Simulation time 38209247 ps
CPU time 0.72 seconds
Started Mar 21 02:02:47 PM PDT 24
Finished Mar 21 02:02:48 PM PDT 24
Peak memory 203308 kb
Host smart-da5155e7-1fca-468a-a468-aabf9fefb700
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278835276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.
3278835276
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.2175399284
Short name T1085
Test name
Test status
Simulation time 148909013 ps
CPU time 3.36 seconds
Started Mar 21 02:02:46 PM PDT 24
Finished Mar 21 02:02:50 PM PDT 24
Peak memory 215148 kb
Host smart-6ca8b9f2-426c-4aef-858e-7cbbd9789d5e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175399284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
spi_device_same_csr_outstanding.2175399284
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.1575065019
Short name T114
Test name
Test status
Simulation time 226919831 ps
CPU time 2.2 seconds
Started Mar 21 02:02:46 PM PDT 24
Finished Mar 21 02:02:48 PM PDT 24
Peak memory 215272 kb
Host smart-b26bfd4f-a333-4350-9c18-e99f619d50ac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575065019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.
1575065019
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.4068794877
Short name T1108
Test name
Test status
Simulation time 27522250 ps
CPU time 1.8 seconds
Started Mar 21 02:02:48 PM PDT 24
Finished Mar 21 02:02:49 PM PDT 24
Peak memory 216156 kb
Host smart-7e00421c-07c9-4a6e-ba63-c33fdcae3a76
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068794877 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.4068794877
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.1118519586
Short name T1077
Test name
Test status
Simulation time 64800959 ps
CPU time 1.17 seconds
Started Mar 21 02:02:47 PM PDT 24
Finished Mar 21 02:02:48 PM PDT 24
Peak memory 206936 kb
Host smart-2c3c4f71-9615-4006-8efb-0cde39bd74d1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118519586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.
1118519586
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.2206131407
Short name T1105
Test name
Test status
Simulation time 19589880 ps
CPU time 0.7 seconds
Started Mar 21 02:02:45 PM PDT 24
Finished Mar 21 02:02:46 PM PDT 24
Peak memory 203300 kb
Host smart-70e1f8f8-963b-47f7-a783-3a5f6883cf31
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206131407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.
2206131407
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.1626000170
Short name T148
Test name
Test status
Simulation time 547818100 ps
CPU time 4.34 seconds
Started Mar 21 02:02:48 PM PDT 24
Finished Mar 21 02:02:52 PM PDT 24
Peak memory 215128 kb
Host smart-df22e41c-d35f-4f6e-8e3b-10b0e7fd0443
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626000170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
spi_device_same_csr_outstanding.1626000170
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.3121772377
Short name T113
Test name
Test status
Simulation time 133393079 ps
CPU time 4.35 seconds
Started Mar 21 02:02:47 PM PDT 24
Finished Mar 21 02:02:52 PM PDT 24
Peak memory 215236 kb
Host smart-377809e0-a737-44f2-8c8d-23013f5c7628
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121772377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.
3121772377
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.1640198487
Short name T1039
Test name
Test status
Simulation time 74241616 ps
CPU time 3.34 seconds
Started Mar 21 02:02:47 PM PDT 24
Finished Mar 21 02:02:50 PM PDT 24
Peak memory 216688 kb
Host smart-be76a591-ed35-4a14-8835-80d9221005e3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640198487 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.1640198487
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.4198013312
Short name T147
Test name
Test status
Simulation time 166525425 ps
CPU time 2.11 seconds
Started Mar 21 02:02:46 PM PDT 24
Finished Mar 21 02:02:49 PM PDT 24
Peak memory 215164 kb
Host smart-2be92406-e378-45c8-a861-a53fd620c9e6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198013312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.
4198013312
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.244840494
Short name T1096
Test name
Test status
Simulation time 13487029 ps
CPU time 0.76 seconds
Started Mar 21 02:02:58 PM PDT 24
Finished Mar 21 02:03:01 PM PDT 24
Peak memory 203300 kb
Host smart-e8826282-67f6-45e0-9db7-2e4b051ead28
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244840494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.244840494
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.2068472650
Short name T1052
Test name
Test status
Simulation time 917004144 ps
CPU time 4.59 seconds
Started Mar 21 02:02:49 PM PDT 24
Finished Mar 21 02:02:54 PM PDT 24
Peak memory 215160 kb
Host smart-6bdc3618-bcdd-4cc6-88fb-8d890746d88e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068472650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
spi_device_same_csr_outstanding.2068472650
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.778052110
Short name T120
Test name
Test status
Simulation time 106407496 ps
CPU time 3.15 seconds
Started Mar 21 02:02:46 PM PDT 24
Finished Mar 21 02:02:50 PM PDT 24
Peak memory 215236 kb
Host smart-a49b0445-a58e-41d4-9e6e-e91125c63cf2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778052110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.778052110
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.1889194412
Short name T1062
Test name
Test status
Simulation time 792383743 ps
CPU time 12.99 seconds
Started Mar 21 02:03:11 PM PDT 24
Finished Mar 21 02:03:25 PM PDT 24
Peak memory 215420 kb
Host smart-12557c83-cece-4e39-96f6-222d4d44fea6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889194412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_devic
e_tl_intg_err.1889194412
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.560119793
Short name T149
Test name
Test status
Simulation time 116616783 ps
CPU time 2.76 seconds
Started Mar 21 02:02:51 PM PDT 24
Finished Mar 21 02:02:54 PM PDT 24
Peak memory 216216 kb
Host smart-d10d2f59-b33d-41be-9866-2deec4fe820c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560119793 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.560119793
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.3718122984
Short name T128
Test name
Test status
Simulation time 387400367 ps
CPU time 2.73 seconds
Started Mar 21 02:02:46 PM PDT 24
Finished Mar 21 02:02:50 PM PDT 24
Peak memory 214672 kb
Host smart-4380985b-7dbb-4086-9505-fac0f9df73d4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718122984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.
3718122984
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.2198199307
Short name T1086
Test name
Test status
Simulation time 43215917 ps
CPU time 0.72 seconds
Started Mar 21 02:02:50 PM PDT 24
Finished Mar 21 02:02:51 PM PDT 24
Peak memory 203632 kb
Host smart-b8499080-9eb1-4afb-97ae-629134531621
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198199307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.
2198199307
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.786703576
Short name T1006
Test name
Test status
Simulation time 104988596 ps
CPU time 3.09 seconds
Started Mar 21 02:02:50 PM PDT 24
Finished Mar 21 02:02:54 PM PDT 24
Peak memory 215080 kb
Host smart-64822c27-cd7a-4ac1-b528-2e0975186322
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786703576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.s
pi_device_same_csr_outstanding.786703576
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.1874447176
Short name T107
Test name
Test status
Simulation time 316453175 ps
CPU time 17.29 seconds
Started Mar 21 02:02:50 PM PDT 24
Finished Mar 21 02:03:08 PM PDT 24
Peak memory 215868 kb
Host smart-a1f9a4e5-ad99-4855-9a75-bbd926c04303
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874447176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_devic
e_tl_intg_err.1874447176
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.1869689881
Short name T1021
Test name
Test status
Simulation time 309840952 ps
CPU time 2.85 seconds
Started Mar 21 02:02:49 PM PDT 24
Finished Mar 21 02:02:52 PM PDT 24
Peak memory 216296 kb
Host smart-fbeb5909-7f24-4ab4-a7ad-407f83bb4a74
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869689881 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.1869689881
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.563660738
Short name T130
Test name
Test status
Simulation time 59593779 ps
CPU time 2.28 seconds
Started Mar 21 02:02:40 PM PDT 24
Finished Mar 21 02:02:43 PM PDT 24
Peak memory 215128 kb
Host smart-1953aa12-190b-4c8a-a6e3-8f9b1262bdf6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563660738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.563660738
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.136282394
Short name T1017
Test name
Test status
Simulation time 12623004 ps
CPU time 0.79 seconds
Started Mar 21 02:02:42 PM PDT 24
Finished Mar 21 02:02:43 PM PDT 24
Peak memory 203292 kb
Host smart-2f5671ea-b263-49fe-849f-3344d16bebb6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136282394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.136282394
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.3861577100
Short name T1037
Test name
Test status
Simulation time 61264779 ps
CPU time 1.76 seconds
Started Mar 21 02:02:41 PM PDT 24
Finished Mar 21 02:02:43 PM PDT 24
Peak memory 206972 kb
Host smart-bae513ce-0999-476a-9f5c-54b1c5707e59
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861577100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
spi_device_same_csr_outstanding.3861577100
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.1268306139
Short name T108
Test name
Test status
Simulation time 383745941 ps
CPU time 3.04 seconds
Started Mar 21 02:02:50 PM PDT 24
Finished Mar 21 02:02:54 PM PDT 24
Peak memory 216224 kb
Host smart-4a0a0df4-0e3e-489e-9416-386d779a41ba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268306139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.
1268306139
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.1419673999
Short name T190
Test name
Test status
Simulation time 7992859349 ps
CPU time 15.17 seconds
Started Mar 21 02:02:50 PM PDT 24
Finished Mar 21 02:03:06 PM PDT 24
Peak memory 215468 kb
Host smart-8e20bb8d-e531-4d50-92ab-8c2401b06a97
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419673999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_devic
e_tl_intg_err.1419673999
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.1669845221
Short name T1033
Test name
Test status
Simulation time 41740462 ps
CPU time 1.54 seconds
Started Mar 21 02:02:50 PM PDT 24
Finished Mar 21 02:02:52 PM PDT 24
Peak memory 215312 kb
Host smart-b2cf460c-1f79-44ba-a0f2-f3889956519c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669845221 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.1669845221
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.2337631866
Short name T124
Test name
Test status
Simulation time 35934392 ps
CPU time 2.27 seconds
Started Mar 21 02:02:49 PM PDT 24
Finished Mar 21 02:02:51 PM PDT 24
Peak memory 215148 kb
Host smart-0a6d1bec-d6d5-4019-b2e4-18c23fd2fd6e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337631866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.
2337631866
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.1000575287
Short name T1040
Test name
Test status
Simulation time 59783119 ps
CPU time 0.74 seconds
Started Mar 21 02:02:49 PM PDT 24
Finished Mar 21 02:02:50 PM PDT 24
Peak memory 203280 kb
Host smart-0a47f598-92f5-4971-a63b-21698c43eb12
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000575287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.
1000575287
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.3508574507
Short name T1100
Test name
Test status
Simulation time 483657494 ps
CPU time 3.19 seconds
Started Mar 21 02:02:49 PM PDT 24
Finished Mar 21 02:02:52 PM PDT 24
Peak memory 215048 kb
Host smart-ebfda807-2223-448b-a076-3ec5b9b1f073
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508574507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
spi_device_same_csr_outstanding.3508574507
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.3355652091
Short name T117
Test name
Test status
Simulation time 119502086 ps
CPU time 1.87 seconds
Started Mar 21 02:02:41 PM PDT 24
Finished Mar 21 02:02:43 PM PDT 24
Peak memory 215312 kb
Host smart-3d35bebd-7dc2-4807-b73b-7ce8417879f9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355652091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.
3355652091
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.2031953071
Short name T1104
Test name
Test status
Simulation time 2703374171 ps
CPU time 14.95 seconds
Started Mar 21 02:02:41 PM PDT 24
Finished Mar 21 02:02:56 PM PDT 24
Peak memory 215392 kb
Host smart-1cd93af7-84d6-440b-82e8-59288adca9fc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031953071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_devic
e_tl_intg_err.2031953071
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.1601639735
Short name T1030
Test name
Test status
Simulation time 46446007 ps
CPU time 1.68 seconds
Started Mar 21 02:02:55 PM PDT 24
Finished Mar 21 02:02:58 PM PDT 24
Peak memory 215300 kb
Host smart-01208bbd-4539-4c1e-8667-d856f1148d15
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601639735 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.1601639735
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.3953144809
Short name T1042
Test name
Test status
Simulation time 141825422 ps
CPU time 1.77 seconds
Started Mar 21 02:02:50 PM PDT 24
Finished Mar 21 02:02:53 PM PDT 24
Peak memory 206852 kb
Host smart-1e6d7f3e-a9e6-43b1-b3be-cf7902f9b2a5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953144809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.
3953144809
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.1524533791
Short name T1024
Test name
Test status
Simulation time 38569847 ps
CPU time 0.72 seconds
Started Mar 21 02:02:54 PM PDT 24
Finished Mar 21 02:02:56 PM PDT 24
Peak memory 203568 kb
Host smart-ac976534-5a0f-4ff4-a3ae-5260eac4d49b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524533791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.
1524533791
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.2013550056
Short name T1061
Test name
Test status
Simulation time 120828561 ps
CPU time 1.82 seconds
Started Mar 21 02:02:50 PM PDT 24
Finished Mar 21 02:02:52 PM PDT 24
Peak memory 215104 kb
Host smart-a7d3ee62-ee4c-4110-902f-1bb0de871722
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013550056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
spi_device_same_csr_outstanding.2013550056
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.316872029
Short name T112
Test name
Test status
Simulation time 146023981 ps
CPU time 2.33 seconds
Started Mar 21 02:02:51 PM PDT 24
Finished Mar 21 02:02:54 PM PDT 24
Peak memory 215280 kb
Host smart-d7ac47ae-3482-47e0-a14c-99c5a855bfa8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316872029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.316872029
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.3759623321
Short name T1065
Test name
Test status
Simulation time 275881063 ps
CPU time 3.44 seconds
Started Mar 21 02:02:51 PM PDT 24
Finished Mar 21 02:02:54 PM PDT 24
Peak memory 217020 kb
Host smart-2a57668c-9a53-40b4-bf1c-c8bf88ef6952
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759623321 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.3759623321
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.1057562518
Short name T132
Test name
Test status
Simulation time 96394456 ps
CPU time 1.81 seconds
Started Mar 21 02:02:49 PM PDT 24
Finished Mar 21 02:02:51 PM PDT 24
Peak memory 215124 kb
Host smart-3dc7487a-01c3-4ef6-8b61-56db1d3de66f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057562518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.
1057562518
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.1201425926
Short name T1008
Test name
Test status
Simulation time 19585351 ps
CPU time 0.7 seconds
Started Mar 21 02:02:53 PM PDT 24
Finished Mar 21 02:02:54 PM PDT 24
Peak memory 203344 kb
Host smart-c5a41053-b81b-47e4-b4cc-0adf98dab54e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201425926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.
1201425926
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.3246766657
Short name T1050
Test name
Test status
Simulation time 46699555 ps
CPU time 2.9 seconds
Started Mar 21 02:02:50 PM PDT 24
Finished Mar 21 02:02:54 PM PDT 24
Peak memory 215148 kb
Host smart-d5d5e1f6-024b-4401-8594-7a44258c9774
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246766657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
spi_device_same_csr_outstanding.3246766657
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.2519870622
Short name T1059
Test name
Test status
Simulation time 63746656 ps
CPU time 3.86 seconds
Started Mar 21 02:02:55 PM PDT 24
Finished Mar 21 02:02:59 PM PDT 24
Peak memory 215288 kb
Host smart-2edd21fa-ab63-4285-89fc-bac603db646b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519870622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.
2519870622
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.3178641751
Short name T152
Test name
Test status
Simulation time 2403409421 ps
CPU time 6.91 seconds
Started Mar 21 02:02:53 PM PDT 24
Finished Mar 21 02:03:00 PM PDT 24
Peak memory 216644 kb
Host smart-f5b3187c-58c5-406c-b69c-af90db776c97
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178641751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_devic
e_tl_intg_err.3178641751
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.34967820
Short name T1098
Test name
Test status
Simulation time 2026009637 ps
CPU time 2.69 seconds
Started Mar 21 02:02:51 PM PDT 24
Finished Mar 21 02:02:54 PM PDT 24
Peak memory 216168 kb
Host smart-e7e4f7a6-6add-4ff3-8ee0-eb88f509b217
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34967820 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.34967820
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.4001903813
Short name T1034
Test name
Test status
Simulation time 64549020 ps
CPU time 2.07 seconds
Started Mar 21 02:02:51 PM PDT 24
Finished Mar 21 02:02:53 PM PDT 24
Peak memory 215160 kb
Host smart-5778d947-a7d3-4c2a-8163-194d6de6f478
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001903813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.
4001903813
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.674750987
Short name T1067
Test name
Test status
Simulation time 11150683 ps
CPU time 0.7 seconds
Started Mar 21 02:02:51 PM PDT 24
Finished Mar 21 02:02:52 PM PDT 24
Peak memory 203328 kb
Host smart-ff78fc89-bee0-46c4-a16e-d054d210f82c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674750987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.674750987
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.2927092098
Short name T155
Test name
Test status
Simulation time 65396818 ps
CPU time 1.67 seconds
Started Mar 21 02:02:55 PM PDT 24
Finished Mar 21 02:02:57 PM PDT 24
Peak memory 206948 kb
Host smart-48a854ff-ad9e-4e2a-b551-58c53b8224ab
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927092098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
spi_device_same_csr_outstanding.2927092098
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.2962816087
Short name T1090
Test name
Test status
Simulation time 80641248 ps
CPU time 3.26 seconds
Started Mar 21 02:02:50 PM PDT 24
Finished Mar 21 02:02:54 PM PDT 24
Peak memory 216292 kb
Host smart-ba846e68-281b-4da6-b4a1-7def4e99e114
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962816087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.
2962816087
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.249479480
Short name T187
Test name
Test status
Simulation time 299318660 ps
CPU time 18.56 seconds
Started Mar 21 02:02:50 PM PDT 24
Finished Mar 21 02:03:09 PM PDT 24
Peak memory 215140 kb
Host smart-621914d8-3646-4a96-a770-6a3ed67ed201
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249479480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device
_tl_intg_err.249479480
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.1886716263
Short name T1112
Test name
Test status
Simulation time 1793359325 ps
CPU time 21.68 seconds
Started Mar 21 02:02:45 PM PDT 24
Finished Mar 21 02:03:07 PM PDT 24
Peak memory 215164 kb
Host smart-531da200-68e8-45d8-82bd-2b63d91d5f5e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886716263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_aliasing.1886716263
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.2139254443
Short name T125
Test name
Test status
Simulation time 1064593802 ps
CPU time 33.6 seconds
Started Mar 21 02:02:45 PM PDT 24
Finished Mar 21 02:03:20 PM PDT 24
Peak memory 206924 kb
Host smart-666429bd-3b82-4cc7-8032-2e91a89c2b93
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139254443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_bit_bash.2139254443
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.54660441
Short name T98
Test name
Test status
Simulation time 184137722 ps
CPU time 0.91 seconds
Started Mar 21 02:02:43 PM PDT 24
Finished Mar 21 02:02:44 PM PDT 24
Peak memory 206692 kb
Host smart-78ed6272-2769-475a-b212-3f8beb04aa88
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54660441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_
hw_reset.54660441
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.2020575372
Short name T1106
Test name
Test status
Simulation time 237389614 ps
CPU time 3.79 seconds
Started Mar 21 02:02:50 PM PDT 24
Finished Mar 21 02:02:55 PM PDT 24
Peak memory 216800 kb
Host smart-ffc5d089-acda-4f2b-bedc-3fc6ae62a0b6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020575372 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.2020575372
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.399502994
Short name T1005
Test name
Test status
Simulation time 128002009 ps
CPU time 1.92 seconds
Started Mar 21 02:02:49 PM PDT 24
Finished Mar 21 02:02:51 PM PDT 24
Peak memory 206900 kb
Host smart-d819a648-eb17-458a-bcb5-ba396b807276
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399502994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.399502994
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.4104622660
Short name T1058
Test name
Test status
Simulation time 29606342 ps
CPU time 0.69 seconds
Started Mar 21 02:02:42 PM PDT 24
Finished Mar 21 02:02:44 PM PDT 24
Peak memory 203268 kb
Host smart-1fae9c43-b676-49af-ab96-1bbb02b51d5e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104622660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.4
104622660
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.4193063954
Short name T1076
Test name
Test status
Simulation time 37422105 ps
CPU time 1.26 seconds
Started Mar 21 02:02:42 PM PDT 24
Finished Mar 21 02:02:43 PM PDT 24
Peak memory 215144 kb
Host smart-cac133ee-c9d5-44a6-8d6d-fa3dbdd5339b
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193063954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi
_device_mem_partial_access.4193063954
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.2263345903
Short name T1066
Test name
Test status
Simulation time 36591979 ps
CPU time 0.74 seconds
Started Mar 21 02:02:41 PM PDT 24
Finished Mar 21 02:02:42 PM PDT 24
Peak memory 203236 kb
Host smart-af8bc0a3-2ed9-4508-9fa3-5edd8553339e
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263345903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_me
m_walk.2263345903
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.3914950170
Short name T154
Test name
Test status
Simulation time 131054840 ps
CPU time 1.77 seconds
Started Mar 21 02:02:45 PM PDT 24
Finished Mar 21 02:02:48 PM PDT 24
Peak memory 215120 kb
Host smart-ca7a3dd8-0a7b-48cb-8562-e19481285a66
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914950170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s
pi_device_same_csr_outstanding.3914950170
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.3205398600
Short name T1051
Test name
Test status
Simulation time 63271020 ps
CPU time 4.57 seconds
Started Mar 21 02:02:40 PM PDT 24
Finished Mar 21 02:02:45 PM PDT 24
Peak memory 215176 kb
Host smart-4f698d0e-ea17-4550-8c18-afc0f34c413b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205398600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.3
205398600
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.2698179059
Short name T1045
Test name
Test status
Simulation time 383990300 ps
CPU time 19.56 seconds
Started Mar 21 02:02:44 PM PDT 24
Finished Mar 21 02:03:03 PM PDT 24
Peak memory 215140 kb
Host smart-92e428fa-ee60-45e1-8ee2-a330d153f5bf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698179059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device
_tl_intg_err.2698179059
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.133954029
Short name T1004
Test name
Test status
Simulation time 178983621 ps
CPU time 0.76 seconds
Started Mar 21 02:02:50 PM PDT 24
Finished Mar 21 02:02:51 PM PDT 24
Peak memory 203344 kb
Host smart-d9d33092-27ac-473d-ad2d-9b0f66e9f4f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133954029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.133954029
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.1801037097
Short name T1075
Test name
Test status
Simulation time 42717174 ps
CPU time 0.69 seconds
Started Mar 21 02:02:49 PM PDT 24
Finished Mar 21 02:02:50 PM PDT 24
Peak memory 203328 kb
Host smart-b355bc84-facc-4641-9dc9-9b66a4589e4f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801037097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.
1801037097
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.3096104594
Short name T1107
Test name
Test status
Simulation time 35315375 ps
CPU time 0.8 seconds
Started Mar 21 02:02:50 PM PDT 24
Finished Mar 21 02:02:52 PM PDT 24
Peak memory 203324 kb
Host smart-ee2578cd-b077-4852-a6ed-d997c4b8953f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096104594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.
3096104594
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.609184856
Short name T1009
Test name
Test status
Simulation time 54797308 ps
CPU time 0.69 seconds
Started Mar 21 02:02:50 PM PDT 24
Finished Mar 21 02:02:51 PM PDT 24
Peak memory 203632 kb
Host smart-701a6784-c32d-46d7-bc23-6bb4d8ca5e89
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609184856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.609184856
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.378621524
Short name T1047
Test name
Test status
Simulation time 37010145 ps
CPU time 0.7 seconds
Started Mar 21 02:02:53 PM PDT 24
Finished Mar 21 02:02:54 PM PDT 24
Peak memory 203352 kb
Host smart-121bfa23-aeca-4581-953e-41b12c33e385
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378621524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.378621524
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.977700808
Short name T1003
Test name
Test status
Simulation time 22842442 ps
CPU time 0.69 seconds
Started Mar 21 02:02:53 PM PDT 24
Finished Mar 21 02:02:54 PM PDT 24
Peak memory 203616 kb
Host smart-2165bcf2-e5ec-463d-be91-340d592b2325
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977700808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.977700808
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.2046616001
Short name T999
Test name
Test status
Simulation time 68744925 ps
CPU time 0.82 seconds
Started Mar 21 02:02:55 PM PDT 24
Finished Mar 21 02:02:56 PM PDT 24
Peak memory 203324 kb
Host smart-467f89d4-4d7b-4832-9df0-e7c06e377c86
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046616001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.
2046616001
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.3625196919
Short name T1016
Test name
Test status
Simulation time 17154064 ps
CPU time 0.74 seconds
Started Mar 21 02:02:49 PM PDT 24
Finished Mar 21 02:02:50 PM PDT 24
Peak memory 203564 kb
Host smart-ca3c3148-7dd4-411d-af4d-4742e189eeb2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625196919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.
3625196919
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.952333076
Short name T1103
Test name
Test status
Simulation time 14213465 ps
CPU time 0.74 seconds
Started Mar 21 02:02:52 PM PDT 24
Finished Mar 21 02:02:53 PM PDT 24
Peak memory 203320 kb
Host smart-9b09da3c-fc16-422a-8658-f3b937e73f71
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952333076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.952333076
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.3449380555
Short name T1082
Test name
Test status
Simulation time 32623907 ps
CPU time 0.74 seconds
Started Mar 21 02:02:55 PM PDT 24
Finished Mar 21 02:02:57 PM PDT 24
Peak memory 203292 kb
Host smart-8e6e7cf1-4a50-4416-a566-5e89199175f9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449380555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
3449380555
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.3332229587
Short name T1041
Test name
Test status
Simulation time 855315919 ps
CPU time 15.57 seconds
Started Mar 21 02:02:47 PM PDT 24
Finished Mar 21 02:03:03 PM PDT 24
Peak memory 215088 kb
Host smart-b1e1e432-fc48-42df-9b66-edd271337349
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332229587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_aliasing.3332229587
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.329036738
Short name T1081
Test name
Test status
Simulation time 1680863371 ps
CPU time 32.41 seconds
Started Mar 21 02:02:44 PM PDT 24
Finished Mar 21 02:03:17 PM PDT 24
Peak memory 206932 kb
Host smart-5fd609fd-620f-4717-b0a8-233a89455e32
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329036738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr
_bit_bash.329036738
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.1454354734
Short name T1094
Test name
Test status
Simulation time 82241537 ps
CPU time 1.73 seconds
Started Mar 21 02:02:47 PM PDT 24
Finished Mar 21 02:02:49 PM PDT 24
Peak memory 215272 kb
Host smart-ea20b035-9c7c-472b-9c32-4d1387a4bc3d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454354734 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.1454354734
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.658461659
Short name T133
Test name
Test status
Simulation time 142577043 ps
CPU time 2.79 seconds
Started Mar 21 02:02:42 PM PDT 24
Finished Mar 21 02:02:46 PM PDT 24
Peak memory 207016 kb
Host smart-fd8fa13d-6a92-47a2-bc66-02adf883cdd0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658461659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.658461659
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.1323988820
Short name T1031
Test name
Test status
Simulation time 44004563 ps
CPU time 0.72 seconds
Started Mar 21 02:02:43 PM PDT 24
Finished Mar 21 02:02:45 PM PDT 24
Peak memory 203240 kb
Host smart-9c707125-42f0-479b-b096-909927dc7d21
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323988820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.1
323988820
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.2922198782
Short name T1070
Test name
Test status
Simulation time 22618727 ps
CPU time 1.78 seconds
Started Mar 21 02:02:44 PM PDT 24
Finished Mar 21 02:02:46 PM PDT 24
Peak memory 215056 kb
Host smart-531ddbd5-b59a-4258-a776-6a067dc36eb1
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922198782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi
_device_mem_partial_access.2922198782
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.3137881372
Short name T997
Test name
Test status
Simulation time 17966538 ps
CPU time 0.68 seconds
Started Mar 21 02:02:43 PM PDT 24
Finished Mar 21 02:02:44 PM PDT 24
Peak memory 203600 kb
Host smart-ffe529ae-2b93-4b19-ad8b-6cd7c0430104
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137881372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_me
m_walk.3137881372
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.3609972032
Short name T1055
Test name
Test status
Simulation time 66932233 ps
CPU time 1.78 seconds
Started Mar 21 02:02:45 PM PDT 24
Finished Mar 21 02:02:48 PM PDT 24
Peak memory 215188 kb
Host smart-07990188-c014-4efe-bc05-d6b566083303
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609972032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.s
pi_device_same_csr_outstanding.3609972032
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.2078651135
Short name T118
Test name
Test status
Simulation time 116707913 ps
CPU time 3.34 seconds
Started Mar 21 02:02:45 PM PDT 24
Finished Mar 21 02:02:49 PM PDT 24
Peak memory 215352 kb
Host smart-800faa20-1022-45a3-8e89-7138ccfc4623
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078651135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.2
078651135
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.2402180752
Short name T1025
Test name
Test status
Simulation time 31315263 ps
CPU time 0.68 seconds
Started Mar 21 02:02:51 PM PDT 24
Finished Mar 21 02:02:52 PM PDT 24
Peak memory 203340 kb
Host smart-a6d6c851-f592-4601-9d36-4c339ff0fd7c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402180752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.
2402180752
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.1729117451
Short name T1020
Test name
Test status
Simulation time 38999414 ps
CPU time 0.74 seconds
Started Mar 21 02:02:52 PM PDT 24
Finished Mar 21 02:02:53 PM PDT 24
Peak memory 203644 kb
Host smart-f1e10a0a-17e4-4d98-84cc-ea8734d3b3c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729117451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.
1729117451
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.2146456998
Short name T1048
Test name
Test status
Simulation time 14405323 ps
CPU time 0.74 seconds
Started Mar 21 02:02:48 PM PDT 24
Finished Mar 21 02:02:49 PM PDT 24
Peak memory 203288 kb
Host smart-77d8534c-d0e9-442e-9f74-cee1aa875724
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146456998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.
2146456998
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.1771361476
Short name T995
Test name
Test status
Simulation time 16667677 ps
CPU time 0.69 seconds
Started Mar 21 02:02:51 PM PDT 24
Finished Mar 21 02:02:52 PM PDT 24
Peak memory 203288 kb
Host smart-5c00edcc-9d3b-447e-905e-8a08d107f633
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771361476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.
1771361476
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.2675019637
Short name T1099
Test name
Test status
Simulation time 13987091 ps
CPU time 0.79 seconds
Started Mar 21 02:02:55 PM PDT 24
Finished Mar 21 02:02:57 PM PDT 24
Peak memory 203288 kb
Host smart-a2e0791f-3eee-489e-9f91-57cdf2a250e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675019637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
2675019637
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.1267976253
Short name T1044
Test name
Test status
Simulation time 14545858 ps
CPU time 0.72 seconds
Started Mar 21 02:02:50 PM PDT 24
Finished Mar 21 02:02:52 PM PDT 24
Peak memory 203236 kb
Host smart-50f1e050-df44-42af-bc40-dd6cf4ba451e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267976253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.
1267976253
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.2073823057
Short name T1011
Test name
Test status
Simulation time 37836469 ps
CPU time 0.68 seconds
Started Mar 21 02:02:48 PM PDT 24
Finished Mar 21 02:02:49 PM PDT 24
Peak memory 203428 kb
Host smart-01753236-1a56-440a-892f-cb82bb689d8b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073823057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.
2073823057
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.3161223532
Short name T1046
Test name
Test status
Simulation time 13499819 ps
CPU time 0.68 seconds
Started Mar 21 02:02:49 PM PDT 24
Finished Mar 21 02:02:50 PM PDT 24
Peak memory 203288 kb
Host smart-f6b9c135-a283-421b-83c6-05127bd7614b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161223532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.
3161223532
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.1818680907
Short name T1056
Test name
Test status
Simulation time 43455742 ps
CPU time 0.69 seconds
Started Mar 21 02:02:50 PM PDT 24
Finished Mar 21 02:02:51 PM PDT 24
Peak memory 203264 kb
Host smart-317354ae-4c7c-4861-802b-50df6604d389
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818680907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.
1818680907
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.2709264163
Short name T1043
Test name
Test status
Simulation time 25773583 ps
CPU time 0.73 seconds
Started Mar 21 02:02:52 PM PDT 24
Finished Mar 21 02:02:53 PM PDT 24
Peak memory 203660 kb
Host smart-44f75b04-4fae-4784-a09f-e0f3004b6f0e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709264163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.
2709264163
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.45522749
Short name T1089
Test name
Test status
Simulation time 2075814133 ps
CPU time 21.54 seconds
Started Mar 21 02:02:47 PM PDT 24
Finished Mar 21 02:03:08 PM PDT 24
Peak memory 215188 kb
Host smart-6dd1bacd-412f-495b-863f-a435ff5c7e68
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45522749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_
aliasing.45522749
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.3907937407
Short name T1026
Test name
Test status
Simulation time 187224154 ps
CPU time 11.99 seconds
Started Mar 21 02:02:48 PM PDT 24
Finished Mar 21 02:03:00 PM PDT 24
Peak memory 206988 kb
Host smart-a12648c0-fb4f-4720-908d-d5d3d6e3c965
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907937407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_bit_bash.3907937407
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.221904264
Short name T97
Test name
Test status
Simulation time 177399571 ps
CPU time 1.25 seconds
Started Mar 21 02:02:42 PM PDT 24
Finished Mar 21 02:02:43 PM PDT 24
Peak memory 216128 kb
Host smart-3eda4e66-f540-4883-9607-49d293e2967c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221904264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr
_hw_reset.221904264
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.2075679141
Short name T1032
Test name
Test status
Simulation time 133433312 ps
CPU time 2.81 seconds
Started Mar 21 02:02:47 PM PDT 24
Finished Mar 21 02:02:50 PM PDT 24
Peak memory 216128 kb
Host smart-3e41c006-d4d9-4465-8e15-4c186447691d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075679141 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.2075679141
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.2014907428
Short name T1097
Test name
Test status
Simulation time 88613812 ps
CPU time 2.13 seconds
Started Mar 21 02:02:46 PM PDT 24
Finished Mar 21 02:02:48 PM PDT 24
Peak memory 206864 kb
Host smart-6f06b49d-8034-42b4-b909-29e9a3b67363
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014907428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.2
014907428
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.4157986951
Short name T1001
Test name
Test status
Simulation time 34120778 ps
CPU time 0.74 seconds
Started Mar 21 02:02:45 PM PDT 24
Finished Mar 21 02:02:46 PM PDT 24
Peak memory 203332 kb
Host smart-b18f5e96-2bcd-4538-9cc6-96b817c30abe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157986951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.4
157986951
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.4216405745
Short name T1102
Test name
Test status
Simulation time 36752405 ps
CPU time 1.32 seconds
Started Mar 21 02:02:47 PM PDT 24
Finished Mar 21 02:02:49 PM PDT 24
Peak memory 215176 kb
Host smart-397024ab-27f4-4639-9915-051e51be5b82
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216405745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi
_device_mem_partial_access.4216405745
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.1636732916
Short name T1010
Test name
Test status
Simulation time 14196188 ps
CPU time 0.69 seconds
Started Mar 21 02:02:45 PM PDT 24
Finished Mar 21 02:02:46 PM PDT 24
Peak memory 203228 kb
Host smart-65beae54-32fb-4508-9965-19c347801918
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636732916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.1636732916
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.3972507328
Short name T1053
Test name
Test status
Simulation time 71757279 ps
CPU time 1.72 seconds
Started Mar 21 02:02:54 PM PDT 24
Finished Mar 21 02:02:55 PM PDT 24
Peak memory 215092 kb
Host smart-531ae9e1-9e5b-47ad-94c5-edf83ea09214
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972507328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.s
pi_device_same_csr_outstanding.3972507328
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.1334102943
Short name T173
Test name
Test status
Simulation time 65680534 ps
CPU time 2.02 seconds
Started Mar 21 02:02:45 PM PDT 24
Finished Mar 21 02:02:47 PM PDT 24
Peak memory 215256 kb
Host smart-83421eb6-8cfe-4bd3-897a-d4fef8a0dbee
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334102943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.1
334102943
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.146297816
Short name T1091
Test name
Test status
Simulation time 525432934 ps
CPU time 15.19 seconds
Started Mar 21 02:02:47 PM PDT 24
Finished Mar 21 02:03:02 PM PDT 24
Peak memory 215120 kb
Host smart-5596834c-b5a8-4986-895a-6f134ab432ab
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146297816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_
tl_intg_err.146297816
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.1797974049
Short name T996
Test name
Test status
Simulation time 13251311 ps
CPU time 0.76 seconds
Started Mar 21 02:02:55 PM PDT 24
Finished Mar 21 02:02:56 PM PDT 24
Peak memory 203224 kb
Host smart-6612398c-0524-491c-ad42-9a763c7fe23f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797974049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.
1797974049
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.550784636
Short name T998
Test name
Test status
Simulation time 47427247 ps
CPU time 0.71 seconds
Started Mar 21 02:02:54 PM PDT 24
Finished Mar 21 02:02:56 PM PDT 24
Peak memory 203600 kb
Host smart-212235b3-ef2d-4f6f-97ad-ff69d590cf60
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550784636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.550784636
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.3158503744
Short name T1023
Test name
Test status
Simulation time 34779731 ps
CPU time 0.67 seconds
Started Mar 21 02:02:50 PM PDT 24
Finished Mar 21 02:02:51 PM PDT 24
Peak memory 203284 kb
Host smart-1b3d5bfe-56ea-44f1-ad3e-412730831307
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158503744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.
3158503744
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.124221350
Short name T1014
Test name
Test status
Simulation time 11593197 ps
CPU time 0.71 seconds
Started Mar 21 02:02:51 PM PDT 24
Finished Mar 21 02:02:52 PM PDT 24
Peak memory 203632 kb
Host smart-3f535ebb-81eb-4319-86b3-bfdcb815885b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124221350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.124221350
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.601525465
Short name T1073
Test name
Test status
Simulation time 11563595 ps
CPU time 0.72 seconds
Started Mar 21 02:02:51 PM PDT 24
Finished Mar 21 02:02:52 PM PDT 24
Peak memory 203288 kb
Host smart-e703def2-f51c-4be9-a112-63b19769cf91
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601525465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.601525465
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.4060233081
Short name T1036
Test name
Test status
Simulation time 13597918 ps
CPU time 0.68 seconds
Started Mar 21 02:02:48 PM PDT 24
Finished Mar 21 02:02:49 PM PDT 24
Peak memory 203300 kb
Host smart-5ffaee1b-2289-4b09-a156-18523e8bf199
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060233081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.
4060233081
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.193129394
Short name T1074
Test name
Test status
Simulation time 50067515 ps
CPU time 0.71 seconds
Started Mar 21 02:02:51 PM PDT 24
Finished Mar 21 02:02:52 PM PDT 24
Peak memory 203328 kb
Host smart-0f333f03-25e1-4884-8b8b-f888f8b44815
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193129394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.193129394
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.3014889834
Short name T1022
Test name
Test status
Simulation time 70110237 ps
CPU time 0.76 seconds
Started Mar 21 02:02:52 PM PDT 24
Finished Mar 21 02:02:53 PM PDT 24
Peak memory 203320 kb
Host smart-9e5e5004-4b68-4a61-96e6-9023935fb30e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014889834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.
3014889834
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.3812117893
Short name T1018
Test name
Test status
Simulation time 46204621 ps
CPU time 0.69 seconds
Started Mar 21 02:02:49 PM PDT 24
Finished Mar 21 02:02:51 PM PDT 24
Peak memory 203316 kb
Host smart-acec2bc3-3ab1-4e49-ba5a-d1ae710a530e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812117893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.
3812117893
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.575582898
Short name T1027
Test name
Test status
Simulation time 53142827 ps
CPU time 0.75 seconds
Started Mar 21 02:02:52 PM PDT 24
Finished Mar 21 02:02:53 PM PDT 24
Peak memory 203624 kb
Host smart-029b586a-d543-484d-a510-8aa3d3633882
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575582898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.575582898
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.1141101875
Short name T121
Test name
Test status
Simulation time 129813309 ps
CPU time 3.71 seconds
Started Mar 21 02:02:47 PM PDT 24
Finished Mar 21 02:02:51 PM PDT 24
Peak memory 216964 kb
Host smart-701ad13a-88f1-425d-9225-9a617561511e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141101875 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.1141101875
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.2554240784
Short name T126
Test name
Test status
Simulation time 328188007 ps
CPU time 2.9 seconds
Started Mar 21 02:02:50 PM PDT 24
Finished Mar 21 02:02:54 PM PDT 24
Peak memory 206876 kb
Host smart-943984f2-5046-4974-bfdd-9a6a2984eac1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554240784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.2
554240784
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.4034883567
Short name T1060
Test name
Test status
Simulation time 53150024 ps
CPU time 0.77 seconds
Started Mar 21 02:02:48 PM PDT 24
Finished Mar 21 02:02:49 PM PDT 24
Peak memory 203612 kb
Host smart-55c1a786-3927-47ed-a5c5-9c915106c798
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034883567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.4
034883567
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.1622551961
Short name T146
Test name
Test status
Simulation time 317696570 ps
CPU time 1.97 seconds
Started Mar 21 02:02:50 PM PDT 24
Finished Mar 21 02:02:53 PM PDT 24
Peak memory 215148 kb
Host smart-4c225fb0-2b35-418f-b29c-91e777166a00
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622551961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.s
pi_device_same_csr_outstanding.1622551961
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.2756920059
Short name T185
Test name
Test status
Simulation time 283787416 ps
CPU time 4.23 seconds
Started Mar 21 02:02:48 PM PDT 24
Finished Mar 21 02:02:52 PM PDT 24
Peak memory 215284 kb
Host smart-18698bf3-e053-4dce-8fb7-c8d7abfeef5c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756920059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.2
756920059
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.2524910499
Short name T1092
Test name
Test status
Simulation time 1485854818 ps
CPU time 7.59 seconds
Started Mar 21 02:02:47 PM PDT 24
Finished Mar 21 02:02:55 PM PDT 24
Peak memory 215556 kb
Host smart-9e86f22a-5cc0-428c-aa21-3369833273f2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524910499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.2524910499
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.4262903098
Short name T122
Test name
Test status
Simulation time 58218742 ps
CPU time 1.7 seconds
Started Mar 21 02:02:49 PM PDT 24
Finished Mar 21 02:02:51 PM PDT 24
Peak memory 215228 kb
Host smart-49371139-ec59-46b5-b2fb-035656c66fd9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262903098 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.4262903098
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.3099521965
Short name T1093
Test name
Test status
Simulation time 37884999 ps
CPU time 1.21 seconds
Started Mar 21 02:02:50 PM PDT 24
Finished Mar 21 02:02:52 PM PDT 24
Peak memory 206888 kb
Host smart-fd2993f1-94ac-43b5-b82a-69ebf2a94c3a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099521965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.3
099521965
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.3396490726
Short name T1029
Test name
Test status
Simulation time 166409397 ps
CPU time 0.69 seconds
Started Mar 21 02:02:50 PM PDT 24
Finished Mar 21 02:02:51 PM PDT 24
Peak memory 203288 kb
Host smart-3d5b711e-7d19-455d-bda0-04eb79a3a90f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396490726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.3
396490726
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.798016442
Short name T1028
Test name
Test status
Simulation time 1474454468 ps
CPU time 3.24 seconds
Started Mar 21 02:02:42 PM PDT 24
Finished Mar 21 02:02:45 PM PDT 24
Peak memory 215132 kb
Host smart-b5c71d03-15e4-413e-bb3d-d0095de5b711
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798016442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sp
i_device_same_csr_outstanding.798016442
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.1316510328
Short name T1049
Test name
Test status
Simulation time 138140284 ps
CPU time 4.57 seconds
Started Mar 21 02:02:47 PM PDT 24
Finished Mar 21 02:02:52 PM PDT 24
Peak memory 215224 kb
Host smart-3f3f1bad-6956-4cd2-ab7d-5a25db205590
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316510328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.1
316510328
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.2402299325
Short name T103
Test name
Test status
Simulation time 15722361183 ps
CPU time 19.21 seconds
Started Mar 21 02:02:47 PM PDT 24
Finished Mar 21 02:03:06 PM PDT 24
Peak memory 216504 kb
Host smart-b5b79a34-d9aa-43f7-be01-cc43dfb28fbf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402299325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device
_tl_intg_err.2402299325
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.577768011
Short name T102
Test name
Test status
Simulation time 163557419 ps
CPU time 2.93 seconds
Started Mar 21 02:02:41 PM PDT 24
Finished Mar 21 02:02:44 PM PDT 24
Peak memory 216532 kb
Host smart-cd11602d-7670-4ecd-b45d-2dea9fee7113
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577768011 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.577768011
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.3302438562
Short name T129
Test name
Test status
Simulation time 478554207 ps
CPU time 2 seconds
Started Mar 21 02:02:45 PM PDT 24
Finished Mar 21 02:02:47 PM PDT 24
Peak memory 215140 kb
Host smart-810fd341-4f23-40f6-9be0-dba164700e36
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302438562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.3
302438562
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.2537162760
Short name T1012
Test name
Test status
Simulation time 14944979 ps
CPU time 0.71 seconds
Started Mar 21 02:02:45 PM PDT 24
Finished Mar 21 02:02:47 PM PDT 24
Peak memory 203328 kb
Host smart-6f03ee8e-5e28-40dd-8b55-f8fd01d04754
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537162760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.2
537162760
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.4111531058
Short name T150
Test name
Test status
Simulation time 81851149 ps
CPU time 1.99 seconds
Started Mar 21 02:02:44 PM PDT 24
Finished Mar 21 02:02:46 PM PDT 24
Peak memory 215008 kb
Host smart-84b3cd98-1953-406a-964a-2d496c8c187e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111531058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.s
pi_device_same_csr_outstanding.4111531058
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.2151378327
Short name T105
Test name
Test status
Simulation time 65109860 ps
CPU time 2.39 seconds
Started Mar 21 02:02:49 PM PDT 24
Finished Mar 21 02:02:52 PM PDT 24
Peak memory 215172 kb
Host smart-d34e39c8-f0b1-4d89-8813-30f45c6ebf17
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151378327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.2
151378327
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.2497377614
Short name T1110
Test name
Test status
Simulation time 301837683 ps
CPU time 19.39 seconds
Started Mar 21 02:02:42 PM PDT 24
Finished Mar 21 02:03:02 PM PDT 24
Peak memory 215120 kb
Host smart-b74ce4f8-a0ae-4856-96eb-91f4439d80e2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497377614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device
_tl_intg_err.2497377614
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.1838474684
Short name T153
Test name
Test status
Simulation time 142750553 ps
CPU time 3.59 seconds
Started Mar 21 02:02:45 PM PDT 24
Finished Mar 21 02:02:49 PM PDT 24
Peak memory 216336 kb
Host smart-34106d36-4b01-4a73-98a2-e0a6de07eecc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838474684 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.1838474684
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.2172867545
Short name T1063
Test name
Test status
Simulation time 133784223 ps
CPU time 2.54 seconds
Started Mar 21 02:02:45 PM PDT 24
Finished Mar 21 02:02:48 PM PDT 24
Peak memory 207124 kb
Host smart-3be22e86-f860-4eca-8d61-3a0ff4c259c9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172867545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.2
172867545
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.578513392
Short name T1072
Test name
Test status
Simulation time 15160635 ps
CPU time 0.7 seconds
Started Mar 21 02:02:42 PM PDT 24
Finished Mar 21 02:02:44 PM PDT 24
Peak memory 203616 kb
Host smart-e6e0c4c1-8b8d-4902-baf5-21af3acf364d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578513392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.578513392
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.2045894617
Short name T1113
Test name
Test status
Simulation time 181783752 ps
CPU time 2.9 seconds
Started Mar 21 02:02:42 PM PDT 24
Finished Mar 21 02:02:45 PM PDT 24
Peak memory 215176 kb
Host smart-9b40fbe6-c5cd-46f5-a3a0-78923f4c99d1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045894617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.s
pi_device_same_csr_outstanding.2045894617
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.852778969
Short name T186
Test name
Test status
Simulation time 488061215 ps
CPU time 3.95 seconds
Started Mar 21 02:02:45 PM PDT 24
Finished Mar 21 02:02:49 PM PDT 24
Peak memory 215300 kb
Host smart-e71257c1-2b65-4bcb-9dfb-0909901af70b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852778969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.852778969
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.4102896033
Short name T1064
Test name
Test status
Simulation time 413400593 ps
CPU time 6.19 seconds
Started Mar 21 02:02:42 PM PDT 24
Finished Mar 21 02:02:48 PM PDT 24
Peak memory 215560 kb
Host smart-c109e9a6-d8a9-49a2-b3d7-de7cec1aef73
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102896033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device
_tl_intg_err.4102896033
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.3339995335
Short name T1111
Test name
Test status
Simulation time 308190051 ps
CPU time 4.23 seconds
Started Mar 21 02:02:44 PM PDT 24
Finished Mar 21 02:02:50 PM PDT 24
Peak memory 217772 kb
Host smart-d5c77382-2841-43fd-8817-2cbf8a6b67fc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339995335 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.3339995335
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.1230398349
Short name T1007
Test name
Test status
Simulation time 25421792 ps
CPU time 1.34 seconds
Started Mar 21 02:02:43 PM PDT 24
Finished Mar 21 02:02:45 PM PDT 24
Peak memory 206952 kb
Host smart-485af698-b9e7-4f48-8c99-3720f5860ed7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230398349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.1
230398349
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.2602919002
Short name T1019
Test name
Test status
Simulation time 69724679 ps
CPU time 0.75 seconds
Started Mar 21 02:02:44 PM PDT 24
Finished Mar 21 02:02:45 PM PDT 24
Peak memory 203700 kb
Host smart-f89e76bb-219f-4149-8dd3-f27d73898525
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602919002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.2
602919002
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.1085251142
Short name T1054
Test name
Test status
Simulation time 59139147 ps
CPU time 1.85 seconds
Started Mar 21 02:02:44 PM PDT 24
Finished Mar 21 02:02:48 PM PDT 24
Peak memory 215212 kb
Host smart-fae73ebe-61b7-415a-9bd8-8bd58a960e3c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085251142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.s
pi_device_same_csr_outstanding.1085251142
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.2754040992
Short name T192
Test name
Test status
Simulation time 1208563690 ps
CPU time 17.91 seconds
Started Mar 21 02:02:41 PM PDT 24
Finished Mar 21 02:02:59 PM PDT 24
Peak memory 215164 kb
Host smart-984b0cdc-9483-48df-98c8-41835be775bf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754040992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device
_tl_intg_err.2754040992
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.3660870375
Short name T762
Test name
Test status
Simulation time 34611253 ps
CPU time 0.74 seconds
Started Mar 21 02:23:08 PM PDT 24
Finished Mar 21 02:23:09 PM PDT 24
Peak memory 205420 kb
Host smart-30c56ad5-b75e-46d9-890e-01e64a19e33c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660870375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.3
660870375
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.1152973435
Short name T818
Test name
Test status
Simulation time 490734747 ps
CPU time 4.26 seconds
Started Mar 21 02:23:05 PM PDT 24
Finished Mar 21 02:23:10 PM PDT 24
Peak memory 238764 kb
Host smart-548b33d9-9a13-43dc-bb2f-4d8226199fab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1152973435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.1152973435
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.2862065600
Short name T986
Test name
Test status
Simulation time 245220634 ps
CPU time 0.81 seconds
Started Mar 21 02:22:59 PM PDT 24
Finished Mar 21 02:23:00 PM PDT 24
Peak memory 206600 kb
Host smart-87f3654b-38af-416a-83a3-a6b11568d57f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2862065600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.2862065600
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.3216638345
Short name T872
Test name
Test status
Simulation time 3845948962 ps
CPU time 27.42 seconds
Started Mar 21 02:23:06 PM PDT 24
Finished Mar 21 02:23:34 PM PDT 24
Peak memory 236736 kb
Host smart-9c84af12-4dc4-423e-b192-4364d4d211e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3216638345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.3216638345
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.3413589829
Short name T57
Test name
Test status
Simulation time 366632713146 ps
CPU time 282.56 seconds
Started Mar 21 02:23:06 PM PDT 24
Finished Mar 21 02:27:49 PM PDT 24
Peak memory 253040 kb
Host smart-77e67b31-e06b-41a4-b0bb-5f07858157a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3413589829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.3413589829
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.2338493477
Short name T797
Test name
Test status
Simulation time 34398858582 ps
CPU time 131.58 seconds
Started Mar 21 02:23:07 PM PDT 24
Finished Mar 21 02:25:19 PM PDT 24
Peak memory 254036 kb
Host smart-7181af37-4f45-4fdc-b82a-d8b6cd3e2ad2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338493477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle
.2338493477
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.3956327851
Short name T400
Test name
Test status
Simulation time 2226933002 ps
CPU time 19.27 seconds
Started Mar 21 02:23:14 PM PDT 24
Finished Mar 21 02:23:33 PM PDT 24
Peak memory 239512 kb
Host smart-408526f0-b13b-42c6-aa44-2cbe79e00ca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3956327851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.3956327851
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_intercept.3505278601
Short name T406
Test name
Test status
Simulation time 175466462 ps
CPU time 3.2 seconds
Started Mar 21 02:23:34 PM PDT 24
Finished Mar 21 02:23:37 PM PDT 24
Peak memory 234280 kb
Host smart-1e30d2c0-f915-4a8e-9c37-bcb69eb2b005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3505278601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.3505278601
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.1165331489
Short name T407
Test name
Test status
Simulation time 27918182627 ps
CPU time 19.75 seconds
Started Mar 21 02:23:07 PM PDT 24
Finished Mar 21 02:23:27 PM PDT 24
Peak memory 230060 kb
Host smart-18b4b818-01c0-44a2-8354-d4d9029af72d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165331489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.1165331489
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_mem_parity.2773993667
Short name T888
Test name
Test status
Simulation time 125262174 ps
CPU time 1.12 seconds
Started Mar 21 02:22:59 PM PDT 24
Finished Mar 21 02:23:00 PM PDT 24
Peak memory 216992 kb
Host smart-d4cfcd6b-045f-4291-be87-e14e1673bef6
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773993667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 0.spi_device_mem_parity.2773993667
Directory /workspace/0.spi_device_mem_parity/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.956705896
Short name T468
Test name
Test status
Simulation time 341904078 ps
CPU time 6.14 seconds
Started Mar 21 02:23:02 PM PDT 24
Finished Mar 21 02:23:08 PM PDT 24
Peak memory 224664 kb
Host smart-ef881d78-0f6a-4db2-a443-1d0736c1fda0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=956705896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.956705896
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.326160411
Short name T837
Test name
Test status
Simulation time 16605263 ps
CPU time 0.75 seconds
Started Mar 21 02:22:57 PM PDT 24
Finished Mar 21 02:22:58 PM PDT 24
Peak memory 216356 kb
Host smart-02b42c25-86bd-43f6-8429-2a8aa1fe6eef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=326160411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.326160411
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.2978960004
Short name T614
Test name
Test status
Simulation time 2613263659 ps
CPU time 4.85 seconds
Started Mar 21 02:23:10 PM PDT 24
Finished Mar 21 02:23:16 PM PDT 24
Peak memory 222008 kb
Host smart-07da4c82-4289-42e0-9268-df7a65b7987a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2978960004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.2978960004
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.3616108762
Short name T164
Test name
Test status
Simulation time 7868331128 ps
CPU time 54.45 seconds
Started Mar 21 02:23:07 PM PDT 24
Finished Mar 21 02:24:02 PM PDT 24
Peak memory 233012 kb
Host smart-b5bdf6ef-69c5-45c2-a960-be6847b60b87
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616108762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stres
s_all.3616108762
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.3323044732
Short name T819
Test name
Test status
Simulation time 19018968442 ps
CPU time 22.29 seconds
Started Mar 21 02:22:57 PM PDT 24
Finished Mar 21 02:23:20 PM PDT 24
Peak memory 216528 kb
Host smart-93ced23a-b915-4073-ac58-581b232efe4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3323044732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.3323044732
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.469423607
Short name T19
Test name
Test status
Simulation time 6466926036 ps
CPU time 11.01 seconds
Started Mar 21 02:23:00 PM PDT 24
Finished Mar 21 02:23:11 PM PDT 24
Peak memory 216532 kb
Host smart-14872213-c651-4748-8b47-d6a654769c74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=469423607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.469423607
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.246037333
Short name T825
Test name
Test status
Simulation time 85509981 ps
CPU time 2.07 seconds
Started Mar 21 02:23:00 PM PDT 24
Finished Mar 21 02:23:03 PM PDT 24
Peak memory 216684 kb
Host smart-6349a5da-fdd8-435e-b0c3-a6083e09cdd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=246037333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.246037333
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.4294934029
Short name T897
Test name
Test status
Simulation time 112677153 ps
CPU time 0.73 seconds
Started Mar 21 02:23:00 PM PDT 24
Finished Mar 21 02:23:01 PM PDT 24
Peak memory 205764 kb
Host smart-0a1c8eb1-573d-471e-b923-2ba1d4e267cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4294934029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.4294934029
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.3063303266
Short name T505
Test name
Test status
Simulation time 1318556345 ps
CPU time 11.17 seconds
Started Mar 21 02:23:07 PM PDT 24
Finished Mar 21 02:23:18 PM PDT 24
Peak memory 248532 kb
Host smart-61ed29d2-1e5d-4b18-a459-25b619e788ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063303266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.3063303266
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.3778914849
Short name T924
Test name
Test status
Simulation time 12304360 ps
CPU time 0.7 seconds
Started Mar 21 02:23:17 PM PDT 24
Finished Mar 21 02:23:18 PM PDT 24
Peak memory 205420 kb
Host smart-30c0814a-3493-4c42-9ba7-303a285a8c56
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778914849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.3
778914849
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.726678346
Short name T3
Test name
Test status
Simulation time 11534905620 ps
CPU time 10.25 seconds
Started Mar 21 02:23:14 PM PDT 24
Finished Mar 21 02:23:24 PM PDT 24
Peak memory 238500 kb
Host smart-7f704590-ee7b-4cce-85c6-aa8890af7f4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=726678346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.726678346
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.702005897
Short name T884
Test name
Test status
Simulation time 51274975 ps
CPU time 0.8 seconds
Started Mar 21 02:23:07 PM PDT 24
Finished Mar 21 02:23:08 PM PDT 24
Peak memory 206616 kb
Host smart-b6e70f24-ffe2-411d-878c-35f2d0d3b375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=702005897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.702005897
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.3468496317
Short name T299
Test name
Test status
Simulation time 35143374864 ps
CPU time 61.39 seconds
Started Mar 21 02:23:05 PM PDT 24
Finished Mar 21 02:24:07 PM PDT 24
Peak memory 239332 kb
Host smart-f4b74197-fef0-4bc5-adbb-6eb816fbc40f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3468496317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.3468496317
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.3848439794
Short name T248
Test name
Test status
Simulation time 49015621700 ps
CPU time 176.74 seconds
Started Mar 21 02:23:14 PM PDT 24
Finished Mar 21 02:26:12 PM PDT 24
Peak memory 263324 kb
Host smart-c39c3640-98a6-4096-9a47-fc971ecb06af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3848439794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.3848439794
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.1789643216
Short name T516
Test name
Test status
Simulation time 16859503310 ps
CPU time 21.84 seconds
Started Mar 21 02:23:06 PM PDT 24
Finished Mar 21 02:23:28 PM PDT 24
Peak memory 232940 kb
Host smart-88c9bf5f-a93c-4c64-ab68-e46b385c6b33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1789643216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.1789643216
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_intercept.2074844700
Short name T560
Test name
Test status
Simulation time 5558148078 ps
CPU time 3.12 seconds
Started Mar 21 02:23:12 PM PDT 24
Finished Mar 21 02:23:16 PM PDT 24
Peak memory 224712 kb
Host smart-232ffb4c-1246-42e7-b030-3cf489a3dce0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2074844700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.2074844700
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.868261983
Short name T21
Test name
Test status
Simulation time 7879841009 ps
CPU time 7.92 seconds
Started Mar 21 02:23:06 PM PDT 24
Finished Mar 21 02:23:14 PM PDT 24
Peak memory 234076 kb
Host smart-02dd54dc-528c-477c-b23c-96e6fca0d81b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868261983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.868261983
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.2323611303
Short name T859
Test name
Test status
Simulation time 2170784109 ps
CPU time 8.49 seconds
Started Mar 21 02:23:07 PM PDT 24
Finished Mar 21 02:23:16 PM PDT 24
Peak memory 234952 kb
Host smart-e3810410-d8c7-4473-bbcb-37f2118bc3da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2323611303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.2323611303
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.3852831667
Short name T765
Test name
Test status
Simulation time 419705226 ps
CPU time 7.89 seconds
Started Mar 21 02:23:07 PM PDT 24
Finished Mar 21 02:23:15 PM PDT 24
Peak memory 240400 kb
Host smart-efc542bb-c603-4c33-aa75-1779d3d333f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852831667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.3852831667
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_ram_cfg.705478966
Short name T651
Test name
Test status
Simulation time 18469351 ps
CPU time 0.8 seconds
Started Mar 21 02:23:06 PM PDT 24
Finished Mar 21 02:23:06 PM PDT 24
Peak memory 216400 kb
Host smart-5b6ffee7-8304-466d-9613-4a5e7dc119e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=705478966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_ram_cfg.705478966
Directory /workspace/1.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.2913957460
Short name T531
Test name
Test status
Simulation time 74085679 ps
CPU time 3.04 seconds
Started Mar 21 02:23:06 PM PDT 24
Finished Mar 21 02:23:09 PM PDT 24
Peak memory 218816 kb
Host smart-8946761c-e30b-4ced-bf58-0ea4bc6ec5f9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2913957460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_dire
ct.2913957460
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.4025561589
Short name T80
Test name
Test status
Simulation time 71790253 ps
CPU time 1.05 seconds
Started Mar 21 02:23:06 PM PDT 24
Finished Mar 21 02:23:07 PM PDT 24
Peak memory 235764 kb
Host smart-56afb288-95a4-405a-a7ef-4acf9763397c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025561589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.4025561589
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.4162498601
Short name T662
Test name
Test status
Simulation time 1320731230434 ps
CPU time 1143.66 seconds
Started Mar 21 02:23:12 PM PDT 24
Finished Mar 21 02:42:15 PM PDT 24
Peak memory 282200 kb
Host smart-e95a3152-eeec-485f-8905-96d941ade5c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162498601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stres
s_all.4162498601
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.1559972345
Short name T671
Test name
Test status
Simulation time 4157503213 ps
CPU time 14.58 seconds
Started Mar 21 02:23:05 PM PDT 24
Finished Mar 21 02:23:20 PM PDT 24
Peak memory 216552 kb
Host smart-12c01c77-cb64-43c7-b3f6-5375f2a9324f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1559972345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.1559972345
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.1885736097
Short name T513
Test name
Test status
Simulation time 379411747 ps
CPU time 1.58 seconds
Started Mar 21 02:23:09 PM PDT 24
Finished Mar 21 02:23:11 PM PDT 24
Peak memory 207804 kb
Host smart-66734626-6990-4b42-b525-5166ab2b1f0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1885736097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.1885736097
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.3769941403
Short name T639
Test name
Test status
Simulation time 404884391 ps
CPU time 4.64 seconds
Started Mar 21 02:23:06 PM PDT 24
Finished Mar 21 02:23:11 PM PDT 24
Peak memory 216488 kb
Host smart-6e6dbcb4-82e2-454a-af2d-f409d54dc778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3769941403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.3769941403
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.1340119303
Short name T380
Test name
Test status
Simulation time 343312270 ps
CPU time 0.99 seconds
Started Mar 21 02:23:38 PM PDT 24
Finished Mar 21 02:23:40 PM PDT 24
Peak memory 206764 kb
Host smart-58f85bfb-5233-4f47-895e-34f55604d1ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1340119303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.1340119303
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.248847849
Short name T708
Test name
Test status
Simulation time 89881163 ps
CPU time 2.56 seconds
Started Mar 21 02:23:09 PM PDT 24
Finished Mar 21 02:23:12 PM PDT 24
Peak memory 234252 kb
Host smart-d52154a5-33b6-4a6e-898c-5290cd9d780d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=248847849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.248847849
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.608992897
Short name T377
Test name
Test status
Simulation time 11687874 ps
CPU time 0.76 seconds
Started Mar 21 02:24:20 PM PDT 24
Finished Mar 21 02:24:21 PM PDT 24
Peak memory 205384 kb
Host smart-4220932a-0c3c-4dce-b6c9-600d4e38854c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608992897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.608992897
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.2524083472
Short name T482
Test name
Test status
Simulation time 464660941 ps
CPU time 2.82 seconds
Started Mar 21 02:24:04 PM PDT 24
Finished Mar 21 02:24:06 PM PDT 24
Peak memory 218768 kb
Host smart-7c9f6b09-3655-4e26-b54e-91fbb5381fe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2524083472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.2524083472
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.3060347821
Short name T642
Test name
Test status
Simulation time 88534677 ps
CPU time 0.79 seconds
Started Mar 21 02:24:04 PM PDT 24
Finished Mar 21 02:24:05 PM PDT 24
Peak memory 205556 kb
Host smart-b24e3290-3f36-4490-aa31-ddb8ea99e349
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3060347821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.3060347821
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.21939659
Short name T89
Test name
Test status
Simulation time 21774973058 ps
CPU time 49.87 seconds
Started Mar 21 02:24:02 PM PDT 24
Finished Mar 21 02:24:52 PM PDT 24
Peak memory 253360 kb
Host smart-518bc86d-82b4-48be-bb9f-10ed68c5535d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21939659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.21939659
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.4148527025
Short name T422
Test name
Test status
Simulation time 4530513687 ps
CPU time 75.27 seconds
Started Mar 21 02:24:03 PM PDT 24
Finished Mar 21 02:25:19 PM PDT 24
Peak memory 257496 kb
Host smart-56ff6b7c-3d70-48fd-8ba9-7f4c5f45c9e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4148527025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.4148527025
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.2183952969
Short name T832
Test name
Test status
Simulation time 8474426264 ps
CPU time 54.94 seconds
Started Mar 21 02:24:05 PM PDT 24
Finished Mar 21 02:25:00 PM PDT 24
Peak memory 239852 kb
Host smart-6f6c83de-4241-4539-800b-afc96690f6b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2183952969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idl
e.2183952969
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.2717091089
Short name T247
Test name
Test status
Simulation time 3947393640 ps
CPU time 24.48 seconds
Started Mar 21 02:24:05 PM PDT 24
Finished Mar 21 02:24:29 PM PDT 24
Peak memory 235892 kb
Host smart-b65f0f1e-55c1-4810-b32f-4df62e0b86a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717091089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.2717091089
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_intercept.786686324
Short name T212
Test name
Test status
Simulation time 592078845 ps
CPU time 5.12 seconds
Started Mar 21 02:24:05 PM PDT 24
Finished Mar 21 02:24:10 PM PDT 24
Peak memory 219336 kb
Host smart-7d68a808-b733-4c0e-8288-d251984bbce2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786686324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.786686324
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.3015197042
Short name T249
Test name
Test status
Simulation time 11814954776 ps
CPU time 21.44 seconds
Started Mar 21 02:24:04 PM PDT 24
Finished Mar 21 02:24:25 PM PDT 24
Peak memory 232916 kb
Host smart-3d02adb8-88b4-48f2-983c-a5afa0d7a617
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3015197042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.3015197042
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_mem_parity.2692873351
Short name T763
Test name
Test status
Simulation time 16852366 ps
CPU time 1.03 seconds
Started Mar 21 02:24:05 PM PDT 24
Finished Mar 21 02:24:06 PM PDT 24
Peak memory 217052 kb
Host smart-95d1bc01-2db8-4717-af0e-b6497236a4e5
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692873351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 10.spi_device_mem_parity.2692873351
Directory /workspace/10.spi_device_mem_parity/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.3142138327
Short name T806
Test name
Test status
Simulation time 1941558442 ps
CPU time 7.76 seconds
Started Mar 21 02:24:05 PM PDT 24
Finished Mar 21 02:24:13 PM PDT 24
Peak memory 232896 kb
Host smart-d1b58e4f-5398-4c98-b398-b63ac8088969
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3142138327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swa
p.3142138327
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.3531703376
Short name T876
Test name
Test status
Simulation time 9800642727 ps
CPU time 15.74 seconds
Started Mar 21 02:24:04 PM PDT 24
Finished Mar 21 02:24:20 PM PDT 24
Peak memory 220796 kb
Host smart-20e73eab-f36e-4d39-9278-85287c61b671
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531703376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.3531703376
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.1362338018
Short name T743
Test name
Test status
Simulation time 509275412 ps
CPU time 4.08 seconds
Started Mar 21 02:24:03 PM PDT 24
Finished Mar 21 02:24:07 PM PDT 24
Peak memory 220348 kb
Host smart-9fa1006d-10b5-439a-b9f4-466b58131b0a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1362338018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dir
ect.1362338018
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.2530530507
Short name T69
Test name
Test status
Simulation time 88022598 ps
CPU time 0.95 seconds
Started Mar 21 02:24:04 PM PDT 24
Finished Mar 21 02:24:05 PM PDT 24
Peak memory 206988 kb
Host smart-53cf15ca-2724-4339-9056-523e52b2ea06
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530530507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stre
ss_all.2530530507
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.3539818058
Short name T885
Test name
Test status
Simulation time 5243918148 ps
CPU time 14.73 seconds
Started Mar 21 02:24:03 PM PDT 24
Finished Mar 21 02:24:18 PM PDT 24
Peak memory 216552 kb
Host smart-9fafb3d9-0d91-4654-a721-1632f26c86fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539818058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.3539818058
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.326540507
Short name T877
Test name
Test status
Simulation time 500715976 ps
CPU time 1.33 seconds
Started Mar 21 02:24:05 PM PDT 24
Finished Mar 21 02:24:06 PM PDT 24
Peak memory 216244 kb
Host smart-470cb154-e6bb-4f82-bd85-73bb2e51a65c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=326540507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.326540507
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.1404908034
Short name T429
Test name
Test status
Simulation time 89091497 ps
CPU time 1.05 seconds
Started Mar 21 02:24:05 PM PDT 24
Finished Mar 21 02:24:06 PM PDT 24
Peak memory 206800 kb
Host smart-7a794983-8a1c-42c5-bd41-5bbebefbbeb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404908034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.1404908034
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.1805621424
Short name T973
Test name
Test status
Simulation time 1208483514 ps
CPU time 6.09 seconds
Started Mar 21 02:24:05 PM PDT 24
Finished Mar 21 02:24:11 PM PDT 24
Peak memory 241040 kb
Host smart-de0bc227-a12f-4b98-a845-36c35e6c03f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1805621424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.1805621424
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.4043938760
Short name T926
Test name
Test status
Simulation time 40302880 ps
CPU time 0.74 seconds
Started Mar 21 02:24:18 PM PDT 24
Finished Mar 21 02:24:19 PM PDT 24
Peak memory 205748 kb
Host smart-5188cd15-39c8-4487-a259-a5637f3131ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043938760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.
4043938760
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.4262834774
Short name T720
Test name
Test status
Simulation time 941370749 ps
CPU time 5.14 seconds
Started Mar 21 02:24:15 PM PDT 24
Finished Mar 21 02:24:20 PM PDT 24
Peak memory 218544 kb
Host smart-2819711f-4d36-4699-beb0-5739b8849fb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4262834774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.4262834774
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.999064638
Short name T961
Test name
Test status
Simulation time 63329211 ps
CPU time 0.77 seconds
Started Mar 21 02:24:17 PM PDT 24
Finished Mar 21 02:24:18 PM PDT 24
Peak memory 205588 kb
Host smart-5701825e-cb34-4eb0-b8ec-c0ff21422ac8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=999064638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.999064638
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.1708891994
Short name T172
Test name
Test status
Simulation time 106041210676 ps
CPU time 179.34 seconds
Started Mar 21 02:24:19 PM PDT 24
Finished Mar 21 02:27:18 PM PDT 24
Peak memory 237916 kb
Host smart-eb9fc27a-ee62-4759-bdc9-507333e09b17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1708891994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.1708891994
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.2136352059
Short name T903
Test name
Test status
Simulation time 3092011796 ps
CPU time 44.92 seconds
Started Mar 21 02:24:17 PM PDT 24
Finished Mar 21 02:25:02 PM PDT 24
Peak memory 237688 kb
Host smart-5275befe-8644-4f68-8fff-92ff879f9e2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2136352059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idl
e.2136352059
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.2627272183
Short name T313
Test name
Test status
Simulation time 1375649781 ps
CPU time 10.56 seconds
Started Mar 21 02:24:17 PM PDT 24
Finished Mar 21 02:24:27 PM PDT 24
Peak memory 247192 kb
Host smart-7ee0b5ec-c586-40ca-b608-52f6cc2603e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2627272183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.2627272183
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_intercept.3092588917
Short name T615
Test name
Test status
Simulation time 16694714693 ps
CPU time 14.45 seconds
Started Mar 21 02:24:16 PM PDT 24
Finished Mar 21 02:24:31 PM PDT 24
Peak memory 219304 kb
Host smart-fcd2de0d-088b-4916-97ff-424c6645fd44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3092588917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.3092588917
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.95077332
Short name T8
Test name
Test status
Simulation time 3524613341 ps
CPU time 6.19 seconds
Started Mar 21 02:24:15 PM PDT 24
Finished Mar 21 02:24:22 PM PDT 24
Peak memory 236432 kb
Host smart-44da4b99-18d9-4b56-9472-5185d7371691
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95077332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.95077332
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_mem_parity.3470892275
Short name T26
Test name
Test status
Simulation time 16912450 ps
CPU time 1.04 seconds
Started Mar 21 02:24:17 PM PDT 24
Finished Mar 21 02:24:18 PM PDT 24
Peak memory 216984 kb
Host smart-9849be6a-42b4-43ea-b5c2-43dfd0e6da31
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470892275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 11.spi_device_mem_parity.3470892275
Directory /workspace/11.spi_device_mem_parity/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.4268898871
Short name T980
Test name
Test status
Simulation time 24438409147 ps
CPU time 14.35 seconds
Started Mar 21 02:24:17 PM PDT 24
Finished Mar 21 02:24:32 PM PDT 24
Peak memory 232880 kb
Host smart-432dda83-ac9c-44eb-b086-e18f7bdee232
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4268898871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swa
p.4268898871
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.2135519257
Short name T578
Test name
Test status
Simulation time 1315413326 ps
CPU time 12.41 seconds
Started Mar 21 02:24:18 PM PDT 24
Finished Mar 21 02:24:31 PM PDT 24
Peak memory 239224 kb
Host smart-e4047197-5577-467e-8f34-d352bb3e1acb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135519257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.2135519257
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_ram_cfg.3352752110
Short name T538
Test name
Test status
Simulation time 38222780 ps
CPU time 0.76 seconds
Started Mar 21 02:24:21 PM PDT 24
Finished Mar 21 02:24:22 PM PDT 24
Peak memory 216388 kb
Host smart-c376986e-82a8-4ec7-b34f-e1c44889df8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3352752110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_ram_cfg.3352752110
Directory /workspace/11.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.2541984593
Short name T989
Test name
Test status
Simulation time 602000216 ps
CPU time 5.13 seconds
Started Mar 21 02:24:21 PM PDT 24
Finished Mar 21 02:24:26 PM PDT 24
Peak memory 223064 kb
Host smart-8374c859-6215-404f-a31d-465ab8d5b558
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2541984593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dir
ect.2541984593
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.2388601276
Short name T525
Test name
Test status
Simulation time 9212023693 ps
CPU time 36.87 seconds
Started Mar 21 02:24:16 PM PDT 24
Finished Mar 21 02:24:53 PM PDT 24
Peak memory 241184 kb
Host smart-346add22-1dc0-4087-abae-47a789a3c68d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388601276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stre
ss_all.2388601276
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.3742501439
Short name T444
Test name
Test status
Simulation time 7629844981 ps
CPU time 14.87 seconds
Started Mar 21 02:24:17 PM PDT 24
Finished Mar 21 02:24:32 PM PDT 24
Peak memory 216528 kb
Host smart-f35bfd23-b56c-449a-93d9-e8d0f2ef9525
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742501439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.3742501439
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.1201966855
Short name T388
Test name
Test status
Simulation time 5565481114 ps
CPU time 9.04 seconds
Started Mar 21 02:24:19 PM PDT 24
Finished Mar 21 02:24:28 PM PDT 24
Peak memory 216620 kb
Host smart-0cba6a04-7f76-42fd-b1ae-423fd6216f54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201966855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.1201966855
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.1129080119
Short name T705
Test name
Test status
Simulation time 30827297 ps
CPU time 0.78 seconds
Started Mar 21 02:24:18 PM PDT 24
Finished Mar 21 02:24:19 PM PDT 24
Peak memory 206560 kb
Host smart-4bd6783a-7a7a-4da6-bd70-8e3c474e641c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1129080119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.1129080119
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.3007380242
Short name T1
Test name
Test status
Simulation time 56089702 ps
CPU time 0.73 seconds
Started Mar 21 02:24:21 PM PDT 24
Finished Mar 21 02:24:22 PM PDT 24
Peak memory 205756 kb
Host smart-26555967-3b4d-4409-a53c-69506700889a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3007380242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.3007380242
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.2908144794
Short name T612
Test name
Test status
Simulation time 2472912011 ps
CPU time 10.68 seconds
Started Mar 21 02:24:16 PM PDT 24
Finished Mar 21 02:24:26 PM PDT 24
Peak memory 239424 kb
Host smart-a184f45d-0710-48cc-87c0-35f99c1cf45d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2908144794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.2908144794
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.2137518018
Short name T745
Test name
Test status
Simulation time 14372996 ps
CPU time 0.72 seconds
Started Mar 21 02:24:18 PM PDT 24
Finished Mar 21 02:24:19 PM PDT 24
Peak memory 205756 kb
Host smart-0bc3ea19-25f5-47fe-81ff-d6678a0c187a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137518018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.
2137518018
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.2120509692
Short name T532
Test name
Test status
Simulation time 63449623 ps
CPU time 2.66 seconds
Started Mar 21 02:24:19 PM PDT 24
Finished Mar 21 02:24:22 PM PDT 24
Peak memory 233836 kb
Host smart-54f0234e-83f3-4594-86a1-31aea7e21945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2120509692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.2120509692
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.193469820
Short name T667
Test name
Test status
Simulation time 22245885 ps
CPU time 0.81 seconds
Started Mar 21 02:24:15 PM PDT 24
Finished Mar 21 02:24:16 PM PDT 24
Peak memory 206544 kb
Host smart-3961d2fe-d1e6-4f3a-986b-74b24ce7af5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=193469820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.193469820
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.425135012
Short name T781
Test name
Test status
Simulation time 2026062634 ps
CPU time 11.4 seconds
Started Mar 21 02:24:17 PM PDT 24
Finished Mar 21 02:24:28 PM PDT 24
Peak memory 236176 kb
Host smart-01fd329f-e8a3-421e-8752-0aa522a2a5f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=425135012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.425135012
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.506836101
Short name T767
Test name
Test status
Simulation time 46891501360 ps
CPU time 86.53 seconds
Started Mar 21 02:24:17 PM PDT 24
Finished Mar 21 02:25:43 PM PDT 24
Peak memory 268732 kb
Host smart-39227cd5-e9c6-4bab-87fd-b70e534136d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=506836101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.506836101
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.1464823380
Short name T952
Test name
Test status
Simulation time 130329461231 ps
CPU time 362.47 seconds
Started Mar 21 02:24:19 PM PDT 24
Finished Mar 21 02:30:22 PM PDT 24
Peak memory 252544 kb
Host smart-417994eb-6718-4274-bab3-91f3c08be7ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1464823380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idl
e.1464823380
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.3830024354
Short name T411
Test name
Test status
Simulation time 16346078903 ps
CPU time 29.19 seconds
Started Mar 21 02:24:15 PM PDT 24
Finished Mar 21 02:24:44 PM PDT 24
Peak memory 221900 kb
Host smart-8077a17e-c750-476c-b0a4-1fac094426bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3830024354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.3830024354
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_intercept.1178328663
Short name T873
Test name
Test status
Simulation time 1276456449 ps
CPU time 5.34 seconds
Started Mar 21 02:24:16 PM PDT 24
Finished Mar 21 02:24:22 PM PDT 24
Peak memory 233832 kb
Host smart-f4c51b17-fc00-4657-914f-3306e07c4f63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1178328663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.1178328663
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.2781418578
Short name T371
Test name
Test status
Simulation time 16269232684 ps
CPU time 43.55 seconds
Started Mar 21 02:24:18 PM PDT 24
Finished Mar 21 02:25:02 PM PDT 24
Peak memory 223452 kb
Host smart-52e42e9c-eb26-4d3a-9d50-d5de005f6725
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2781418578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.2781418578
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_mem_parity.346806428
Short name T596
Test name
Test status
Simulation time 64659466 ps
CPU time 1.18 seconds
Started Mar 21 02:24:19 PM PDT 24
Finished Mar 21 02:24:20 PM PDT 24
Peak memory 216952 kb
Host smart-55cf70ed-c07f-4029-a3f8-e9bd3629c2d4
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346806428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.spi_device_mem_parity.346806428
Directory /workspace/12.spi_device_mem_parity/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.2161181104
Short name T906
Test name
Test status
Simulation time 16448065489 ps
CPU time 21.46 seconds
Started Mar 21 02:24:16 PM PDT 24
Finished Mar 21 02:24:38 PM PDT 24
Peak memory 218692 kb
Host smart-a31bf06c-89ca-4504-96ea-53548311b04d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161181104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swa
p.2161181104
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.299662959
Short name T250
Test name
Test status
Simulation time 482284833 ps
CPU time 6.02 seconds
Started Mar 21 02:24:16 PM PDT 24
Finished Mar 21 02:24:22 PM PDT 24
Peak memory 237572 kb
Host smart-e4983ccd-ea0e-4454-85ad-96f1611788a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=299662959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.299662959
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_ram_cfg.2321324465
Short name T438
Test name
Test status
Simulation time 36963121 ps
CPU time 0.76 seconds
Started Mar 21 02:24:18 PM PDT 24
Finished Mar 21 02:24:19 PM PDT 24
Peak memory 216372 kb
Host smart-72012cf7-3d5f-4ac4-a32a-164c58901261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2321324465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_ram_cfg.2321324465
Directory /workspace/12.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.68984502
Short name T142
Test name
Test status
Simulation time 4951910954 ps
CPU time 6.06 seconds
Started Mar 21 02:24:14 PM PDT 24
Finished Mar 21 02:24:20 PM PDT 24
Peak memory 223096 kb
Host smart-c84d09ea-7582-4c0d-8bb8-275562ea874a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=68984502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_direc
t.68984502
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.610843898
Short name T387
Test name
Test status
Simulation time 57467300 ps
CPU time 1.1 seconds
Started Mar 21 02:24:17 PM PDT 24
Finished Mar 21 02:24:19 PM PDT 24
Peak memory 207196 kb
Host smart-26ec9aeb-a313-4c7d-ab51-90937bf06f24
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610843898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stres
s_all.610843898
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.1291218514
Short name T981
Test name
Test status
Simulation time 1484268269 ps
CPU time 7.64 seconds
Started Mar 21 02:24:19 PM PDT 24
Finished Mar 21 02:24:27 PM PDT 24
Peak memory 216500 kb
Host smart-46fb4b0d-37ac-4c71-907d-b315ce932f93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291218514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.1291218514
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.3324019568
Short name T848
Test name
Test status
Simulation time 17388824945 ps
CPU time 12.92 seconds
Started Mar 21 02:24:18 PM PDT 24
Finished Mar 21 02:24:31 PM PDT 24
Peak memory 216576 kb
Host smart-ec1c8614-c923-478a-ad0e-f64556d70594
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3324019568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.3324019568
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.3135377500
Short name T325
Test name
Test status
Simulation time 834541226 ps
CPU time 1.55 seconds
Started Mar 21 02:24:17 PM PDT 24
Finished Mar 21 02:24:19 PM PDT 24
Peak memory 216536 kb
Host smart-57e807d7-9675-48b1-b3f9-b951fa415b0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3135377500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.3135377500
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.2274765334
Short name T785
Test name
Test status
Simulation time 46771657 ps
CPU time 0.8 seconds
Started Mar 21 02:24:17 PM PDT 24
Finished Mar 21 02:24:17 PM PDT 24
Peak memory 205760 kb
Host smart-d9a4fd05-438d-46ec-afb3-9430543bdd56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2274765334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.2274765334
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.2708325461
Short name T278
Test name
Test status
Simulation time 3956872723 ps
CPU time 9.39 seconds
Started Mar 21 02:24:18 PM PDT 24
Finished Mar 21 02:24:27 PM PDT 24
Peak memory 232936 kb
Host smart-80b37c66-c1c0-4b1d-a4de-c6701eae8aad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2708325461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.2708325461
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.295865166
Short name T875
Test name
Test status
Simulation time 22580906 ps
CPU time 0.71 seconds
Started Mar 21 02:24:51 PM PDT 24
Finished Mar 21 02:24:53 PM PDT 24
Peak memory 204876 kb
Host smart-f0cf6965-6ab9-4db6-a108-dab7415eeee5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295865166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.295865166
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.370411984
Short name T820
Test name
Test status
Simulation time 429654933 ps
CPU time 5.16 seconds
Started Mar 21 02:24:30 PM PDT 24
Finished Mar 21 02:24:35 PM PDT 24
Peak memory 233836 kb
Host smart-cb9ebe14-3c46-4aaa-846c-cd16976302ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=370411984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.370411984
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.3729849326
Short name T378
Test name
Test status
Simulation time 19068772 ps
CPU time 0.77 seconds
Started Mar 21 02:24:18 PM PDT 24
Finished Mar 21 02:24:19 PM PDT 24
Peak memory 205560 kb
Host smart-0b5c1005-efa0-49c1-abb9-629a4eec7d39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3729849326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.3729849326
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.3127245598
Short name T648
Test name
Test status
Simulation time 4318401449 ps
CPU time 78.45 seconds
Started Mar 21 02:24:24 PM PDT 24
Finished Mar 21 02:25:43 PM PDT 24
Peak memory 251612 kb
Host smart-bb6adb32-f854-4183-beeb-684432ebc78a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127245598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.3127245598
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.6829467
Short name T95
Test name
Test status
Simulation time 76189516464 ps
CPU time 585.01 seconds
Started Mar 21 02:24:25 PM PDT 24
Finished Mar 21 02:34:11 PM PDT 24
Peak memory 256396 kb
Host smart-982c250d-cf5a-41f3-8e18-1e68dfdd8e99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6829467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idle.6829467
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.2847357433
Short name T597
Test name
Test status
Simulation time 29406593967 ps
CPU time 32.95 seconds
Started Mar 21 02:24:32 PM PDT 24
Finished Mar 21 02:25:05 PM PDT 24
Peak memory 249368 kb
Host smart-836b68d6-0c7b-4d1c-bc75-033eb55af656
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2847357433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.2847357433
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_intercept.4010250900
Short name T809
Test name
Test status
Simulation time 10281519102 ps
CPU time 8.23 seconds
Started Mar 21 02:24:27 PM PDT 24
Finished Mar 21 02:24:36 PM PDT 24
Peak memory 219804 kb
Host smart-0067354b-ac75-4926-875b-06e73e5a63ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4010250900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.4010250900
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.1156974088
Short name T528
Test name
Test status
Simulation time 3949444989 ps
CPU time 6.17 seconds
Started Mar 21 02:24:30 PM PDT 24
Finished Mar 21 02:24:36 PM PDT 24
Peak memory 236204 kb
Host smart-38959834-114c-4e05-8c7c-1200abcba91f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1156974088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.1156974088
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_mem_parity.1812537164
Short name T729
Test name
Test status
Simulation time 22942756 ps
CPU time 1.03 seconds
Started Mar 21 02:24:15 PM PDT 24
Finished Mar 21 02:24:16 PM PDT 24
Peak memory 216924 kb
Host smart-493bc699-5abd-434a-896b-27d278fb29ea
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812537164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 13.spi_device_mem_parity.1812537164
Directory /workspace/13.spi_device_mem_parity/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.277883522
Short name T987
Test name
Test status
Simulation time 7054571991 ps
CPU time 17.56 seconds
Started Mar 21 02:24:27 PM PDT 24
Finished Mar 21 02:24:45 PM PDT 24
Peak memory 218240 kb
Host smart-ace36f71-1de9-469d-b5aa-a120a175457e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=277883522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swap
.277883522
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.2732592298
Short name T674
Test name
Test status
Simulation time 7028747880 ps
CPU time 8.24 seconds
Started Mar 21 02:24:35 PM PDT 24
Finished Mar 21 02:24:43 PM PDT 24
Peak memory 233848 kb
Host smart-e79deb2b-c02b-446a-bcdb-2fc51fa69bff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2732592298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.2732592298
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_ram_cfg.4242174706
Short name T958
Test name
Test status
Simulation time 20210445 ps
CPU time 0.75 seconds
Started Mar 21 02:24:19 PM PDT 24
Finished Mar 21 02:24:19 PM PDT 24
Peak memory 216364 kb
Host smart-c918f770-637f-4a29-aed5-b70b22b320de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4242174706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_ram_cfg.4242174706
Directory /workspace/13.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.3695009940
Short name T736
Test name
Test status
Simulation time 91520431 ps
CPU time 3.68 seconds
Started Mar 21 02:24:25 PM PDT 24
Finished Mar 21 02:24:28 PM PDT 24
Peak memory 222952 kb
Host smart-c04d46b4-9b05-4e2d-aee1-f1302115479d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3695009940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dir
ect.3695009940
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.3051653322
Short name T967
Test name
Test status
Simulation time 3387048643 ps
CPU time 43.03 seconds
Started Mar 21 02:24:25 PM PDT 24
Finished Mar 21 02:25:08 PM PDT 24
Peak memory 248392 kb
Host smart-0e19b38a-8f30-400c-aed6-b2682e059d73
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051653322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stre
ss_all.3051653322
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.489488910
Short name T669
Test name
Test status
Simulation time 27161676463 ps
CPU time 43.54 seconds
Started Mar 21 02:24:25 PM PDT 24
Finished Mar 21 02:25:09 PM PDT 24
Peak memory 216636 kb
Host smart-1c3eea46-4243-4b43-9659-caca1c0c861a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=489488910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.489488910
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.2096248362
Short name T787
Test name
Test status
Simulation time 500274417 ps
CPU time 4.48 seconds
Started Mar 21 02:24:32 PM PDT 24
Finished Mar 21 02:24:36 PM PDT 24
Peak memory 216496 kb
Host smart-02717b54-c42c-467c-a3da-c9a416cf2a69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096248362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.2096248362
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.807944252
Short name T959
Test name
Test status
Simulation time 29892471 ps
CPU time 1.43 seconds
Started Mar 21 02:24:28 PM PDT 24
Finished Mar 21 02:24:30 PM PDT 24
Peak memory 216476 kb
Host smart-2e90444c-bf17-4ec0-872a-6a5cfdd0ad50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807944252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.807944252
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.3816055200
Short name T946
Test name
Test status
Simulation time 222521695 ps
CPU time 1.29 seconds
Started Mar 21 02:24:26 PM PDT 24
Finished Mar 21 02:24:27 PM PDT 24
Peak memory 206760 kb
Host smart-a1041114-7cac-4bf4-89dc-91dc39b6ff02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3816055200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.3816055200
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.1288447344
Short name T654
Test name
Test status
Simulation time 2929023247 ps
CPU time 12.92 seconds
Started Mar 21 02:24:27 PM PDT 24
Finished Mar 21 02:24:40 PM PDT 24
Peak memory 227148 kb
Host smart-139bf1d1-e300-408d-8d64-2f1cf820636d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1288447344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.1288447344
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.2522219234
Short name T638
Test name
Test status
Simulation time 42578170 ps
CPU time 0.72 seconds
Started Mar 21 02:24:26 PM PDT 24
Finished Mar 21 02:24:27 PM PDT 24
Peak memory 205756 kb
Host smart-4e03db77-74a2-4a44-8e75-fd5258404da1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522219234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.
2522219234
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.3905662295
Short name T539
Test name
Test status
Simulation time 1738924297 ps
CPU time 6.9 seconds
Started Mar 21 02:24:28 PM PDT 24
Finished Mar 21 02:24:35 PM PDT 24
Peak memory 224648 kb
Host smart-b6a5e136-e26d-4098-a176-6217271c4330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905662295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.3905662295
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.2924429161
Short name T956
Test name
Test status
Simulation time 28561015 ps
CPU time 0.74 seconds
Started Mar 21 02:24:30 PM PDT 24
Finished Mar 21 02:24:31 PM PDT 24
Peak memory 205572 kb
Host smart-d864c01b-1e0d-45b8-8481-53b4470c1982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2924429161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.2924429161
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.228527907
Short name T817
Test name
Test status
Simulation time 30126369226 ps
CPU time 77.95 seconds
Started Mar 21 02:24:28 PM PDT 24
Finished Mar 21 02:25:46 PM PDT 24
Peak memory 250488 kb
Host smart-c828908b-9c7a-476d-a4d2-16b3ad346084
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228527907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.228527907
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.803164721
Short name T658
Test name
Test status
Simulation time 616533211 ps
CPU time 13.41 seconds
Started Mar 21 02:24:28 PM PDT 24
Finished Mar 21 02:24:41 PM PDT 24
Peak memory 238100 kb
Host smart-9778b409-390c-4b92-860e-c49b7b0a6556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=803164721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.803164721
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_intercept.4100979
Short name T435
Test name
Test status
Simulation time 1996413570 ps
CPU time 5.89 seconds
Started Mar 21 02:24:27 PM PDT 24
Finished Mar 21 02:24:33 PM PDT 24
Peak memory 217968 kb
Host smart-fa636677-0d6f-47a0-a266-32d882540983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4100979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.4100979
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.476625414
Short name T225
Test name
Test status
Simulation time 286427598 ps
CPU time 2.67 seconds
Started Mar 21 02:24:27 PM PDT 24
Finished Mar 21 02:24:30 PM PDT 24
Peak memory 232848 kb
Host smart-efffea08-e71c-4a15-af38-3257d875438f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=476625414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.476625414
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_mem_parity.3988028951
Short name T398
Test name
Test status
Simulation time 118505922 ps
CPU time 1.14 seconds
Started Mar 21 02:24:29 PM PDT 24
Finished Mar 21 02:24:30 PM PDT 24
Peak memory 217012 kb
Host smart-cd95422d-cb07-4c6a-8bf1-2f51cb7dab89
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988028951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 14.spi_device_mem_parity.3988028951
Directory /workspace/14.spi_device_mem_parity/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.3099072161
Short name T629
Test name
Test status
Simulation time 548186577 ps
CPU time 5.81 seconds
Started Mar 21 02:24:27 PM PDT 24
Finished Mar 21 02:24:32 PM PDT 24
Peak memory 228072 kb
Host smart-bc8f7fba-8d85-415b-bd40-4bef494a1c1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099072161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swa
p.3099072161
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.215432044
Short name T561
Test name
Test status
Simulation time 18318299122 ps
CPU time 18.15 seconds
Started Mar 21 02:24:26 PM PDT 24
Finished Mar 21 02:24:45 PM PDT 24
Peak memory 240296 kb
Host smart-0a733da5-7dd3-4c93-8db7-44e255b0c40a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=215432044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.215432044
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_ram_cfg.24326045
Short name T984
Test name
Test status
Simulation time 39592001 ps
CPU time 0.73 seconds
Started Mar 21 02:24:25 PM PDT 24
Finished Mar 21 02:24:26 PM PDT 24
Peak memory 216392 kb
Host smart-5ebdd013-369f-448d-9006-88e4de21fefb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24326045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_ram_cfg.24326045
Directory /workspace/14.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.2456152606
Short name T409
Test name
Test status
Simulation time 618014242 ps
CPU time 3.89 seconds
Started Mar 21 02:24:25 PM PDT 24
Finished Mar 21 02:24:29 PM PDT 24
Peak memory 222480 kb
Host smart-3ebbb0d6-a280-4aa8-8dcc-ac0751386955
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2456152606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dir
ect.2456152606
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.2850509191
Short name T826
Test name
Test status
Simulation time 90363709598 ps
CPU time 151.64 seconds
Started Mar 21 02:24:30 PM PDT 24
Finished Mar 21 02:27:02 PM PDT 24
Peak memory 252564 kb
Host smart-f88b5e68-29fa-4dc1-a46b-4fde947912c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850509191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stre
ss_all.2850509191
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.1114244583
Short name T955
Test name
Test status
Simulation time 4575106550 ps
CPU time 33.57 seconds
Started Mar 21 02:24:32 PM PDT 24
Finished Mar 21 02:25:06 PM PDT 24
Peak memory 216580 kb
Host smart-b2e4a3aa-23e8-4273-8dcb-f845f8e998cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114244583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.1114244583
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.351818063
Short name T770
Test name
Test status
Simulation time 17428604217 ps
CPU time 26.61 seconds
Started Mar 21 02:24:30 PM PDT 24
Finished Mar 21 02:24:57 PM PDT 24
Peak memory 216624 kb
Host smart-6c8ba756-d409-4b53-9cd2-1fb6067c9efa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=351818063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.351818063
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.1824652151
Short name T439
Test name
Test status
Simulation time 50371045 ps
CPU time 1.67 seconds
Started Mar 21 02:24:26 PM PDT 24
Finished Mar 21 02:24:28 PM PDT 24
Peak memory 216400 kb
Host smart-98fcd7f4-20c5-406d-a65a-3e2bba3438cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1824652151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.1824652151
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.985127175
Short name T920
Test name
Test status
Simulation time 29937028 ps
CPU time 0.88 seconds
Started Mar 21 02:24:28 PM PDT 24
Finished Mar 21 02:24:29 PM PDT 24
Peak memory 205736 kb
Host smart-b219b728-e4d9-49b1-98df-bbac687fa23c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985127175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.985127175
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.2264882925
Short name T676
Test name
Test status
Simulation time 468336301 ps
CPU time 7.91 seconds
Started Mar 21 02:24:27 PM PDT 24
Finished Mar 21 02:24:35 PM PDT 24
Peak memory 228384 kb
Host smart-b0eb1c50-0454-4f42-9acd-3544ea7333ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2264882925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.2264882925
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.1442148582
Short name T691
Test name
Test status
Simulation time 25430423 ps
CPU time 0.71 seconds
Started Mar 21 02:24:34 PM PDT 24
Finished Mar 21 02:24:34 PM PDT 24
Peak memory 205320 kb
Host smart-6b318a9d-2007-4031-8533-559421889745
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442148582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.
1442148582
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.268904749
Short name T452
Test name
Test status
Simulation time 414863900 ps
CPU time 2.49 seconds
Started Mar 21 02:24:35 PM PDT 24
Finished Mar 21 02:24:38 PM PDT 24
Peak memory 218604 kb
Host smart-945335d1-3f54-4954-8343-4dbf45248c0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=268904749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.268904749
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.250044273
Short name T922
Test name
Test status
Simulation time 66949878 ps
CPU time 0.81 seconds
Started Mar 21 02:24:27 PM PDT 24
Finished Mar 21 02:24:27 PM PDT 24
Peak memory 206896 kb
Host smart-c8c713c8-dc75-41fe-a8d4-ed4f646fc155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=250044273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.250044273
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.1330318002
Short name T246
Test name
Test status
Simulation time 17607106771 ps
CPU time 40.32 seconds
Started Mar 21 02:24:38 PM PDT 24
Finished Mar 21 02:25:19 PM PDT 24
Peak memory 238572 kb
Host smart-73eed828-7db9-4044-bcd9-1e54ad01781e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1330318002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.1330318002
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.598488893
Short name T494
Test name
Test status
Simulation time 340651443694 ps
CPU time 419.74 seconds
Started Mar 21 02:24:34 PM PDT 24
Finished Mar 21 02:31:34 PM PDT 24
Peak memory 265768 kb
Host smart-f67e6854-854d-469f-b960-7564a7d58029
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=598488893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.598488893
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.1431436312
Short name T198
Test name
Test status
Simulation time 52140845605 ps
CPU time 278.38 seconds
Started Mar 21 02:24:38 PM PDT 24
Finished Mar 21 02:29:17 PM PDT 24
Peak memory 255524 kb
Host smart-d52b11b6-ae76-4259-b478-62aff0c16677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1431436312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idl
e.1431436312
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.3013843550
Short name T314
Test name
Test status
Simulation time 1115858230 ps
CPU time 12.95 seconds
Started Mar 21 02:24:35 PM PDT 24
Finished Mar 21 02:24:48 PM PDT 24
Peak memory 234928 kb
Host smart-af8a60a3-354c-4f5e-a981-112a47b6298a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013843550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.3013843550
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_intercept.1106102222
Short name T199
Test name
Test status
Simulation time 1265928589 ps
CPU time 6.28 seconds
Started Mar 21 02:24:35 PM PDT 24
Finished Mar 21 02:24:41 PM PDT 24
Peak memory 217964 kb
Host smart-9fb2a86c-a69f-4e0f-b6c0-e0d265126701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1106102222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.1106102222
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.839678203
Short name T725
Test name
Test status
Simulation time 4441262615 ps
CPU time 13.87 seconds
Started Mar 21 02:24:37 PM PDT 24
Finished Mar 21 02:24:51 PM PDT 24
Peak memory 240992 kb
Host smart-71e9a797-495e-4199-b342-c65451331e88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=839678203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.839678203
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_mem_parity.3191406950
Short name T419
Test name
Test status
Simulation time 91101120 ps
CPU time 1.11 seconds
Started Mar 21 02:24:26 PM PDT 24
Finished Mar 21 02:24:27 PM PDT 24
Peak memory 218240 kb
Host smart-88f906f9-02eb-46bf-8ff2-b29cef9874e3
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191406950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 15.spi_device_mem_parity.3191406950
Directory /workspace/15.spi_device_mem_parity/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.2191962202
Short name T603
Test name
Test status
Simulation time 327529986 ps
CPU time 3.28 seconds
Started Mar 21 02:24:34 PM PDT 24
Finished Mar 21 02:24:37 PM PDT 24
Peak memory 233224 kb
Host smart-f5352463-1bdd-4326-8b63-0992b3ac0f3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2191962202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swa
p.2191962202
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.1116610032
Short name T869
Test name
Test status
Simulation time 11571014097 ps
CPU time 26.44 seconds
Started Mar 21 02:24:38 PM PDT 24
Finished Mar 21 02:25:05 PM PDT 24
Peak memory 218176 kb
Host smart-21e908a9-d64f-497b-ac85-a3c9ba3cb436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1116610032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.1116610032
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_ram_cfg.2883264800
Short name T535
Test name
Test status
Simulation time 38297704 ps
CPU time 0.74 seconds
Started Mar 21 02:24:32 PM PDT 24
Finished Mar 21 02:24:33 PM PDT 24
Peak memory 216356 kb
Host smart-67e31613-1c9f-4c29-8776-3d744e37dff7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2883264800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_ram_cfg.2883264800
Directory /workspace/15.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.1105874304
Short name T892
Test name
Test status
Simulation time 1378789674 ps
CPU time 4.12 seconds
Started Mar 21 02:24:36 PM PDT 24
Finished Mar 21 02:24:41 PM PDT 24
Peak memory 223004 kb
Host smart-f69269df-2f5b-440a-b344-1dc1513c5a53
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1105874304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir
ect.1105874304
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.973167882
Short name T860
Test name
Test status
Simulation time 10513220187 ps
CPU time 54.2 seconds
Started Mar 21 02:24:38 PM PDT 24
Finished Mar 21 02:25:32 PM PDT 24
Peak memory 216424 kb
Host smart-84527ebb-e314-4879-8992-bf47c66b705e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=973167882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.973167882
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.818380538
Short name T443
Test name
Test status
Simulation time 48089478735 ps
CPU time 17.54 seconds
Started Mar 21 02:24:27 PM PDT 24
Finished Mar 21 02:24:45 PM PDT 24
Peak memory 216532 kb
Host smart-e6494988-a667-47d7-9e42-5a09e8a5e76e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=818380538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.818380538
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.4226702993
Short name T358
Test name
Test status
Simulation time 307966319 ps
CPU time 2.66 seconds
Started Mar 21 02:24:34 PM PDT 24
Finished Mar 21 02:24:37 PM PDT 24
Peak memory 216424 kb
Host smart-1da627e3-2c5f-4bbe-be8e-41c102298fdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4226702993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.4226702993
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.3171827723
Short name T552
Test name
Test status
Simulation time 211408184 ps
CPU time 0.97 seconds
Started Mar 21 02:24:35 PM PDT 24
Finished Mar 21 02:24:36 PM PDT 24
Peak memory 206232 kb
Host smart-1c950f1d-6fe3-4591-a774-0b3a3d7a0d32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3171827723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.3171827723
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.1980351076
Short name T971
Test name
Test status
Simulation time 10442871639 ps
CPU time 35.67 seconds
Started Mar 21 02:24:36 PM PDT 24
Finished Mar 21 02:25:11 PM PDT 24
Peak memory 243400 kb
Host smart-e8aade90-8e71-42f8-a020-cc4492bc70f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1980351076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.1980351076
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.4237090401
Short name T783
Test name
Test status
Simulation time 13482973 ps
CPU time 0.7 seconds
Started Mar 21 02:24:45 PM PDT 24
Finished Mar 21 02:24:46 PM PDT 24
Peak memory 205396 kb
Host smart-b14a957f-9dcd-495c-a51b-6c2e36870861
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237090401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.
4237090401
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.3551624288
Short name T534
Test name
Test status
Simulation time 137037018 ps
CPU time 2.07 seconds
Started Mar 21 02:24:34 PM PDT 24
Finished Mar 21 02:24:36 PM PDT 24
Peak memory 216948 kb
Host smart-f76ba6e3-4270-402f-ac65-f2ceb0478863
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3551624288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.3551624288
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.1147026391
Short name T931
Test name
Test status
Simulation time 20201241 ps
CPU time 0.77 seconds
Started Mar 21 02:24:34 PM PDT 24
Finished Mar 21 02:24:35 PM PDT 24
Peak memory 206568 kb
Host smart-26dcdf1c-3c79-4470-adaf-1cc4c723da8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1147026391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.1147026391
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.3868511091
Short name T29
Test name
Test status
Simulation time 64367174449 ps
CPU time 63.05 seconds
Started Mar 21 02:24:36 PM PDT 24
Finished Mar 21 02:25:39 PM PDT 24
Peak memory 233228 kb
Host smart-34133001-b23f-4d08-81dd-b616d37e2026
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3868511091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.3868511091
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.3916819304
Short name T239
Test name
Test status
Simulation time 14646993887 ps
CPU time 57.79 seconds
Started Mar 21 02:24:48 PM PDT 24
Finished Mar 21 02:25:45 PM PDT 24
Peak memory 236028 kb
Host smart-e73cbd77-38ea-4211-8831-9bc3dac5aa46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916819304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idl
e.3916819304
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.2712127077
Short name T83
Test name
Test status
Simulation time 677446121 ps
CPU time 8.89 seconds
Started Mar 21 02:24:35 PM PDT 24
Finished Mar 21 02:24:44 PM PDT 24
Peak memory 248908 kb
Host smart-308b6c65-3f6d-4313-8826-c2840d0d4b95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712127077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.2712127077
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_intercept.2274074900
Short name T700
Test name
Test status
Simulation time 349091854 ps
CPU time 2.95 seconds
Started Mar 21 02:24:34 PM PDT 24
Finished Mar 21 02:24:37 PM PDT 24
Peak memory 217916 kb
Host smart-7a150ae8-1c2e-4506-9bcd-cb3c1643081f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2274074900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.2274074900
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.1212106146
Short name T230
Test name
Test status
Simulation time 14157093865 ps
CPU time 36.78 seconds
Started Mar 21 02:24:37 PM PDT 24
Finished Mar 21 02:25:14 PM PDT 24
Peak memory 241072 kb
Host smart-070e074d-cbf6-4b32-add5-d35fedbb7ad6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1212106146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.1212106146
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_mem_parity.3897695630
Short name T66
Test name
Test status
Simulation time 104056208 ps
CPU time 1.07 seconds
Started Mar 21 02:24:41 PM PDT 24
Finished Mar 21 02:24:42 PM PDT 24
Peak memory 218224 kb
Host smart-3ad0945c-f33f-4fb3-8b77-b5cf46b944c3
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897695630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 16.spi_device_mem_parity.3897695630
Directory /workspace/16.spi_device_mem_parity/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.219125716
Short name T741
Test name
Test status
Simulation time 10075133565 ps
CPU time 9.43 seconds
Started Mar 21 02:24:33 PM PDT 24
Finished Mar 21 02:24:43 PM PDT 24
Peak memory 233840 kb
Host smart-c7626847-d2f6-4cc4-9555-50c5cf99cca4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=219125716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swap
.219125716
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.3792010313
Short name T792
Test name
Test status
Simulation time 32914611989 ps
CPU time 16.15 seconds
Started Mar 21 02:24:34 PM PDT 24
Finished Mar 21 02:24:50 PM PDT 24
Peak memory 224796 kb
Host smart-413687ec-b6a5-45f6-aece-85001921969f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792010313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.3792010313
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_ram_cfg.4006604593
Short name T886
Test name
Test status
Simulation time 23459169 ps
CPU time 0.74 seconds
Started Mar 21 02:24:39 PM PDT 24
Finished Mar 21 02:24:40 PM PDT 24
Peak memory 216400 kb
Host smart-c8d37da4-8b17-4224-b63a-b427196a9e58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4006604593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_ram_cfg.4006604593
Directory /workspace/16.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.45324376
Short name T5
Test name
Test status
Simulation time 108174147 ps
CPU time 3.54 seconds
Started Mar 21 02:24:38 PM PDT 24
Finished Mar 21 02:24:41 PM PDT 24
Peak memory 222840 kb
Host smart-6ec0e57b-a4c8-4737-ac25-fdc758b8d64f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=45324376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_direc
t.45324376
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.2564465357
Short name T686
Test name
Test status
Simulation time 154301655 ps
CPU time 0.98 seconds
Started Mar 21 02:24:44 PM PDT 24
Finished Mar 21 02:24:46 PM PDT 24
Peak memory 206984 kb
Host smart-752bb4f3-19a0-4373-a5f3-86b6bdae0d8b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564465357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stre
ss_all.2564465357
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.2130194623
Short name T813
Test name
Test status
Simulation time 3893831464 ps
CPU time 19.6 seconds
Started Mar 21 02:24:37 PM PDT 24
Finished Mar 21 02:24:57 PM PDT 24
Peak memory 216612 kb
Host smart-f2783fba-0c19-4372-9ae6-58ad2e9e5c62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130194623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.2130194623
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.2981188974
Short name T470
Test name
Test status
Simulation time 10763023464 ps
CPU time 14.74 seconds
Started Mar 21 02:24:35 PM PDT 24
Finished Mar 21 02:24:50 PM PDT 24
Peak memory 216608 kb
Host smart-121d8c38-11d3-4308-8477-b5e766d6572c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2981188974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.2981188974
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.2798917219
Short name T329
Test name
Test status
Simulation time 24950627 ps
CPU time 1.47 seconds
Started Mar 21 02:24:34 PM PDT 24
Finished Mar 21 02:24:35 PM PDT 24
Peak memory 216636 kb
Host smart-7b30e356-8a88-42e0-9794-5d63cd522001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2798917219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.2798917219
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.3476857668
Short name T715
Test name
Test status
Simulation time 99739036 ps
CPU time 1.05 seconds
Started Mar 21 02:24:36 PM PDT 24
Finished Mar 21 02:24:37 PM PDT 24
Peak memory 205768 kb
Host smart-d727d27f-085a-4fd4-bd48-de26842e0887
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3476857668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.3476857668
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.1622817361
Short name T36
Test name
Test status
Simulation time 7386192649 ps
CPU time 26.38 seconds
Started Mar 21 02:24:34 PM PDT 24
Finished Mar 21 02:25:01 PM PDT 24
Peak memory 233000 kb
Host smart-2c3fb5ad-89d6-4a3c-a6fd-b68610d07dc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1622817361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.1622817361
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.1065111264
Short name T812
Test name
Test status
Simulation time 16331348 ps
CPU time 0.69 seconds
Started Mar 21 02:24:44 PM PDT 24
Finished Mar 21 02:24:45 PM PDT 24
Peak memory 205408 kb
Host smart-9c0e71d3-843c-40cc-8c4f-b40f8e65141e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065111264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.
1065111264
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.2053282020
Short name T503
Test name
Test status
Simulation time 409109462 ps
CPU time 3.73 seconds
Started Mar 21 02:24:44 PM PDT 24
Finished Mar 21 02:24:48 PM PDT 24
Peak memory 219956 kb
Host smart-090c512b-545c-4f8d-aecd-ac53341bdd9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053282020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.2053282020
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.983568705
Short name T863
Test name
Test status
Simulation time 18265789 ps
CPU time 0.78 seconds
Started Mar 21 02:24:48 PM PDT 24
Finished Mar 21 02:24:49 PM PDT 24
Peak memory 205556 kb
Host smart-b685b13a-fbd8-419d-8eb3-dc5d1a572dc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=983568705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.983568705
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.419944713
Short name T933
Test name
Test status
Simulation time 6701656647 ps
CPU time 41.17 seconds
Started Mar 21 02:24:44 PM PDT 24
Finished Mar 21 02:25:26 PM PDT 24
Peak memory 238112 kb
Host smart-0be1f0ca-b876-4827-ad14-13317ef6b761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=419944713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.419944713
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.971488490
Short name T101
Test name
Test status
Simulation time 10151110371 ps
CPU time 46.77 seconds
Started Mar 21 02:24:48 PM PDT 24
Finished Mar 21 02:25:35 PM PDT 24
Peak memory 239316 kb
Host smart-0e6f2b2e-7f62-4c62-89f3-bd8130120b84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=971488490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.971488490
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.2414813992
Short name T37
Test name
Test status
Simulation time 7096680706 ps
CPU time 74.23 seconds
Started Mar 21 02:24:44 PM PDT 24
Finished Mar 21 02:25:59 PM PDT 24
Peak memory 265844 kb
Host smart-0fc66a15-1682-4063-9172-c578115c086b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2414813992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idl
e.2414813992
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.2096312633
Short name T605
Test name
Test status
Simulation time 29363475903 ps
CPU time 45.35 seconds
Started Mar 21 02:24:43 PM PDT 24
Finished Mar 21 02:25:30 PM PDT 24
Peak memory 237248 kb
Host smart-ae9f6de4-3298-4a1a-b7dd-953a68052b7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096312633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.2096312633
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_intercept.2095942463
Short name T772
Test name
Test status
Simulation time 4161312862 ps
CPU time 3.81 seconds
Started Mar 21 02:24:48 PM PDT 24
Finished Mar 21 02:24:52 PM PDT 24
Peak memory 224736 kb
Host smart-5fd0e0ad-d284-4676-9e6e-a08772212b18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2095942463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.2095942463
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.653258578
Short name T733
Test name
Test status
Simulation time 4413679675 ps
CPU time 10.95 seconds
Started Mar 21 02:24:46 PM PDT 24
Finished Mar 21 02:24:59 PM PDT 24
Peak memory 240160 kb
Host smart-1501aac1-e9ed-422c-8e97-8c4654cb2ca3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653258578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.653258578
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_mem_parity.3355951013
Short name T586
Test name
Test status
Simulation time 14538565 ps
CPU time 0.95 seconds
Started Mar 21 02:24:44 PM PDT 24
Finished Mar 21 02:24:46 PM PDT 24
Peak memory 218196 kb
Host smart-fbc5d86b-12ef-4e0b-a1f7-d08d80715dac
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355951013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 17.spi_device_mem_parity.3355951013
Directory /workspace/17.spi_device_mem_parity/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.1438321350
Short name T717
Test name
Test status
Simulation time 2489155392 ps
CPU time 7.08 seconds
Started Mar 21 02:24:44 PM PDT 24
Finished Mar 21 02:24:52 PM PDT 24
Peak memory 217080 kb
Host smart-b18ba0d1-084d-434a-a116-f84e4543eca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1438321350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swa
p.1438321350
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.1299525438
Short name T502
Test name
Test status
Simulation time 340690180 ps
CPU time 3.15 seconds
Started Mar 21 02:24:46 PM PDT 24
Finished Mar 21 02:24:51 PM PDT 24
Peak memory 217164 kb
Host smart-ee9877b3-042c-4592-b594-ef7292f42521
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1299525438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.1299525438
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_ram_cfg.630759176
Short name T74
Test name
Test status
Simulation time 26923884 ps
CPU time 0.76 seconds
Started Mar 21 02:24:44 PM PDT 24
Finished Mar 21 02:24:45 PM PDT 24
Peak memory 216396 kb
Host smart-6af80f7a-58bb-4461-9051-d26c69cc3f37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=630759176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_ram_cfg.630759176
Directory /workspace/17.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.1830369324
Short name T738
Test name
Test status
Simulation time 1236916392 ps
CPU time 5.72 seconds
Started Mar 21 02:24:44 PM PDT 24
Finished Mar 21 02:24:50 PM PDT 24
Peak memory 220608 kb
Host smart-f2e3ac8c-791d-473e-a01d-d9649f72cab4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1830369324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dir
ect.1830369324
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.3635070913
Short name T175
Test name
Test status
Simulation time 186148485 ps
CPU time 1.04 seconds
Started Mar 21 02:24:48 PM PDT 24
Finished Mar 21 02:24:49 PM PDT 24
Peak memory 207120 kb
Host smart-6a69cf2b-7fca-4d0b-a340-4136bebf7703
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635070913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stre
ss_all.3635070913
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.2255034877
Short name T413
Test name
Test status
Simulation time 15068474465 ps
CPU time 82.55 seconds
Started Mar 21 02:24:48 PM PDT 24
Finished Mar 21 02:26:10 PM PDT 24
Peak memory 216576 kb
Host smart-663c5a41-ee35-48b9-b1be-4988ee6cc2ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2255034877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.2255034877
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.3315041868
Short name T579
Test name
Test status
Simulation time 552489377 ps
CPU time 3.07 seconds
Started Mar 21 02:24:50 PM PDT 24
Finished Mar 21 02:24:53 PM PDT 24
Peak memory 216396 kb
Host smart-d9b9fdb8-572e-40e9-b6e0-7077c4d0a8cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315041868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.3315041868
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.1163759647
Short name T423
Test name
Test status
Simulation time 141613039 ps
CPU time 1.34 seconds
Started Mar 21 02:24:49 PM PDT 24
Finished Mar 21 02:24:50 PM PDT 24
Peak memory 216428 kb
Host smart-d8fc5717-504f-4f9c-83a4-de0882393c84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1163759647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.1163759647
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.124325541
Short name T372
Test name
Test status
Simulation time 57593115 ps
CPU time 0.83 seconds
Started Mar 21 02:24:46 PM PDT 24
Finished Mar 21 02:24:48 PM PDT 24
Peak memory 205820 kb
Host smart-2e7fc6b8-caeb-4213-9c13-cbd053c04371
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=124325541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.124325541
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.1192676865
Short name T945
Test name
Test status
Simulation time 39502111494 ps
CPU time 31.51 seconds
Started Mar 21 02:24:44 PM PDT 24
Finished Mar 21 02:25:16 PM PDT 24
Peak memory 228748 kb
Host smart-a3522149-9fe6-4e00-9dff-1c08de191477
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192676865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.1192676865
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.1181100234
Short name T824
Test name
Test status
Simulation time 14984545 ps
CPU time 0.76 seconds
Started Mar 21 02:24:55 PM PDT 24
Finished Mar 21 02:24:57 PM PDT 24
Peak memory 204792 kb
Host smart-0d196fe0-26c3-461b-b5af-9c50d963d8e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181100234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.
1181100234
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.2918655995
Short name T353
Test name
Test status
Simulation time 500209140 ps
CPU time 2.75 seconds
Started Mar 21 02:24:56 PM PDT 24
Finished Mar 21 02:25:00 PM PDT 24
Peak memory 224644 kb
Host smart-2b765f0c-d918-4153-a19b-3ab241f7f35e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2918655995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.2918655995
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.3749925846
Short name T915
Test name
Test status
Simulation time 72842601 ps
CPU time 0.8 seconds
Started Mar 21 02:24:48 PM PDT 24
Finished Mar 21 02:24:49 PM PDT 24
Peak memory 206596 kb
Host smart-3cd832f3-0b1c-4416-b81e-b6ff90efb68d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749925846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.3749925846
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.3488302977
Short name T257
Test name
Test status
Simulation time 103112682280 ps
CPU time 522.31 seconds
Started Mar 21 02:24:56 PM PDT 24
Finished Mar 21 02:33:39 PM PDT 24
Peak memory 269792 kb
Host smart-3235400d-3588-438e-bde5-09fd37b57ee3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3488302977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.3488302977
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.2614646224
Short name T418
Test name
Test status
Simulation time 37818825418 ps
CPU time 114.68 seconds
Started Mar 21 02:24:58 PM PDT 24
Finished Mar 21 02:26:53 PM PDT 24
Peak memory 249892 kb
Host smart-6d7a5e48-a7e8-413d-ac01-c148d3bbdc8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2614646224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.2614646224
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.2495709548
Short name T759
Test name
Test status
Simulation time 58270750338 ps
CPU time 335.22 seconds
Started Mar 21 02:24:56 PM PDT 24
Finished Mar 21 02:30:32 PM PDT 24
Peak memory 267392 kb
Host smart-3fe7528c-2304-4d06-8047-f2bd143f0fe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2495709548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idl
e.2495709548
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.220148817
Short name T957
Test name
Test status
Simulation time 6355315386 ps
CPU time 31.83 seconds
Started Mar 21 02:24:56 PM PDT 24
Finished Mar 21 02:25:29 PM PDT 24
Peak memory 232920 kb
Host smart-7729801b-2e83-419a-a0bb-182b896ded19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=220148817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.220148817
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_intercept.2421789603
Short name T264
Test name
Test status
Simulation time 377939923 ps
CPU time 4.53 seconds
Started Mar 21 02:24:46 PM PDT 24
Finished Mar 21 02:24:52 PM PDT 24
Peak memory 219668 kb
Host smart-9279842b-6433-4066-9e80-49c0749fdf6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2421789603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.2421789603
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.2258636176
Short name T901
Test name
Test status
Simulation time 2223137470 ps
CPU time 7.02 seconds
Started Mar 21 02:24:56 PM PDT 24
Finished Mar 21 02:25:04 PM PDT 24
Peak memory 226968 kb
Host smart-cc76f61e-ac81-445d-8dbb-77a235b2ea91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2258636176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.2258636176
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_mem_parity.1432110509
Short name T916
Test name
Test status
Simulation time 109344475 ps
CPU time 1.08 seconds
Started Mar 21 02:24:45 PM PDT 24
Finished Mar 21 02:24:46 PM PDT 24
Peak memory 216956 kb
Host smart-0bba61fc-6d2c-47ca-99bc-083265a3f1f3
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432110509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 18.spi_device_mem_parity.1432110509
Directory /workspace/18.spi_device_mem_parity/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.2950677102
Short name T902
Test name
Test status
Simulation time 3940777861 ps
CPU time 7.46 seconds
Started Mar 21 02:24:44 PM PDT 24
Finished Mar 21 02:24:52 PM PDT 24
Peak memory 217356 kb
Host smart-bf06e77d-5a8a-4045-aec9-0adc9f9b5b5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2950677102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swa
p.2950677102
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.346335142
Short name T462
Test name
Test status
Simulation time 839469104 ps
CPU time 8.75 seconds
Started Mar 21 02:24:44 PM PDT 24
Finished Mar 21 02:24:53 PM PDT 24
Peak memory 234932 kb
Host smart-eff0af66-e917-4822-9ac3-2fc070ed8ab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=346335142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.346335142
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_ram_cfg.2257670547
Short name T543
Test name
Test status
Simulation time 37345866 ps
CPU time 0.77 seconds
Started Mar 21 02:24:46 PM PDT 24
Finished Mar 21 02:24:48 PM PDT 24
Peak memory 216408 kb
Host smart-e3bca256-9297-4570-b05a-81074b1613fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2257670547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_ram_cfg.2257670547
Directory /workspace/18.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.3551100392
Short name T571
Test name
Test status
Simulation time 3616081754 ps
CPU time 5.46 seconds
Started Mar 21 02:24:59 PM PDT 24
Finished Mar 21 02:25:05 PM PDT 24
Peak memory 223056 kb
Host smart-a8ff4ce4-c443-4f53-a52d-dd4264a41986
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3551100392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dir
ect.3551100392
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.584334187
Short name T867
Test name
Test status
Simulation time 42754865898 ps
CPU time 309.88 seconds
Started Mar 21 02:24:59 PM PDT 24
Finished Mar 21 02:30:09 PM PDT 24
Peak memory 256480 kb
Host smart-1feb8f69-78ec-4e34-8926-c126462dabb8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584334187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stres
s_all.584334187
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.2299372333
Short name T856
Test name
Test status
Simulation time 2390482017 ps
CPU time 19.56 seconds
Started Mar 21 02:24:48 PM PDT 24
Finished Mar 21 02:25:07 PM PDT 24
Peak memory 216704 kb
Host smart-835efbd6-5584-4362-a48c-b444382ee0dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299372333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.2299372333
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.3783798193
Short name T660
Test name
Test status
Simulation time 18667274236 ps
CPU time 12.4 seconds
Started Mar 21 02:24:46 PM PDT 24
Finished Mar 21 02:25:00 PM PDT 24
Peak memory 216600 kb
Host smart-065c28d9-8311-4c91-a2c8-95356991a403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783798193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.3783798193
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.3132729301
Short name T594
Test name
Test status
Simulation time 136880597 ps
CPU time 1.52 seconds
Started Mar 21 02:24:48 PM PDT 24
Finished Mar 21 02:24:49 PM PDT 24
Peak memory 216472 kb
Host smart-07dd3e34-170a-4005-a08f-d6ebd8d7ad75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3132729301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.3132729301
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.927755032
Short name T514
Test name
Test status
Simulation time 30031862 ps
CPU time 0.82 seconds
Started Mar 21 02:24:47 PM PDT 24
Finished Mar 21 02:24:48 PM PDT 24
Peak memory 205744 kb
Host smart-ecdbff1b-d08e-4849-b95b-655b724ed3b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927755032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.927755032
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.2025111767
Short name T43
Test name
Test status
Simulation time 5683662147 ps
CPU time 7.81 seconds
Started Mar 21 02:24:58 PM PDT 24
Finished Mar 21 02:25:06 PM PDT 24
Peak memory 220844 kb
Host smart-aa0926c0-2be7-433f-aebc-8522286e42a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2025111767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.2025111767
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.3650063615
Short name T61
Test name
Test status
Simulation time 791199873 ps
CPU time 5.07 seconds
Started Mar 21 02:24:56 PM PDT 24
Finished Mar 21 02:25:02 PM PDT 24
Peak memory 235120 kb
Host smart-84483d07-dff5-4d33-b1f7-8752816310e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3650063615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.3650063615
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.2861059583
Short name T457
Test name
Test status
Simulation time 16642760 ps
CPU time 0.77 seconds
Started Mar 21 02:24:55 PM PDT 24
Finished Mar 21 02:24:56 PM PDT 24
Peak memory 206940 kb
Host smart-3f0ed00c-9b6c-4e17-878f-d67f8e9e641d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2861059583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.2861059583
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.2936622304
Short name T816
Test name
Test status
Simulation time 16995016444 ps
CPU time 98.73 seconds
Started Mar 21 02:25:09 PM PDT 24
Finished Mar 21 02:26:48 PM PDT 24
Peak memory 257296 kb
Host smart-f4a2e0f9-36d8-4471-b924-fd850c789533
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2936622304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.2936622304
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.1340570737
Short name T51
Test name
Test status
Simulation time 190448696452 ps
CPU time 328.39 seconds
Started Mar 21 02:25:09 PM PDT 24
Finished Mar 21 02:30:37 PM PDT 24
Peak memory 271840 kb
Host smart-340793aa-9731-4683-b9fe-670c759b69ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1340570737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.1340570737
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.1885065475
Short name T425
Test name
Test status
Simulation time 1561267346 ps
CPU time 14.89 seconds
Started Mar 21 02:24:58 PM PDT 24
Finished Mar 21 02:25:13 PM PDT 24
Peak memory 242836 kb
Host smart-90a4569d-02ef-4c0c-b42a-dbfc910669bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1885065475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.1885065475
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_intercept.2127633981
Short name T263
Test name
Test status
Simulation time 571230678 ps
CPU time 2.69 seconds
Started Mar 21 02:24:56 PM PDT 24
Finished Mar 21 02:25:00 PM PDT 24
Peak memory 224528 kb
Host smart-ba134f29-7f57-4847-9435-eb635400d942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127633981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.2127633981
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.2847410414
Short name T441
Test name
Test status
Simulation time 2107783280 ps
CPU time 16.02 seconds
Started Mar 21 02:24:55 PM PDT 24
Finished Mar 21 02:25:11 PM PDT 24
Peak memory 253748 kb
Host smart-328bad28-de4c-4f8a-98e5-8924fd92d9b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2847410414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.2847410414
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_mem_parity.3973296284
Short name T68
Test name
Test status
Simulation time 35974439 ps
CPU time 1.16 seconds
Started Mar 21 02:24:56 PM PDT 24
Finished Mar 21 02:24:58 PM PDT 24
Peak memory 217004 kb
Host smart-afe42232-17a1-4eee-a6dc-037be56f6819
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973296284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 19.spi_device_mem_parity.3973296284
Directory /workspace/19.spi_device_mem_parity/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.766065763
Short name T231
Test name
Test status
Simulation time 3102022330 ps
CPU time 10.6 seconds
Started Mar 21 02:24:57 PM PDT 24
Finished Mar 21 02:25:07 PM PDT 24
Peak memory 219328 kb
Host smart-467942a5-dcf8-4b6f-aa58-8d7e4ab1b60a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=766065763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swap
.766065763
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.3425862696
Short name T42
Test name
Test status
Simulation time 12259831781 ps
CPU time 10.85 seconds
Started Mar 21 02:24:56 PM PDT 24
Finished Mar 21 02:25:08 PM PDT 24
Peak memory 232976 kb
Host smart-e260924a-d36e-4e12-af55-34be4505b713
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3425862696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.3425862696
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_ram_cfg.469011889
Short name T383
Test name
Test status
Simulation time 16601282 ps
CPU time 0.77 seconds
Started Mar 21 02:24:58 PM PDT 24
Finished Mar 21 02:24:59 PM PDT 24
Peak memory 216444 kb
Host smart-6d190ecc-509e-4c7c-89ba-9e9c179fb6b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=469011889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_ram_cfg.469011889
Directory /workspace/19.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.84398030
Short name T618
Test name
Test status
Simulation time 545113223 ps
CPU time 4.22 seconds
Started Mar 21 02:24:56 PM PDT 24
Finished Mar 21 02:25:01 PM PDT 24
Peak memory 219868 kb
Host smart-390bde1a-b113-45c5-9686-18b34fea1ec0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=84398030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_direc
t.84398030
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.2945949512
Short name T991
Test name
Test status
Simulation time 49472263 ps
CPU time 1.07 seconds
Started Mar 21 02:25:08 PM PDT 24
Finished Mar 21 02:25:09 PM PDT 24
Peak memory 206828 kb
Host smart-0cf36545-2443-4f2d-acf4-123d1b5ae0d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945949512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stre
ss_all.2945949512
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.3426906350
Short name T982
Test name
Test status
Simulation time 31877796741 ps
CPU time 43.69 seconds
Started Mar 21 02:24:59 PM PDT 24
Finished Mar 21 02:25:43 PM PDT 24
Peak memory 216560 kb
Host smart-b9db57c1-d878-49d0-848d-99444e37f5a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3426906350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.3426906350
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.3850053382
Short name T939
Test name
Test status
Simulation time 4251396711 ps
CPU time 19.38 seconds
Started Mar 21 02:24:55 PM PDT 24
Finished Mar 21 02:25:15 PM PDT 24
Peak memory 216512 kb
Host smart-10c50482-c397-4948-a21a-05873f983694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850053382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.3850053382
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.3291071375
Short name T548
Test name
Test status
Simulation time 15614345 ps
CPU time 0.87 seconds
Started Mar 21 02:24:55 PM PDT 24
Finished Mar 21 02:24:56 PM PDT 24
Peak memory 206788 kb
Host smart-4699d704-6965-414b-9444-a9b62e3a5850
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3291071375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.3291071375
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.112509702
Short name T526
Test name
Test status
Simulation time 92159815 ps
CPU time 0.79 seconds
Started Mar 21 02:24:57 PM PDT 24
Finished Mar 21 02:24:58 PM PDT 24
Peak memory 205716 kb
Host smart-14d74027-94cc-4f2a-b34d-2147eae8a9ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112509702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.112509702
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.1295185472
Short name T283
Test name
Test status
Simulation time 294685173 ps
CPU time 5.37 seconds
Started Mar 21 02:24:57 PM PDT 24
Finished Mar 21 02:25:03 PM PDT 24
Peak memory 233604 kb
Host smart-8cfcc067-2c6b-43eb-9517-b72470410602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1295185472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.1295185472
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.1629091312
Short name T364
Test name
Test status
Simulation time 38762371 ps
CPU time 0.75 seconds
Started Mar 21 02:23:16 PM PDT 24
Finished Mar 21 02:23:17 PM PDT 24
Peak memory 205436 kb
Host smart-8cd04e2f-e71e-46d5-bad3-256f4c85816f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629091312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.1
629091312
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.3294017678
Short name T259
Test name
Test status
Simulation time 319762790 ps
CPU time 4.08 seconds
Started Mar 21 02:23:16 PM PDT 24
Finished Mar 21 02:23:20 PM PDT 24
Peak memory 233900 kb
Host smart-bc867791-aa8a-4665-9862-494d58579f12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294017678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.3294017678
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.3836528772
Short name T472
Test name
Test status
Simulation time 40760003 ps
CPU time 0.75 seconds
Started Mar 21 02:23:08 PM PDT 24
Finished Mar 21 02:23:09 PM PDT 24
Peak memory 205568 kb
Host smart-59d67c28-d48e-4b86-b3c1-9e4062f56b15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3836528772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.3836528772
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.986505610
Short name T210
Test name
Test status
Simulation time 11201047312 ps
CPU time 30.85 seconds
Started Mar 21 02:23:19 PM PDT 24
Finished Mar 21 02:23:50 PM PDT 24
Peak memory 241172 kb
Host smart-ae5acea1-21dd-40ea-9bfa-2806c4f02dad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=986505610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.986505610
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.3762368189
Short name T238
Test name
Test status
Simulation time 23667766656 ps
CPU time 222.65 seconds
Started Mar 21 02:23:16 PM PDT 24
Finished Mar 21 02:26:59 PM PDT 24
Peak memory 257636 kb
Host smart-335e33e5-ed5f-4602-86e3-d20b691551ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3762368189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle
.3762368189
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.1713008369
Short name T790
Test name
Test status
Simulation time 769382845 ps
CPU time 12.3 seconds
Started Mar 21 02:23:28 PM PDT 24
Finished Mar 21 02:23:41 PM PDT 24
Peak memory 236836 kb
Host smart-04053aa5-2f63-4693-86c7-685ee7f1bd8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1713008369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.1713008369
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_intercept.97733384
Short name T789
Test name
Test status
Simulation time 10129388835 ps
CPU time 9.77 seconds
Started Mar 21 02:23:19 PM PDT 24
Finished Mar 21 02:23:29 PM PDT 24
Peak memory 224724 kb
Host smart-a20793bf-cd9b-4784-88bf-6c10da271247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97733384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.97733384
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.1369542608
Short name T834
Test name
Test status
Simulation time 174939605 ps
CPU time 2.6 seconds
Started Mar 21 02:23:17 PM PDT 24
Finished Mar 21 02:23:20 PM PDT 24
Peak memory 218644 kb
Host smart-7c5b77c3-3655-4ac8-8073-d47047e50537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369542608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.1369542608
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_mem_parity.3190478952
Short name T28
Test name
Test status
Simulation time 207336919 ps
CPU time 1.06 seconds
Started Mar 21 02:23:17 PM PDT 24
Finished Mar 21 02:23:18 PM PDT 24
Peak memory 218228 kb
Host smart-87e81f21-5285-4a48-9dd0-4ab812ccd4e0
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190478952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 2.spi_device_mem_parity.3190478952
Directory /workspace/2.spi_device_mem_parity/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.2087917449
Short name T591
Test name
Test status
Simulation time 2543751949 ps
CPU time 7.47 seconds
Started Mar 21 02:23:19 PM PDT 24
Finished Mar 21 02:23:27 PM PDT 24
Peak memory 226944 kb
Host smart-e874d716-d326-4e59-9a62-f428d69527af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087917449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap
.2087917449
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.3862397867
Short name T41
Test name
Test status
Simulation time 1215196242 ps
CPU time 8.97 seconds
Started Mar 21 02:23:17 PM PDT 24
Finished Mar 21 02:23:26 PM PDT 24
Peak memory 240240 kb
Host smart-5dbfee9f-3cc5-4717-8eea-ad43b608aa24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3862397867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.3862397867
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_ram_cfg.1504266908
Short name T76
Test name
Test status
Simulation time 32220242 ps
CPU time 0.71 seconds
Started Mar 21 02:23:18 PM PDT 24
Finished Mar 21 02:23:19 PM PDT 24
Peak memory 216384 kb
Host smart-cb322983-7629-470c-85da-9a12bbd84b88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1504266908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_ram_cfg.1504266908
Directory /workspace/2.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.647725992
Short name T573
Test name
Test status
Simulation time 10760520006 ps
CPU time 5.91 seconds
Started Mar 21 02:23:17 PM PDT 24
Finished Mar 21 02:23:24 PM PDT 24
Peak memory 223292 kb
Host smart-3391607d-efa5-4546-9151-ba3fb847e553
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=647725992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_direc
t.647725992
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.1103448705
Short name T77
Test name
Test status
Simulation time 42298635 ps
CPU time 1.03 seconds
Started Mar 21 02:23:17 PM PDT 24
Finished Mar 21 02:23:18 PM PDT 24
Peak memory 235724 kb
Host smart-a9cd39fe-c4b9-47fa-a8d5-f6d12e9ff6ef
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103448705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.1103448705
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.1457129682
Short name T828
Test name
Test status
Simulation time 26714462798 ps
CPU time 187.78 seconds
Started Mar 21 02:23:17 PM PDT 24
Finished Mar 21 02:26:25 PM PDT 24
Peak memory 249968 kb
Host smart-f8b5e432-13f3-4081-97e8-90599db941a0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457129682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stres
s_all.1457129682
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.1481798016
Short name T633
Test name
Test status
Simulation time 11131045802 ps
CPU time 24.69 seconds
Started Mar 21 02:23:17 PM PDT 24
Finished Mar 21 02:23:42 PM PDT 24
Peak memory 220276 kb
Host smart-2ed739e9-8477-4322-9603-85bed2d1f67a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1481798016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.1481798016
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.1419016704
Short name T522
Test name
Test status
Simulation time 632587648 ps
CPU time 4.13 seconds
Started Mar 21 02:23:18 PM PDT 24
Finished Mar 21 02:23:22 PM PDT 24
Peak memory 216396 kb
Host smart-6b573f9b-d9be-4fc6-b916-6f81cfacaedd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1419016704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.1419016704
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.2665620585
Short name T403
Test name
Test status
Simulation time 347280233 ps
CPU time 4.16 seconds
Started Mar 21 02:23:16 PM PDT 24
Finished Mar 21 02:23:21 PM PDT 24
Peak memory 215900 kb
Host smart-d9aee9b9-ebca-4808-b97d-5f63a297febc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2665620585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.2665620585
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.2689849467
Short name T498
Test name
Test status
Simulation time 284408297 ps
CPU time 0.92 seconds
Started Mar 21 02:23:19 PM PDT 24
Finished Mar 21 02:23:20 PM PDT 24
Peak memory 206768 kb
Host smart-327485ed-485b-4788-96d3-929c3a6e0805
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2689849467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.2689849467
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.1428060002
Short name T437
Test name
Test status
Simulation time 9603635466 ps
CPU time 11.33 seconds
Started Mar 21 02:23:21 PM PDT 24
Finished Mar 21 02:23:32 PM PDT 24
Peak memory 218188 kb
Host smart-0e78e443-3d52-4ea1-a09d-ef1e4f1efb15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1428060002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.1428060002
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.360153428
Short name T575
Test name
Test status
Simulation time 31359124 ps
CPU time 0.75 seconds
Started Mar 21 02:25:07 PM PDT 24
Finished Mar 21 02:25:08 PM PDT 24
Peak memory 205424 kb
Host smart-607721cc-fc0e-4c1b-aab5-adf77c94fe6c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360153428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.360153428
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.1565429054
Short name T64
Test name
Test status
Simulation time 322746074 ps
CPU time 3.1 seconds
Started Mar 21 02:25:18 PM PDT 24
Finished Mar 21 02:25:22 PM PDT 24
Peak memory 233852 kb
Host smart-dc1ea41d-96b4-4553-88ce-c43c02677eed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1565429054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.1565429054
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.2967789603
Short name T680
Test name
Test status
Simulation time 75077037 ps
CPU time 0.78 seconds
Started Mar 21 02:25:09 PM PDT 24
Finished Mar 21 02:25:10 PM PDT 24
Peak memory 206588 kb
Host smart-8a26b8e9-05ab-4113-8609-36b0ca4f0529
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2967789603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.2967789603
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.1772684978
Short name T410
Test name
Test status
Simulation time 160211860957 ps
CPU time 194.96 seconds
Started Mar 21 02:25:07 PM PDT 24
Finished Mar 21 02:28:22 PM PDT 24
Peak memory 257316 kb
Host smart-6e0ca6d4-c434-4814-81b6-9be6542a9ee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1772684978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.1772684978
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.1415483546
Short name T688
Test name
Test status
Simulation time 126362602281 ps
CPU time 315.34 seconds
Started Mar 21 02:25:09 PM PDT 24
Finished Mar 21 02:30:24 PM PDT 24
Peak memory 249392 kb
Host smart-728c201d-b56d-4195-90b5-86fb289c1855
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1415483546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.1415483546
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.1241278997
Short name T260
Test name
Test status
Simulation time 51341596637 ps
CPU time 370.38 seconds
Started Mar 21 02:25:09 PM PDT 24
Finished Mar 21 02:31:19 PM PDT 24
Peak memory 253440 kb
Host smart-0d2f2c09-4bc9-479d-9006-81a1b1fb992a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241278997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idl
e.1241278997
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.1563235714
Short name T512
Test name
Test status
Simulation time 8043943009 ps
CPU time 19.05 seconds
Started Mar 21 02:25:19 PM PDT 24
Finished Mar 21 02:25:38 PM PDT 24
Peak memory 234932 kb
Host smart-ff6008b7-fcdd-473b-815e-d98be7410962
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1563235714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.1563235714
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_intercept.3222139504
Short name T690
Test name
Test status
Simulation time 293225054 ps
CPU time 3.86 seconds
Started Mar 21 02:25:09 PM PDT 24
Finished Mar 21 02:25:13 PM PDT 24
Peak memory 234840 kb
Host smart-8ddf3e2e-065d-4559-8490-241df07278b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222139504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.3222139504
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.3347420623
Short name T242
Test name
Test status
Simulation time 3783348542 ps
CPU time 16.58 seconds
Started Mar 21 02:25:08 PM PDT 24
Finished Mar 21 02:25:24 PM PDT 24
Peak memory 217992 kb
Host smart-134589e4-3f66-4d39-aeeb-cf1891b17a2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3347420623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.3347420623
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.875863375
Short name T649
Test name
Test status
Simulation time 6226409646 ps
CPU time 11.45 seconds
Started Mar 21 02:25:09 PM PDT 24
Finished Mar 21 02:25:21 PM PDT 24
Peak memory 224700 kb
Host smart-d1ed9eaf-faa8-4d1a-88d4-e2e1a9affab4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=875863375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swap
.875863375
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.1303813611
Short name T478
Test name
Test status
Simulation time 14027564940 ps
CPU time 14.49 seconds
Started Mar 21 02:25:08 PM PDT 24
Finished Mar 21 02:25:22 PM PDT 24
Peak memory 233844 kb
Host smart-ada335a1-d7a9-45de-b9a0-a4e57265c3e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303813611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.1303813611
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.4225177765
Short name T473
Test name
Test status
Simulation time 157138168 ps
CPU time 3.83 seconds
Started Mar 21 02:25:07 PM PDT 24
Finished Mar 21 02:25:11 PM PDT 24
Peak memory 222408 kb
Host smart-296ea665-0f0a-468b-aa7b-fa9f190a4d83
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4225177765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dir
ect.4225177765
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.191015774
Short name T684
Test name
Test status
Simulation time 5179482964 ps
CPU time 30.44 seconds
Started Mar 21 02:25:09 PM PDT 24
Finished Mar 21 02:25:39 PM PDT 24
Peak memory 216616 kb
Host smart-60b0902b-009a-4182-a01c-d439e0e844c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=191015774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.191015774
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.4093269190
Short name T617
Test name
Test status
Simulation time 2449284063 ps
CPU time 13.61 seconds
Started Mar 21 02:25:08 PM PDT 24
Finished Mar 21 02:25:21 PM PDT 24
Peak memory 216508 kb
Host smart-e49cc7e0-4902-48c6-a58e-125cfb20b946
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4093269190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.4093269190
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.3257213464
Short name T86
Test name
Test status
Simulation time 164225859 ps
CPU time 1.89 seconds
Started Mar 21 02:25:09 PM PDT 24
Finished Mar 21 02:25:11 PM PDT 24
Peak memory 216452 kb
Host smart-7a07c97e-8ad0-4d95-9395-2a733a0a1701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3257213464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.3257213464
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.1852150465
Short name T779
Test name
Test status
Simulation time 79525424 ps
CPU time 0.92 seconds
Started Mar 21 02:25:19 PM PDT 24
Finished Mar 21 02:25:20 PM PDT 24
Peak memory 206776 kb
Host smart-1fcb79d9-6c6c-4224-bf02-ea0b97b7742b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852150465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.1852150465
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.50679149
Short name T357
Test name
Test status
Simulation time 94562159 ps
CPU time 2.28 seconds
Started Mar 21 02:25:15 PM PDT 24
Finished Mar 21 02:25:18 PM PDT 24
Peak memory 216484 kb
Host smart-ea2335e5-0194-46a8-93d1-99f4c16770be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50679149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.50679149
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.767635594
Short name T339
Test name
Test status
Simulation time 12869393 ps
CPU time 0.72 seconds
Started Mar 21 02:25:17 PM PDT 24
Finished Mar 21 02:25:18 PM PDT 24
Peak memory 205456 kb
Host smart-eb4c5fc4-0ac9-4fd7-9008-9903064d88cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767635594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.767635594
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.1259209718
Short name T909
Test name
Test status
Simulation time 2272693499 ps
CPU time 4.22 seconds
Started Mar 21 02:25:09 PM PDT 24
Finished Mar 21 02:25:13 PM PDT 24
Peak memory 234528 kb
Host smart-b2943348-8f24-4958-ab1a-4f02a9f1833c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1259209718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.1259209718
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.107072898
Short name T707
Test name
Test status
Simulation time 63416919 ps
CPU time 0.79 seconds
Started Mar 21 02:25:09 PM PDT 24
Finished Mar 21 02:25:09 PM PDT 24
Peak memory 206540 kb
Host smart-a3d91ab4-c41e-455f-b9ba-e031d3b3f461
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107072898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.107072898
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.1774328552
Short name T483
Test name
Test status
Simulation time 158559329825 ps
CPU time 137.88 seconds
Started Mar 21 02:25:19 PM PDT 24
Finished Mar 21 02:27:37 PM PDT 24
Peak memory 251824 kb
Host smart-fbcefe3d-c274-420b-971e-3d2372bf600b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1774328552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.1774328552
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.371375199
Short name T458
Test name
Test status
Simulation time 25551067131 ps
CPU time 75.13 seconds
Started Mar 21 02:25:10 PM PDT 24
Finished Mar 21 02:26:25 PM PDT 24
Peak memory 257588 kb
Host smart-c2e6711d-d0f3-48bb-b857-b37311859176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371375199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.371375199
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.3703314474
Short name T794
Test name
Test status
Simulation time 4997704546 ps
CPU time 64.43 seconds
Started Mar 21 02:25:17 PM PDT 24
Finished Mar 21 02:26:22 PM PDT 24
Peak memory 249368 kb
Host smart-94b47388-0db7-4c2e-bb07-9a07a7cf08c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703314474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idl
e.3703314474
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.1275401487
Short name T366
Test name
Test status
Simulation time 3949395500 ps
CPU time 8.41 seconds
Started Mar 21 02:25:21 PM PDT 24
Finished Mar 21 02:25:31 PM PDT 24
Peak memory 234628 kb
Host smart-8c52e571-7221-4890-a6ec-26616fb5e2b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275401487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.1275401487
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_intercept.3918870808
Short name T927
Test name
Test status
Simulation time 5617735147 ps
CPU time 10.73 seconds
Started Mar 21 02:25:18 PM PDT 24
Finished Mar 21 02:25:30 PM PDT 24
Peak memory 234704 kb
Host smart-83bffd54-3a43-44cf-951a-7a63f81efd9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918870808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.3918870808
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.839134303
Short name T389
Test name
Test status
Simulation time 1974415335 ps
CPU time 4.95 seconds
Started Mar 21 02:25:17 PM PDT 24
Finished Mar 21 02:25:22 PM PDT 24
Peak memory 227100 kb
Host smart-d3722a98-6219-43d6-9175-6395925792ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=839134303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.839134303
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.3157670654
Short name T930
Test name
Test status
Simulation time 1760835026 ps
CPU time 6.13 seconds
Started Mar 21 02:25:19 PM PDT 24
Finished Mar 21 02:25:26 PM PDT 24
Peak memory 233584 kb
Host smart-aa0d48f6-715e-4123-908c-ab410c3f9201
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157670654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swa
p.3157670654
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.2432729119
Short name T536
Test name
Test status
Simulation time 1577346668 ps
CPU time 4.02 seconds
Started Mar 21 02:25:10 PM PDT 24
Finished Mar 21 02:25:14 PM PDT 24
Peak memory 218052 kb
Host smart-91f613a9-5696-48fd-b01b-a844350dfa5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432729119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.2432729119
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.3486437274
Short name T841
Test name
Test status
Simulation time 120030914 ps
CPU time 3.78 seconds
Started Mar 21 02:25:09 PM PDT 24
Finished Mar 21 02:25:13 PM PDT 24
Peak memory 223092 kb
Host smart-fe25bb71-1776-4da9-afaf-f4cf05d3a00e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3486437274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir
ect.3486437274
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.2717381726
Short name T159
Test name
Test status
Simulation time 125268032892 ps
CPU time 206.79 seconds
Started Mar 21 02:25:17 PM PDT 24
Finished Mar 21 02:28:44 PM PDT 24
Peak memory 249392 kb
Host smart-ca37ef5c-bdd9-4f63-8179-80cdc50ccbb8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717381726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stre
ss_all.2717381726
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.3767644063
Short name T318
Test name
Test status
Simulation time 14846696066 ps
CPU time 20.02 seconds
Started Mar 21 02:25:16 PM PDT 24
Finished Mar 21 02:25:36 PM PDT 24
Peak memory 216456 kb
Host smart-897b9f25-6183-434f-93f6-a4c82bce9560
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3767644063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.3767644063
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.540355702
Short name T416
Test name
Test status
Simulation time 1829410968 ps
CPU time 6.38 seconds
Started Mar 21 02:25:17 PM PDT 24
Finished Mar 21 02:25:24 PM PDT 24
Peak memory 216440 kb
Host smart-41bf47d7-fb7b-46dd-9fc2-9ac529a13fef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540355702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.540355702
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.4005184998
Short name T833
Test name
Test status
Simulation time 62893774 ps
CPU time 1.31 seconds
Started Mar 21 02:25:07 PM PDT 24
Finished Mar 21 02:25:08 PM PDT 24
Peak memory 216512 kb
Host smart-f453de29-10d7-4c15-8993-53065373179c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4005184998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.4005184998
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.3661554019
Short name T464
Test name
Test status
Simulation time 178806155 ps
CPU time 0.81 seconds
Started Mar 21 02:25:18 PM PDT 24
Finished Mar 21 02:25:20 PM PDT 24
Peak memory 205768 kb
Host smart-97b40240-4948-49ac-9809-d475f33f113a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3661554019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.3661554019
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.2509291580
Short name T672
Test name
Test status
Simulation time 9668642457 ps
CPU time 18.87 seconds
Started Mar 21 02:25:08 PM PDT 24
Finished Mar 21 02:25:27 PM PDT 24
Peak memory 235980 kb
Host smart-d6269203-5896-43f9-b70a-7391b83185b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2509291580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.2509291580
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.1515832666
Short name T908
Test name
Test status
Simulation time 25047073 ps
CPU time 0.76 seconds
Started Mar 21 02:25:19 PM PDT 24
Finished Mar 21 02:25:21 PM PDT 24
Peak memory 205436 kb
Host smart-8cd2ad6b-e2d6-485f-96bc-5adc0d45d954
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515832666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.
1515832666
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.1312288603
Short name T269
Test name
Test status
Simulation time 146913921 ps
CPU time 2.9 seconds
Started Mar 21 02:25:19 PM PDT 24
Finished Mar 21 02:25:22 PM PDT 24
Peak memory 219684 kb
Host smart-03e0507d-a186-473e-8301-3018d7f789e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1312288603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.1312288603
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.3051957393
Short name T489
Test name
Test status
Simulation time 60345355 ps
CPU time 0.77 seconds
Started Mar 21 02:25:17 PM PDT 24
Finished Mar 21 02:25:18 PM PDT 24
Peak memory 205568 kb
Host smart-0950e3e8-6536-495a-bfce-a2d0e46afbc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051957393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.3051957393
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.2398209813
Short name T477
Test name
Test status
Simulation time 30403538038 ps
CPU time 150.7 seconds
Started Mar 21 02:25:21 PM PDT 24
Finished Mar 21 02:27:52 PM PDT 24
Peak memory 250392 kb
Host smart-7ff8791c-391a-44c5-9b47-dbde9fd7f3bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398209813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.2398209813
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.1614406064
Short name T310
Test name
Test status
Simulation time 4649419654 ps
CPU time 68.94 seconds
Started Mar 21 02:25:19 PM PDT 24
Finished Mar 21 02:26:29 PM PDT 24
Peak memory 249444 kb
Host smart-84da660e-fe07-440d-b2bf-92453130c468
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1614406064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.1614406064
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.4291622790
Short name T311
Test name
Test status
Simulation time 13949559656 ps
CPU time 32.35 seconds
Started Mar 21 02:25:22 PM PDT 24
Finished Mar 21 02:25:55 PM PDT 24
Peak memory 240524 kb
Host smart-9a514492-94ce-4b64-b5b3-4f598ef77a01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4291622790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.4291622790
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_intercept.3316774975
Short name T627
Test name
Test status
Simulation time 2831089451 ps
CPU time 10.75 seconds
Started Mar 21 02:25:19 PM PDT 24
Finished Mar 21 02:25:30 PM PDT 24
Peak memory 224732 kb
Host smart-628c2d6e-3e9c-44be-9e89-7f2c0f6820b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3316774975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.3316774975
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.1438120926
Short name T549
Test name
Test status
Simulation time 57427612211 ps
CPU time 19.63 seconds
Started Mar 21 02:25:18 PM PDT 24
Finished Mar 21 02:25:39 PM PDT 24
Peak memory 230572 kb
Host smart-4003303d-53b5-4396-95f1-fc937559a10b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1438120926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.1438120926
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.2717395375
Short name T507
Test name
Test status
Simulation time 4452534807 ps
CPU time 8.83 seconds
Started Mar 21 02:25:18 PM PDT 24
Finished Mar 21 02:25:28 PM PDT 24
Peak memory 241104 kb
Host smart-935709c6-be0a-4383-a178-503b44b37bce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717395375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swa
p.2717395375
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.3965664675
Short name T803
Test name
Test status
Simulation time 13937848218 ps
CPU time 16.28 seconds
Started Mar 21 02:25:20 PM PDT 24
Finished Mar 21 02:25:37 PM PDT 24
Peak memory 232940 kb
Host smart-986306d7-5e78-4323-ad34-5a8e170e5250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3965664675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.3965664675
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.2571184621
Short name T830
Test name
Test status
Simulation time 584985913 ps
CPU time 4.72 seconds
Started Mar 21 02:25:20 PM PDT 24
Finished Mar 21 02:25:26 PM PDT 24
Peak memory 222620 kb
Host smart-de7ac048-960b-48e9-b476-0d89021cdb6a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2571184621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dir
ect.2571184621
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.1054953745
Short name T160
Test name
Test status
Simulation time 850347903781 ps
CPU time 446.27 seconds
Started Mar 21 02:25:21 PM PDT 24
Finished Mar 21 02:32:48 PM PDT 24
Peak memory 272472 kb
Host smart-300e6410-63ce-493a-9846-d9b097096542
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054953745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stre
ss_all.1054953745
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.919646732
Short name T402
Test name
Test status
Simulation time 2951550463 ps
CPU time 27.43 seconds
Started Mar 21 02:25:18 PM PDT 24
Finished Mar 21 02:25:47 PM PDT 24
Peak memory 216520 kb
Host smart-c6e3f4d6-d8ed-4bf2-9ea7-9b0f2d54eb2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=919646732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.919646732
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.1915175190
Short name T685
Test name
Test status
Simulation time 3204285727 ps
CPU time 6.21 seconds
Started Mar 21 02:25:20 PM PDT 24
Finished Mar 21 02:25:27 PM PDT 24
Peak memory 216564 kb
Host smart-62469522-314d-4837-a45c-d59fd9a1995f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1915175190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.1915175190
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.52429749
Short name T369
Test name
Test status
Simulation time 203684601 ps
CPU time 1.6 seconds
Started Mar 21 02:25:21 PM PDT 24
Finished Mar 21 02:25:24 PM PDT 24
Peak memory 216452 kb
Host smart-814027a6-a7bd-401e-8d08-ebfcbd69d4b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52429749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.52429749
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.2728708914
Short name T786
Test name
Test status
Simulation time 51243202 ps
CPU time 0.81 seconds
Started Mar 21 02:25:19 PM PDT 24
Finished Mar 21 02:25:20 PM PDT 24
Peak memory 205760 kb
Host smart-bdf30d87-51e8-46b6-884b-85577e3fcbb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728708914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.2728708914
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.2805735799
Short name T442
Test name
Test status
Simulation time 209425203 ps
CPU time 2.72 seconds
Started Mar 21 02:25:20 PM PDT 24
Finished Mar 21 02:25:23 PM PDT 24
Peak memory 219080 kb
Host smart-2bd11fc6-755c-4d26-a7a8-fd17af37eedf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2805735799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.2805735799
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.2133137060
Short name T355
Test name
Test status
Simulation time 34599836 ps
CPU time 0.7 seconds
Started Mar 21 02:25:21 PM PDT 24
Finished Mar 21 02:25:23 PM PDT 24
Peak memory 205432 kb
Host smart-5212a195-0a9e-403b-b1d4-f31dbc98cb15
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133137060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.
2133137060
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.1878864930
Short name T510
Test name
Test status
Simulation time 767600724 ps
CPU time 4.01 seconds
Started Mar 21 02:25:22 PM PDT 24
Finished Mar 21 02:25:27 PM PDT 24
Peak memory 234848 kb
Host smart-2a993f7a-fc2f-4ef3-bbde-237f4a3b688d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1878864930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.1878864930
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.3079077794
Short name T396
Test name
Test status
Simulation time 15607857 ps
CPU time 0.79 seconds
Started Mar 21 02:25:19 PM PDT 24
Finished Mar 21 02:25:20 PM PDT 24
Peak memory 205476 kb
Host smart-1e9d1d2e-c280-4d9d-84cb-f656d5c184dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3079077794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.3079077794
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.2179968373
Short name T730
Test name
Test status
Simulation time 7077334074 ps
CPU time 71.33 seconds
Started Mar 21 02:25:22 PM PDT 24
Finished Mar 21 02:26:34 PM PDT 24
Peak memory 250272 kb
Host smart-60e8925c-4697-4c04-88c6-bba402ccf293
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179968373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.2179968373
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.3770581211
Short name T224
Test name
Test status
Simulation time 48446213570 ps
CPU time 148.89 seconds
Started Mar 21 02:25:23 PM PDT 24
Finished Mar 21 02:27:52 PM PDT 24
Peak memory 251616 kb
Host smart-7ebac154-e80c-47e1-b261-27a130b07d42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770581211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idl
e.3770581211
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.460997893
Short name T312
Test name
Test status
Simulation time 1372031070 ps
CPU time 18.65 seconds
Started Mar 21 02:25:21 PM PDT 24
Finished Mar 21 02:25:42 PM PDT 24
Peak memory 234044 kb
Host smart-9c199687-33fe-49b8-9119-e56be7cdc4e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=460997893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.460997893
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_intercept.2835282781
Short name T611
Test name
Test status
Simulation time 2637168661 ps
CPU time 9.86 seconds
Started Mar 21 02:25:22 PM PDT 24
Finished Mar 21 02:25:33 PM PDT 24
Peak memory 233688 kb
Host smart-ee69efca-797d-49e9-a97f-1a7dfd383084
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2835282781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.2835282781
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.4124852068
Short name T698
Test name
Test status
Simulation time 10817283096 ps
CPU time 16.91 seconds
Started Mar 21 02:25:21 PM PDT 24
Finished Mar 21 02:25:39 PM PDT 24
Peak memory 236552 kb
Host smart-789fe373-4b96-4703-a1bd-106490e8af18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124852068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.4124852068
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.2648538007
Short name T718
Test name
Test status
Simulation time 11747244641 ps
CPU time 12.2 seconds
Started Mar 21 02:25:21 PM PDT 24
Finished Mar 21 02:25:35 PM PDT 24
Peak memory 218156 kb
Host smart-4afd1946-209b-48e8-8a7d-413d65aeec90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2648538007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swa
p.2648538007
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.1708401242
Short name T776
Test name
Test status
Simulation time 2170013907 ps
CPU time 5.16 seconds
Started Mar 21 02:25:22 PM PDT 24
Finished Mar 21 02:25:28 PM PDT 24
Peak memory 224792 kb
Host smart-10fcdd03-71f1-4ea9-880b-0b22847726eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1708401242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.1708401242
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.155872467
Short name T921
Test name
Test status
Simulation time 3970904487 ps
CPU time 6.67 seconds
Started Mar 21 02:25:22 PM PDT 24
Finished Mar 21 02:25:30 PM PDT 24
Peak memory 223016 kb
Host smart-1dd3640f-968a-4168-af9a-22a637162957
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=155872467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dire
ct.155872467
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.3889226532
Short name T307
Test name
Test status
Simulation time 26648796978 ps
CPU time 163.97 seconds
Started Mar 21 02:25:21 PM PDT 24
Finished Mar 21 02:28:06 PM PDT 24
Peak memory 268320 kb
Host smart-b1c7e216-2c1f-43db-91ca-7fb132f9c508
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889226532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stre
ss_all.3889226532
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.1817277087
Short name T880
Test name
Test status
Simulation time 9618282769 ps
CPU time 21.58 seconds
Started Mar 21 02:25:23 PM PDT 24
Finished Mar 21 02:25:45 PM PDT 24
Peak memory 216620 kb
Host smart-aa1d5335-8c2a-4929-b8f1-8b0a8c75dbc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1817277087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.1817277087
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.1052932463
Short name T110
Test name
Test status
Simulation time 4999786163 ps
CPU time 16.43 seconds
Started Mar 21 02:25:20 PM PDT 24
Finished Mar 21 02:25:37 PM PDT 24
Peak memory 216524 kb
Host smart-e83113e1-bcc1-4404-8cbf-ab972c1f9250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1052932463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.1052932463
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.1746813880
Short name T831
Test name
Test status
Simulation time 18179418 ps
CPU time 0.77 seconds
Started Mar 21 02:25:20 PM PDT 24
Finished Mar 21 02:25:22 PM PDT 24
Peak memory 205764 kb
Host smart-2411f4d8-935a-4913-bdbf-fa66011b7cf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1746813880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.1746813880
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.1952122841
Short name T977
Test name
Test status
Simulation time 77885713 ps
CPU time 0.93 seconds
Started Mar 21 02:25:21 PM PDT 24
Finished Mar 21 02:25:22 PM PDT 24
Peak memory 206748 kb
Host smart-05cf8a22-d917-4a25-9219-cd36a247818a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1952122841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.1952122841
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.2447520557
Short name T40
Test name
Test status
Simulation time 17661903767 ps
CPU time 23.43 seconds
Started Mar 21 02:25:21 PM PDT 24
Finished Mar 21 02:25:46 PM PDT 24
Peak memory 230640 kb
Host smart-af07d7ea-306f-4c33-9c10-9222747e4bd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2447520557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.2447520557
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.3361588728
Short name T397
Test name
Test status
Simulation time 13209067 ps
CPU time 0.7 seconds
Started Mar 21 02:25:21 PM PDT 24
Finished Mar 21 02:25:24 PM PDT 24
Peak memory 205384 kb
Host smart-a1fc140c-438e-4fbb-a8b3-979c2de8244f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361588728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.
3361588728
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.31338979
Short name T10
Test name
Test status
Simulation time 1520123152 ps
CPU time 3.46 seconds
Started Mar 21 02:25:21 PM PDT 24
Finished Mar 21 02:25:25 PM PDT 24
Peak memory 234920 kb
Host smart-d7b79a85-eefd-443d-973a-33919208b2b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31338979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.31338979
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.484189239
Short name T799
Test name
Test status
Simulation time 62677866 ps
CPU time 0.78 seconds
Started Mar 21 02:25:21 PM PDT 24
Finished Mar 21 02:25:23 PM PDT 24
Peak memory 206640 kb
Host smart-807f62af-61a7-45d8-8749-630b934192a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=484189239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.484189239
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.1698201861
Short name T804
Test name
Test status
Simulation time 559575264 ps
CPU time 5.59 seconds
Started Mar 21 02:25:22 PM PDT 24
Finished Mar 21 02:25:29 PM PDT 24
Peak memory 224684 kb
Host smart-ea3c0759-0c85-47c1-8dd8-ce9d558d85f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698201861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.1698201861
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.586128325
Short name T851
Test name
Test status
Simulation time 94198729960 ps
CPU time 141.96 seconds
Started Mar 21 02:25:22 PM PDT 24
Finished Mar 21 02:27:45 PM PDT 24
Peak memory 249340 kb
Host smart-5d1a73db-d9fa-4b59-9a0e-29e3ec9bbf79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=586128325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.586128325
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.3826796365
Short name T747
Test name
Test status
Simulation time 56924390492 ps
CPU time 138.15 seconds
Started Mar 21 02:25:22 PM PDT 24
Finished Mar 21 02:27:41 PM PDT 24
Peak memory 249476 kb
Host smart-25ca2547-0baa-4fa1-ab58-c3ba702c6176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826796365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idl
e.3826796365
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.4207130017
Short name T399
Test name
Test status
Simulation time 7351176278 ps
CPU time 17.44 seconds
Started Mar 21 02:25:20 PM PDT 24
Finished Mar 21 02:25:38 PM PDT 24
Peak memory 238824 kb
Host smart-38640053-0ff9-47e3-85e4-7cdc2844990f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4207130017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.4207130017
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_intercept.4018797448
Short name T213
Test name
Test status
Simulation time 1646948142 ps
CPU time 4.21 seconds
Started Mar 21 02:25:20 PM PDT 24
Finished Mar 21 02:25:25 PM PDT 24
Peak memory 217704 kb
Host smart-6b8c2c3b-e3b0-456e-9d46-3a95ce094d17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018797448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.4018797448
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.2645823505
Short name T275
Test name
Test status
Simulation time 62671582849 ps
CPU time 29.11 seconds
Started Mar 21 02:25:23 PM PDT 24
Finished Mar 21 02:25:52 PM PDT 24
Peak memory 246968 kb
Host smart-22ddc613-6340-4587-b906-fa20d46083fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645823505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.2645823505
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.2938864227
Short name T774
Test name
Test status
Simulation time 15833203447 ps
CPU time 20.24 seconds
Started Mar 21 02:25:22 PM PDT 24
Finished Mar 21 02:25:43 PM PDT 24
Peak memory 232976 kb
Host smart-08a7efc9-6d7d-4d71-af00-2458f7a0e657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2938864227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swa
p.2938864227
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.4145681941
Short name T261
Test name
Test status
Simulation time 915887514 ps
CPU time 7.21 seconds
Started Mar 21 02:25:19 PM PDT 24
Finished Mar 21 02:25:27 PM PDT 24
Peak memory 233864 kb
Host smart-573ef683-dde5-4813-9654-a8eb823d0f1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4145681941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.4145681941
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.3275822731
Short name T340
Test name
Test status
Simulation time 449146084 ps
CPU time 3.99 seconds
Started Mar 21 02:25:20 PM PDT 24
Finished Mar 21 02:25:24 PM PDT 24
Peak memory 220096 kb
Host smart-b3ad3286-f8fb-4813-9def-82530c842d3d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3275822731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dir
ect.3275822731
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.1636876123
Short name T972
Test name
Test status
Simulation time 112485806471 ps
CPU time 769.68 seconds
Started Mar 21 02:25:23 PM PDT 24
Finished Mar 21 02:38:13 PM PDT 24
Peak memory 306144 kb
Host smart-aa6c6b82-fb2e-473a-823a-29abdf9fa12c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636876123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stre
ss_all.1636876123
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.1299920116
Short name T861
Test name
Test status
Simulation time 22842653251 ps
CPU time 43.36 seconds
Started Mar 21 02:25:22 PM PDT 24
Finished Mar 21 02:26:06 PM PDT 24
Peak memory 216568 kb
Host smart-c8ea939e-4c8f-4ff5-8db0-066ff2c66b39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1299920116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.1299920116
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.2812645059
Short name T845
Test name
Test status
Simulation time 3428951686 ps
CPU time 14.8 seconds
Started Mar 21 02:25:22 PM PDT 24
Finished Mar 21 02:25:38 PM PDT 24
Peak memory 216532 kb
Host smart-6ae1b081-de34-4119-b631-d7222a331da4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812645059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.2812645059
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.758284527
Short name T500
Test name
Test status
Simulation time 1053470064 ps
CPU time 2.52 seconds
Started Mar 21 02:25:22 PM PDT 24
Finished Mar 21 02:25:26 PM PDT 24
Peak memory 216524 kb
Host smart-66fdf4d0-f0ae-48c7-a078-c161ed548ba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=758284527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.758284527
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.2165308235
Short name T558
Test name
Test status
Simulation time 130789039 ps
CPU time 0.8 seconds
Started Mar 21 02:25:21 PM PDT 24
Finished Mar 21 02:25:23 PM PDT 24
Peak memory 205804 kb
Host smart-202ea95c-ab68-4409-9090-24c757823872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165308235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.2165308235
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.3763990755
Short name T65
Test name
Test status
Simulation time 13989795145 ps
CPU time 22.99 seconds
Started Mar 21 02:25:21 PM PDT 24
Finished Mar 21 02:25:46 PM PDT 24
Peak memory 239024 kb
Host smart-0fc0ca66-15d8-4338-a335-58f21ab2f987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3763990755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.3763990755
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.2166885631
Short name T919
Test name
Test status
Simulation time 15957910 ps
CPU time 0.73 seconds
Started Mar 21 02:25:33 PM PDT 24
Finished Mar 21 02:25:34 PM PDT 24
Peak memory 205380 kb
Host smart-5feb7d1d-284c-40bc-84f9-2b5f37fa53b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166885631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.
2166885631
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.4246591202
Short name T979
Test name
Test status
Simulation time 107812472 ps
CPU time 3.85 seconds
Started Mar 21 02:25:35 PM PDT 24
Finished Mar 21 02:25:39 PM PDT 24
Peak memory 233980 kb
Host smart-fbf0cc33-3f7e-4c95-a3a9-8e55f9fa251e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4246591202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.4246591202
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.595961672
Short name T970
Test name
Test status
Simulation time 16012847 ps
CPU time 0.78 seconds
Started Mar 21 02:25:32 PM PDT 24
Finished Mar 21 02:25:33 PM PDT 24
Peak memory 206632 kb
Host smart-540101fe-245b-459e-8431-de171bdd7219
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=595961672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.595961672
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.3852519331
Short name T272
Test name
Test status
Simulation time 17032212483 ps
CPU time 28.2 seconds
Started Mar 21 02:25:35 PM PDT 24
Finished Mar 21 02:26:04 PM PDT 24
Peak memory 238048 kb
Host smart-d0151de1-1ee1-4ac2-b52d-542b186c3eaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852519331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.3852519331
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.2470733087
Short name T292
Test name
Test status
Simulation time 137258121647 ps
CPU time 248.96 seconds
Started Mar 21 02:25:31 PM PDT 24
Finished Mar 21 02:29:40 PM PDT 24
Peak memory 236180 kb
Host smart-4e393c0d-df31-4a42-ba98-c7d3275d1a3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2470733087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.2470733087
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.35753169
Short name T587
Test name
Test status
Simulation time 21720782050 ps
CPU time 75.91 seconds
Started Mar 21 02:25:33 PM PDT 24
Finished Mar 21 02:26:49 PM PDT 24
Peak memory 252832 kb
Host smart-01e2b67d-cf5d-44f3-b4c6-da012899010e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35753169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idle.35753169
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_intercept.440075410
Short name T702
Test name
Test status
Simulation time 4705675130 ps
CPU time 4.36 seconds
Started Mar 21 02:25:35 PM PDT 24
Finished Mar 21 02:25:39 PM PDT 24
Peak memory 224764 kb
Host smart-5c51d52c-ad7c-47fc-ad4e-83b802b78aaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440075410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.440075410
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.1333736249
Short name T39
Test name
Test status
Simulation time 31337713545 ps
CPU time 26.8 seconds
Started Mar 21 02:25:34 PM PDT 24
Finished Mar 21 02:26:01 PM PDT 24
Peak memory 234132 kb
Host smart-19ec9a83-948d-4ca4-98c0-38efb1f10ef4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333736249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.1333736249
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.179068767
Short name T796
Test name
Test status
Simulation time 1209131670 ps
CPU time 4.14 seconds
Started Mar 21 02:25:35 PM PDT 24
Finished Mar 21 02:25:39 PM PDT 24
Peak memory 233248 kb
Host smart-ebee3d24-7b4f-4a64-bc05-38da49a05276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=179068767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swap
.179068767
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.3040423052
Short name T282
Test name
Test status
Simulation time 2332811820 ps
CPU time 9.64 seconds
Started Mar 21 02:25:31 PM PDT 24
Finished Mar 21 02:25:41 PM PDT 24
Peak memory 228592 kb
Host smart-4ec39e88-508a-4270-94dd-1597e08f6544
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3040423052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.3040423052
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.3369516104
Short name T140
Test name
Test status
Simulation time 2710281664 ps
CPU time 4.46 seconds
Started Mar 21 02:25:35 PM PDT 24
Finished Mar 21 02:25:40 PM PDT 24
Peak memory 220956 kb
Host smart-821cf544-d6c3-463f-a9e6-0c10793191a3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3369516104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dir
ect.3369516104
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.1251939836
Short name T63
Test name
Test status
Simulation time 206213436379 ps
CPU time 255.38 seconds
Started Mar 21 02:25:35 PM PDT 24
Finished Mar 21 02:29:50 PM PDT 24
Peak memory 274036 kb
Host smart-f74cb400-bb10-4172-a08d-e11394ae0e70
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251939836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stre
ss_all.1251939836
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.2817080197
Short name T417
Test name
Test status
Simulation time 31720211016 ps
CPU time 75.81 seconds
Started Mar 21 02:25:33 PM PDT 24
Finished Mar 21 02:26:49 PM PDT 24
Peak memory 216552 kb
Host smart-a1206fa5-39cd-4e77-83f8-e52fd2373735
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2817080197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.2817080197
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.3258875115
Short name T365
Test name
Test status
Simulation time 6569624697 ps
CPU time 20.13 seconds
Started Mar 21 02:25:34 PM PDT 24
Finished Mar 21 02:25:54 PM PDT 24
Peak memory 216576 kb
Host smart-8288de07-c55d-4df2-a5db-121618d04800
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258875115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.3258875115
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.1124280294
Short name T390
Test name
Test status
Simulation time 111783639 ps
CPU time 1.07 seconds
Started Mar 21 02:25:32 PM PDT 24
Finished Mar 21 02:25:33 PM PDT 24
Peak memory 207220 kb
Host smart-136ff8b7-92c0-49f5-a500-e0d4fd96b64a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1124280294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.1124280294
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.1260368368
Short name T334
Test name
Test status
Simulation time 76895577 ps
CPU time 0.9 seconds
Started Mar 21 02:25:32 PM PDT 24
Finished Mar 21 02:25:33 PM PDT 24
Peak memory 206088 kb
Host smart-e05c5e6c-8d73-4c92-b814-48c94ec38832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260368368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.1260368368
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.997923326
Short name T689
Test name
Test status
Simulation time 573428447 ps
CPU time 4.14 seconds
Started Mar 21 02:25:34 PM PDT 24
Finished Mar 21 02:25:39 PM PDT 24
Peak memory 218532 kb
Host smart-ec1a7011-21bc-428b-af0d-458c3021fe05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997923326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.997923326
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.742609320
Short name T451
Test name
Test status
Simulation time 37968455 ps
CPU time 0.72 seconds
Started Mar 21 02:25:34 PM PDT 24
Finished Mar 21 02:25:35 PM PDT 24
Peak memory 205412 kb
Host smart-3351aa95-085e-4f1b-b288-97ff81ca7894
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742609320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.742609320
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.1579214337
Short name T613
Test name
Test status
Simulation time 109022050 ps
CPU time 2.35 seconds
Started Mar 21 02:25:34 PM PDT 24
Finished Mar 21 02:25:36 PM PDT 24
Peak memory 216876 kb
Host smart-5b37bb82-2565-4063-bbdf-8abc45cc9679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1579214337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.1579214337
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.92303287
Short name T595
Test name
Test status
Simulation time 14651260 ps
CPU time 0.75 seconds
Started Mar 21 02:25:31 PM PDT 24
Finished Mar 21 02:25:32 PM PDT 24
Peak memory 205540 kb
Host smart-5e37630c-f744-4341-be6d-ed302442158f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92303287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.92303287
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.1645179904
Short name T287
Test name
Test status
Simulation time 264379349013 ps
CPU time 321.51 seconds
Started Mar 21 02:25:32 PM PDT 24
Finished Mar 21 02:30:54 PM PDT 24
Peak memory 271988 kb
Host smart-47f7519b-ba0d-4802-9f8a-dffcfbc872a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1645179904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.1645179904
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.3249765755
Short name T511
Test name
Test status
Simulation time 3547137881 ps
CPU time 40.05 seconds
Started Mar 21 02:25:31 PM PDT 24
Finished Mar 21 02:26:12 PM PDT 24
Peak memory 255276 kb
Host smart-572a7981-6f5b-4e7d-9d8d-38d8a44c3ba0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249765755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.3249765755
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.3083138483
Short name T758
Test name
Test status
Simulation time 34622397260 ps
CPU time 259 seconds
Started Mar 21 02:25:34 PM PDT 24
Finished Mar 21 02:29:53 PM PDT 24
Peak memory 249384 kb
Host smart-bce036c5-e1ad-401d-bd60-f6965b30683a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083138483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idl
e.3083138483
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.1891037662
Short name T245
Test name
Test status
Simulation time 1918006160 ps
CPU time 12.21 seconds
Started Mar 21 02:25:36 PM PDT 24
Finished Mar 21 02:25:48 PM PDT 24
Peak memory 234204 kb
Host smart-060329bf-8fd6-4cae-8e20-09fd32cfafcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891037662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.1891037662
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_intercept.1297133291
Short name T270
Test name
Test status
Simulation time 29738513380 ps
CPU time 9.46 seconds
Started Mar 21 02:25:33 PM PDT 24
Finished Mar 21 02:25:43 PM PDT 24
Peak memory 233972 kb
Host smart-588a3148-ae99-43d1-b9fc-7e0dc6e6ea95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1297133291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.1297133291
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.1574313941
Short name T814
Test name
Test status
Simulation time 1874022779 ps
CPU time 8.99 seconds
Started Mar 21 02:25:33 PM PDT 24
Finished Mar 21 02:25:42 PM PDT 24
Peak memory 238748 kb
Host smart-d1b6caa9-f1e8-4f70-b93d-e28abd53a796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574313941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.1574313941
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.2060264468
Short name T209
Test name
Test status
Simulation time 440486873 ps
CPU time 6.36 seconds
Started Mar 21 02:25:34 PM PDT 24
Finished Mar 21 02:25:41 PM PDT 24
Peak memory 228288 kb
Host smart-cd9799e4-e3ac-4441-afac-a304ee1704ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2060264468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swa
p.2060264468
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.2691049551
Short name T13
Test name
Test status
Simulation time 2828897417 ps
CPU time 14.45 seconds
Started Mar 21 02:25:32 PM PDT 24
Finished Mar 21 02:25:47 PM PDT 24
Peak memory 231756 kb
Host smart-04e68ef1-5e12-4649-b515-71acfa7cebce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2691049551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.2691049551
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.768380834
Short name T53
Test name
Test status
Simulation time 226808248 ps
CPU time 3.55 seconds
Started Mar 21 02:25:32 PM PDT 24
Finished Mar 21 02:25:36 PM PDT 24
Peak memory 222996 kb
Host smart-31f36cda-9849-4f83-a628-c851d56f5762
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=768380834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dire
ct.768380834
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.1919134902
Short name T969
Test name
Test status
Simulation time 2801501949 ps
CPU time 25.42 seconds
Started Mar 21 02:25:32 PM PDT 24
Finished Mar 21 02:25:58 PM PDT 24
Peak memory 216612 kb
Host smart-b15a6c30-a75a-46bc-8115-95e9605c3bb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919134902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.1919134902
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.3074420418
Short name T18
Test name
Test status
Simulation time 5041893413 ps
CPU time 5.04 seconds
Started Mar 21 02:25:36 PM PDT 24
Finished Mar 21 02:25:41 PM PDT 24
Peak memory 216584 kb
Host smart-ba00aa5b-d605-4e3a-ba4a-591970a68e71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3074420418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.3074420418
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.3042052746
Short name T883
Test name
Test status
Simulation time 102499821 ps
CPU time 2.06 seconds
Started Mar 21 02:25:33 PM PDT 24
Finished Mar 21 02:25:36 PM PDT 24
Peak memory 216524 kb
Host smart-32d48a38-9df9-425b-9307-bfdecf7d4c39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3042052746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.3042052746
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.1655248212
Short name T836
Test name
Test status
Simulation time 75328133 ps
CPU time 0.95 seconds
Started Mar 21 02:25:38 PM PDT 24
Finished Mar 21 02:25:39 PM PDT 24
Peak memory 205752 kb
Host smart-92d0ebb2-12d7-438d-88cc-8eea2d2cefbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1655248212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.1655248212
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.2162599352
Short name T424
Test name
Test status
Simulation time 1493248941 ps
CPU time 13.6 seconds
Started Mar 21 02:25:33 PM PDT 24
Finished Mar 21 02:25:47 PM PDT 24
Peak memory 249444 kb
Host smart-6be8f84b-8ccd-4346-8995-ab2b787b938a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2162599352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.2162599352
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.576063923
Short name T868
Test name
Test status
Simulation time 55042108 ps
CPU time 0.72 seconds
Started Mar 21 02:25:33 PM PDT 24
Finished Mar 21 02:25:34 PM PDT 24
Peak memory 205412 kb
Host smart-7bcb35cd-a0e3-441c-a3c8-4ab39daa5fa1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576063923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.576063923
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.1921066791
Short name T550
Test name
Test status
Simulation time 104596986 ps
CPU time 3.54 seconds
Started Mar 21 02:25:35 PM PDT 24
Finished Mar 21 02:25:39 PM PDT 24
Peak memory 233948 kb
Host smart-00464861-ac34-413f-b6e1-9be673a8d343
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1921066791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.1921066791
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.1409835176
Short name T168
Test name
Test status
Simulation time 18578717 ps
CPU time 0.76 seconds
Started Mar 21 02:25:33 PM PDT 24
Finished Mar 21 02:25:34 PM PDT 24
Peak memory 206896 kb
Host smart-84cfd952-e312-4715-9993-f3cc7c1cf00a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1409835176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.1409835176
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.161642234
Short name T656
Test name
Test status
Simulation time 5351304834 ps
CPU time 34.18 seconds
Started Mar 21 02:25:42 PM PDT 24
Finished Mar 21 02:26:16 PM PDT 24
Peak memory 253684 kb
Host smart-6bbbffea-2be4-4c24-baab-5dc387a90f15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161642234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.161642234
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.1886969194
Short name T301
Test name
Test status
Simulation time 6623711878 ps
CPU time 69.85 seconds
Started Mar 21 02:25:42 PM PDT 24
Finished Mar 21 02:26:52 PM PDT 24
Peak memory 251772 kb
Host smart-90c8f2f4-4fc8-4614-9197-5e5e28347754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886969194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.1886969194
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.1678446984
Short name T643
Test name
Test status
Simulation time 58825452254 ps
CPU time 349.64 seconds
Started Mar 21 02:25:39 PM PDT 24
Finished Mar 21 02:31:28 PM PDT 24
Peak memory 265136 kb
Host smart-48f50867-ecdf-4253-a8e4-c49358e1d196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1678446984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idl
e.1678446984
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.2275508610
Short name T504
Test name
Test status
Simulation time 21013556907 ps
CPU time 55.44 seconds
Started Mar 21 02:25:32 PM PDT 24
Finished Mar 21 02:26:27 PM PDT 24
Peak memory 241084 kb
Host smart-c6da1a12-f792-4013-ba5d-4d379cae466e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275508610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.2275508610
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_intercept.3593404823
Short name T604
Test name
Test status
Simulation time 562914624 ps
CPU time 3.33 seconds
Started Mar 21 02:25:36 PM PDT 24
Finished Mar 21 02:25:39 PM PDT 24
Peak memory 218876 kb
Host smart-af2a4305-b6d6-4136-9f5d-9bcf8b6e2dce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593404823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.3593404823
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.3391546891
Short name T985
Test name
Test status
Simulation time 17155981895 ps
CPU time 31.95 seconds
Started Mar 21 02:25:36 PM PDT 24
Finished Mar 21 02:26:08 PM PDT 24
Peak memory 248876 kb
Host smart-c2140245-4349-47e1-a12f-a0161c72d62d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3391546891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.3391546891
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.2588978554
Short name T295
Test name
Test status
Simulation time 6013565535 ps
CPU time 21.73 seconds
Started Mar 21 02:25:39 PM PDT 24
Finished Mar 21 02:26:01 PM PDT 24
Peak memory 233964 kb
Host smart-16d47396-a2ae-45a1-a7f3-96382d681db8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588978554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swa
p.2588978554
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.2598086944
Short name T694
Test name
Test status
Simulation time 19990065797 ps
CPU time 32.23 seconds
Started Mar 21 02:25:47 PM PDT 24
Finished Mar 21 02:26:20 PM PDT 24
Peak memory 239028 kb
Host smart-a68d751d-e158-4ed3-9456-1e2d68e28323
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598086944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.2598086944
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.2150188264
Short name T144
Test name
Test status
Simulation time 2344018695 ps
CPU time 5.88 seconds
Started Mar 21 02:25:39 PM PDT 24
Finished Mar 21 02:25:45 PM PDT 24
Peak memory 220192 kb
Host smart-c53e6a6e-f5a3-4a73-af38-4fdb039adf1b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2150188264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dir
ect.2150188264
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.1030508146
Short name T382
Test name
Test status
Simulation time 2247609007 ps
CPU time 31.2 seconds
Started Mar 21 02:25:33 PM PDT 24
Finished Mar 21 02:26:04 PM PDT 24
Peak memory 216592 kb
Host smart-d6741ac8-ae54-4d01-81de-6a65ef7dcfc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1030508146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.1030508146
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.3268442915
Short name T687
Test name
Test status
Simulation time 54338072199 ps
CPU time 26.75 seconds
Started Mar 21 02:25:33 PM PDT 24
Finished Mar 21 02:26:00 PM PDT 24
Peak memory 216620 kb
Host smart-839b32b0-cb0e-4360-bced-a69ca7e4b927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3268442915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.3268442915
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.4134840349
Short name T965
Test name
Test status
Simulation time 266928405 ps
CPU time 3.16 seconds
Started Mar 21 02:25:32 PM PDT 24
Finished Mar 21 02:25:36 PM PDT 24
Peak memory 216596 kb
Host smart-e5a58c6e-bd7b-4283-b941-68774f059ad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134840349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.4134840349
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.3974111268
Short name T626
Test name
Test status
Simulation time 52917224 ps
CPU time 0.88 seconds
Started Mar 21 02:25:33 PM PDT 24
Finished Mar 21 02:25:34 PM PDT 24
Peak memory 205788 kb
Host smart-2f9f363b-af9e-4155-87b2-534f69e3e291
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974111268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.3974111268
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.427820303
Short name T208
Test name
Test status
Simulation time 2684575262 ps
CPU time 9.99 seconds
Started Mar 21 02:25:31 PM PDT 24
Finished Mar 21 02:25:41 PM PDT 24
Peak memory 234128 kb
Host smart-52e97737-5877-4a79-9265-fe822a178162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427820303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.427820303
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.4125381631
Short name T73
Test name
Test status
Simulation time 17512734 ps
CPU time 0.72 seconds
Started Mar 21 02:25:48 PM PDT 24
Finished Mar 21 02:25:48 PM PDT 24
Peak memory 205396 kb
Host smart-1719b0b7-2649-4bc9-9672-20ce5d63b9bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125381631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.
4125381631
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.479467641
Short name T844
Test name
Test status
Simulation time 585649916 ps
CPU time 2.71 seconds
Started Mar 21 02:25:42 PM PDT 24
Finished Mar 21 02:25:45 PM PDT 24
Peak memory 233820 kb
Host smart-a3e7c222-8ff0-4990-ad60-96b1468c5311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479467641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.479467641
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.1700246753
Short name T637
Test name
Test status
Simulation time 14674483 ps
CPU time 0.84 seconds
Started Mar 21 02:25:32 PM PDT 24
Finished Mar 21 02:25:33 PM PDT 24
Peak memory 206548 kb
Host smart-f01ed0e5-d8b6-44f6-ac4f-0ee4b932c598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1700246753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.1700246753
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.1158461856
Short name T207
Test name
Test status
Simulation time 68939000503 ps
CPU time 194.41 seconds
Started Mar 21 02:25:41 PM PDT 24
Finished Mar 21 02:28:55 PM PDT 24
Peak memory 273260 kb
Host smart-48a87dea-61f1-4ec2-ac0d-d648c0406c26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1158461856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.1158461856
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.1279952807
Short name T934
Test name
Test status
Simulation time 47192818663 ps
CPU time 219.97 seconds
Started Mar 21 02:25:42 PM PDT 24
Finished Mar 21 02:29:22 PM PDT 24
Peak memory 256388 kb
Host smart-290c8f38-823c-4bf6-91a1-fe673216f23f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1279952807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idl
e.1279952807
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.2237825109
Short name T842
Test name
Test status
Simulation time 495647477 ps
CPU time 14.08 seconds
Started Mar 21 02:25:42 PM PDT 24
Finished Mar 21 02:25:56 PM PDT 24
Peak memory 240696 kb
Host smart-12716d02-d96b-43e0-adba-f4d1245983d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2237825109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.2237825109
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_intercept.922037428
Short name T706
Test name
Test status
Simulation time 10807193580 ps
CPU time 11.45 seconds
Started Mar 21 02:25:48 PM PDT 24
Finished Mar 21 02:25:59 PM PDT 24
Peak memory 233424 kb
Host smart-e4a02b14-ba43-43f7-9b31-005bea537958
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=922037428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.922037428
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.3371337552
Short name T497
Test name
Test status
Simulation time 2651426740 ps
CPU time 12.16 seconds
Started Mar 21 02:25:44 PM PDT 24
Finished Mar 21 02:25:56 PM PDT 24
Peak memory 232904 kb
Host smart-99b30073-779a-4558-aad2-2db1a6ea10b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3371337552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.3371337552
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.2357524384
Short name T640
Test name
Test status
Simulation time 3081587923 ps
CPU time 10.44 seconds
Started Mar 21 02:25:50 PM PDT 24
Finished Mar 21 02:26:01 PM PDT 24
Peak memory 231800 kb
Host smart-0a926a2d-a4c2-4119-8d6f-2ee4b16ff8b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357524384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swa
p.2357524384
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.4035381487
Short name T203
Test name
Test status
Simulation time 8887351150 ps
CPU time 19.77 seconds
Started Mar 21 02:25:45 PM PDT 24
Finished Mar 21 02:26:05 PM PDT 24
Peak memory 224836 kb
Host smart-0a34b7c6-734a-4f86-b322-b6527d500e65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4035381487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.4035381487
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.1434911717
Short name T577
Test name
Test status
Simulation time 271070398 ps
CPU time 3.44 seconds
Started Mar 21 02:25:45 PM PDT 24
Finished Mar 21 02:25:49 PM PDT 24
Peak memory 218696 kb
Host smart-18e819d2-903b-4d9c-8377-033bac0eb753
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1434911717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dir
ect.1434911717
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.1757460543
Short name T724
Test name
Test status
Simulation time 190068287 ps
CPU time 1.02 seconds
Started Mar 21 02:25:42 PM PDT 24
Finished Mar 21 02:25:43 PM PDT 24
Peak memory 207132 kb
Host smart-3895cbd6-6372-481a-a588-bbf2261b1bdb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757460543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stre
ss_all.1757460543
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.2011444233
Short name T433
Test name
Test status
Simulation time 427349942 ps
CPU time 3.83 seconds
Started Mar 21 02:25:45 PM PDT 24
Finished Mar 21 02:25:49 PM PDT 24
Peak memory 216448 kb
Host smart-05b12077-dc3a-4cd0-8504-63658eb26c6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2011444233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.2011444233
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.4132137602
Short name T426
Test name
Test status
Simulation time 1508436999 ps
CPU time 5.8 seconds
Started Mar 21 02:25:39 PM PDT 24
Finished Mar 21 02:25:45 PM PDT 24
Peak memory 216376 kb
Host smart-c1e1c105-296e-4e3b-a714-c60a42768649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132137602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.4132137602
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.3911249215
Short name T351
Test name
Test status
Simulation time 291849335 ps
CPU time 3.92 seconds
Started Mar 21 02:25:44 PM PDT 24
Finished Mar 21 02:25:48 PM PDT 24
Peak memory 218496 kb
Host smart-d4fda871-20b6-4d10-a800-24d66096aa38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911249215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.3911249215
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.376693488
Short name T582
Test name
Test status
Simulation time 117990794 ps
CPU time 0.74 seconds
Started Mar 21 02:25:42 PM PDT 24
Finished Mar 21 02:25:43 PM PDT 24
Peak memory 205792 kb
Host smart-ed88b1be-8fa0-4fe2-b13a-a24b1eb67f51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376693488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.376693488
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.3516291426
Short name T255
Test name
Test status
Simulation time 124097627898 ps
CPU time 28.33 seconds
Started Mar 21 02:25:44 PM PDT 24
Finished Mar 21 02:26:12 PM PDT 24
Peak memory 232944 kb
Host smart-0319444c-ad27-4d12-a9ac-214467b3dbb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3516291426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.3516291426
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.3163097275
Short name T666
Test name
Test status
Simulation time 17675476 ps
CPU time 0.74 seconds
Started Mar 21 02:26:00 PM PDT 24
Finished Mar 21 02:26:01 PM PDT 24
Peak memory 205688 kb
Host smart-c7897e92-524d-4ee7-99c8-8bf57a013269
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163097275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.
3163097275
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.2161932390
Short name T281
Test name
Test status
Simulation time 475892807 ps
CPU time 3.06 seconds
Started Mar 21 02:25:48 PM PDT 24
Finished Mar 21 02:25:51 PM PDT 24
Peak memory 234328 kb
Host smart-1881d0eb-a183-433e-87f0-ed7fab4a2da7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161932390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.2161932390
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.2046717839
Short name T361
Test name
Test status
Simulation time 14238800 ps
CPU time 0.77 seconds
Started Mar 21 02:25:46 PM PDT 24
Finished Mar 21 02:25:47 PM PDT 24
Peak memory 205872 kb
Host smart-f6cfc8ef-6314-4080-8ecb-5aff185b7988
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2046717839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.2046717839
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.3922371224
Short name T940
Test name
Test status
Simulation time 4205056935 ps
CPU time 58.83 seconds
Started Mar 21 02:25:43 PM PDT 24
Finished Mar 21 02:26:42 PM PDT 24
Peak memory 249380 kb
Host smart-5a2f4b99-a9eb-49f1-a0b1-9b378cad988d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3922371224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.3922371224
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.3496817964
Short name T379
Test name
Test status
Simulation time 152026248337 ps
CPU time 155.09 seconds
Started Mar 21 02:25:51 PM PDT 24
Finished Mar 21 02:28:26 PM PDT 24
Peak memory 249464 kb
Host smart-626fe372-cd8f-4083-97e8-a680928ff46d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3496817964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.3496817964
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.1851245802
Short name T232
Test name
Test status
Simulation time 7831298683 ps
CPU time 90.28 seconds
Started Mar 21 02:25:46 PM PDT 24
Finished Mar 21 02:27:16 PM PDT 24
Peak memory 257544 kb
Host smart-0d71c6db-9f4b-441c-ba4d-1b4855b0cebc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1851245802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idl
e.1851245802
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.38977017
Short name T432
Test name
Test status
Simulation time 57693227640 ps
CPU time 57.04 seconds
Started Mar 21 02:25:46 PM PDT 24
Finished Mar 21 02:26:43 PM PDT 24
Peak memory 240404 kb
Host smart-36af77dd-171e-4fba-b940-b9496671988f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38977017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.38977017
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_intercept.479744455
Short name T466
Test name
Test status
Simulation time 898533555 ps
CPU time 3.98 seconds
Started Mar 21 02:25:45 PM PDT 24
Finished Mar 21 02:25:49 PM PDT 24
Peak memory 216924 kb
Host smart-df5a3dae-3167-4a70-b7ac-92cbe9ff4e98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479744455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.479744455
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.4241635833
Short name T719
Test name
Test status
Simulation time 3065889017 ps
CPU time 11.79 seconds
Started Mar 21 02:25:42 PM PDT 24
Finished Mar 21 02:25:54 PM PDT 24
Peak memory 234308 kb
Host smart-b26c489c-1fdc-47ff-ab2a-42153baa13d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241635833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.4241635833
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.3311869492
Short name T48
Test name
Test status
Simulation time 21228125359 ps
CPU time 12.39 seconds
Started Mar 21 02:25:42 PM PDT 24
Finished Mar 21 02:25:55 PM PDT 24
Peak memory 228928 kb
Host smart-6b87efcf-6b00-4880-b5e2-f808474be4f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3311869492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swa
p.3311869492
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.2862217430
Short name T898
Test name
Test status
Simulation time 194808500 ps
CPU time 2.2 seconds
Started Mar 21 02:25:43 PM PDT 24
Finished Mar 21 02:25:46 PM PDT 24
Peak memory 217124 kb
Host smart-5963c71b-bc01-49f3-89a0-441c249be72e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2862217430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.2862217430
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.1833281548
Short name T145
Test name
Test status
Simulation time 1235237507 ps
CPU time 6.29 seconds
Started Mar 21 02:25:44 PM PDT 24
Finished Mar 21 02:25:50 PM PDT 24
Peak memory 218872 kb
Host smart-78638cd8-8cb7-4e44-987c-04b4b267c852
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1833281548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dir
ect.1833281548
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.1014288470
Short name T296
Test name
Test status
Simulation time 54683186377 ps
CPU time 460.98 seconds
Started Mar 21 02:26:00 PM PDT 24
Finished Mar 21 02:33:42 PM PDT 24
Peak memory 270552 kb
Host smart-244d1480-e571-4583-afe4-eabb8090ef36
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014288470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stre
ss_all.1014288470
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.2946693231
Short name T746
Test name
Test status
Simulation time 25287322184 ps
CPU time 46.69 seconds
Started Mar 21 02:25:47 PM PDT 24
Finished Mar 21 02:26:34 PM PDT 24
Peak memory 216528 kb
Host smart-e8416322-046a-46c0-bc49-2978f3a788da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2946693231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.2946693231
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.4014011182
Short name T341
Test name
Test status
Simulation time 169638551 ps
CPU time 1.68 seconds
Started Mar 21 02:25:43 PM PDT 24
Finished Mar 21 02:25:45 PM PDT 24
Peak memory 208024 kb
Host smart-cfa0be18-5382-4979-b0f6-474599dca459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014011182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.4014011182
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.170379409
Short name T866
Test name
Test status
Simulation time 266343331 ps
CPU time 1.59 seconds
Started Mar 21 02:25:45 PM PDT 24
Finished Mar 21 02:25:47 PM PDT 24
Peak memory 216428 kb
Host smart-a15097af-39c1-44eb-ba7d-3722a534ee79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=170379409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.170379409
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.1648489694
Short name T701
Test name
Test status
Simulation time 108799718 ps
CPU time 1.03 seconds
Started Mar 21 02:25:47 PM PDT 24
Finished Mar 21 02:25:48 PM PDT 24
Peak memory 205732 kb
Host smart-73f5e400-e45b-49b0-9eff-918fbfcbf04c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1648489694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.1648489694
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.2943390185
Short name T975
Test name
Test status
Simulation time 10045765816 ps
CPU time 31.54 seconds
Started Mar 21 02:25:44 PM PDT 24
Finished Mar 21 02:26:15 PM PDT 24
Peak memory 228576 kb
Host smart-0589d4e4-0641-4948-b8cb-3535994ab373
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2943390185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.2943390185
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.723668064
Short name T948
Test name
Test status
Simulation time 32713373 ps
CPU time 0.7 seconds
Started Mar 21 02:23:29 PM PDT 24
Finished Mar 21 02:23:31 PM PDT 24
Peak memory 204860 kb
Host smart-23331839-fae5-43f7-973f-32c7f4dde845
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723668064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.723668064
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.2822363142
Short name T565
Test name
Test status
Simulation time 40408484 ps
CPU time 2.71 seconds
Started Mar 21 02:23:16 PM PDT 24
Finished Mar 21 02:23:20 PM PDT 24
Peak memory 233504 kb
Host smart-23e9292c-fb4a-4e9f-9472-45e689f2c7fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822363142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.2822363142
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.3578704827
Short name T408
Test name
Test status
Simulation time 23241492 ps
CPU time 0.76 seconds
Started Mar 21 02:23:19 PM PDT 24
Finished Mar 21 02:23:20 PM PDT 24
Peak memory 205628 kb
Host smart-33fc5e27-0b6f-4eb9-99eb-d519eda9af9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3578704827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.3578704827
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.676642096
Short name T211
Test name
Test status
Simulation time 23707762531 ps
CPU time 133.74 seconds
Started Mar 21 02:23:16 PM PDT 24
Finished Mar 21 02:25:30 PM PDT 24
Peak memory 241180 kb
Host smart-6aa5d588-98b6-4d9b-bfb8-296146465415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=676642096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.676642096
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.823240114
Short name T217
Test name
Test status
Simulation time 90800834141 ps
CPU time 648.53 seconds
Started Mar 21 02:23:15 PM PDT 24
Finished Mar 21 02:34:04 PM PDT 24
Peak memory 257428 kb
Host smart-9feba7e6-85f0-422d-9c40-3c6c59c05da9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=823240114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.823240114
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.35185174
Short name T179
Test name
Test status
Simulation time 18232130608 ps
CPU time 126.78 seconds
Started Mar 21 02:23:17 PM PDT 24
Finished Mar 21 02:25:25 PM PDT 24
Peak memory 249412 kb
Host smart-1c8cf175-50d9-4157-86d8-cb20697ea74f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35185174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle.35185174
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.109314835
Short name T976
Test name
Test status
Simulation time 62654192670 ps
CPU time 31.88 seconds
Started Mar 21 02:23:17 PM PDT 24
Finished Mar 21 02:23:49 PM PDT 24
Peak memory 234872 kb
Host smart-d9ee1d97-4540-41f5-afd6-c5ec07b2be4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109314835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.109314835
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_intercept.2142850104
Short name T446
Test name
Test status
Simulation time 293200969 ps
CPU time 3.1 seconds
Started Mar 21 02:23:17 PM PDT 24
Finished Mar 21 02:23:20 PM PDT 24
Peak memory 224632 kb
Host smart-43e730f2-a3b2-468b-9ce9-6b29f8c761e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142850104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.2142850104
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.877274167
Short name T895
Test name
Test status
Simulation time 342746085 ps
CPU time 7.2 seconds
Started Mar 21 02:23:16 PM PDT 24
Finished Mar 21 02:23:23 PM PDT 24
Peak memory 232812 kb
Host smart-62028ba4-1ab7-408e-8a5e-9854e0a7e6c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=877274167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.877274167
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_mem_parity.2590365491
Short name T950
Test name
Test status
Simulation time 18036301 ps
CPU time 1.05 seconds
Started Mar 21 02:23:17 PM PDT 24
Finished Mar 21 02:23:19 PM PDT 24
Peak memory 216996 kb
Host smart-ca7c0258-d257-4c10-a350-95e8b442162c
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590365491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 3.spi_device_mem_parity.2590365491
Directory /workspace/3.spi_device_mem_parity/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.709048069
Short name T619
Test name
Test status
Simulation time 111609315 ps
CPU time 2.39 seconds
Started Mar 21 02:23:20 PM PDT 24
Finished Mar 21 02:23:23 PM PDT 24
Peak memory 218536 kb
Host smart-150e4be5-4451-4338-a8a7-5ad70c41f535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=709048069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap.
709048069
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.2761890938
Short name T592
Test name
Test status
Simulation time 1065015672 ps
CPU time 11.63 seconds
Started Mar 21 02:23:17 PM PDT 24
Finished Mar 21 02:23:29 PM PDT 24
Peak memory 222424 kb
Host smart-a9a12619-83ce-48ef-b95f-bdab8da2ea34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761890938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.2761890938
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_ram_cfg.3283562741
Short name T75
Test name
Test status
Simulation time 18968306 ps
CPU time 0.73 seconds
Started Mar 21 02:23:19 PM PDT 24
Finished Mar 21 02:23:20 PM PDT 24
Peak memory 216392 kb
Host smart-e4d39b1a-49cf-48fe-adc7-b52a975eba85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283562741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_ram_cfg.3283562741
Directory /workspace/3.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.3732372320
Short name T404
Test name
Test status
Simulation time 1497307947 ps
CPU time 4.61 seconds
Started Mar 21 02:23:18 PM PDT 24
Finished Mar 21 02:23:23 PM PDT 24
Peak memory 222380 kb
Host smart-bf1507ef-e564-4cec-b1a9-c9defcb8b5f3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3732372320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_dire
ct.3732372320
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.3746590996
Short name T81
Test name
Test status
Simulation time 124995596 ps
CPU time 0.97 seconds
Started Mar 21 02:23:17 PM PDT 24
Finished Mar 21 02:23:18 PM PDT 24
Peak memory 234640 kb
Host smart-723126b4-433a-4b05-bfa1-aae43b4f2847
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746590996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.3746590996
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.322119807
Short name T177
Test name
Test status
Simulation time 76214386159 ps
CPU time 337.92 seconds
Started Mar 21 02:23:19 PM PDT 24
Finished Mar 21 02:28:58 PM PDT 24
Peak memory 273328 kb
Host smart-9e74793e-e4b5-4bf9-b3e3-8f06dc65067b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322119807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stress
_all.322119807
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.2285301686
Short name T668
Test name
Test status
Simulation time 10916787175 ps
CPU time 70.62 seconds
Started Mar 21 02:23:17 PM PDT 24
Finished Mar 21 02:24:29 PM PDT 24
Peak memory 216612 kb
Host smart-edf9f9ce-1085-41b0-a616-032dc02ac724
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2285301686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.2285301686
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.1766677758
Short name T336
Test name
Test status
Simulation time 698328035 ps
CPU time 5.71 seconds
Started Mar 21 02:23:17 PM PDT 24
Finished Mar 21 02:23:23 PM PDT 24
Peak memory 216356 kb
Host smart-b600495b-dad4-4664-bc07-a94357d59f63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1766677758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.1766677758
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.3179051043
Short name T350
Test name
Test status
Simulation time 226158881 ps
CPU time 6.34 seconds
Started Mar 21 02:23:15 PM PDT 24
Finished Mar 21 02:23:22 PM PDT 24
Peak memory 216488 kb
Host smart-0b7a6d31-d9f4-4c53-b19f-0fa535ce1e9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179051043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.3179051043
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.77895918
Short name T899
Test name
Test status
Simulation time 102482674 ps
CPU time 0.95 seconds
Started Mar 21 02:23:17 PM PDT 24
Finished Mar 21 02:23:18 PM PDT 24
Peak memory 206784 kb
Host smart-77716d79-ba52-4b13-9083-a085af62748a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77895918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.77895918
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.3385796560
Short name T262
Test name
Test status
Simulation time 1658337039 ps
CPU time 11.2 seconds
Started Mar 21 02:23:19 PM PDT 24
Finished Mar 21 02:23:31 PM PDT 24
Peak memory 233644 kb
Host smart-c3dbef66-5686-4192-8ba3-dc4d8efa6899
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385796560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.3385796560
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.1358305772
Short name T499
Test name
Test status
Simulation time 27198531 ps
CPU time 0.74 seconds
Started Mar 21 02:25:59 PM PDT 24
Finished Mar 21 02:26:00 PM PDT 24
Peak memory 204848 kb
Host smart-8397434d-6008-4cce-a363-1f0d50feb271
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358305772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.
1358305772
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.3617952690
Short name T320
Test name
Test status
Simulation time 14530415230 ps
CPU time 14.96 seconds
Started Mar 21 02:26:00 PM PDT 24
Finished Mar 21 02:26:15 PM PDT 24
Peak memory 224732 kb
Host smart-3a5b5919-a060-4523-9d59-74b9339832eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3617952690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.3617952690
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.2290315056
Short name T664
Test name
Test status
Simulation time 47030142 ps
CPU time 0.78 seconds
Started Mar 21 02:25:57 PM PDT 24
Finished Mar 21 02:25:58 PM PDT 24
Peak memory 206580 kb
Host smart-fb935620-475e-47d4-a196-9e5c669044bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2290315056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.2290315056
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.731506784
Short name T360
Test name
Test status
Simulation time 39578141257 ps
CPU time 51.7 seconds
Started Mar 21 02:25:59 PM PDT 24
Finished Mar 21 02:26:51 PM PDT 24
Peak memory 257548 kb
Host smart-5665aee4-1b3f-452a-bd48-4b45c7fa34bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=731506784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.731506784
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.1006544712
Short name T251
Test name
Test status
Simulation time 20872996843 ps
CPU time 75.69 seconds
Started Mar 21 02:25:59 PM PDT 24
Finished Mar 21 02:27:14 PM PDT 24
Peak memory 221872 kb
Host smart-97c7b3e2-9c20-4187-beda-753d9da130d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1006544712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.1006544712
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.3479303127
Short name T134
Test name
Test status
Simulation time 62670410282 ps
CPU time 80.2 seconds
Started Mar 21 02:25:58 PM PDT 24
Finished Mar 21 02:27:19 PM PDT 24
Peak memory 237452 kb
Host smart-15532596-0fc1-468a-b711-6377708f7f32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479303127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.3479303127
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_intercept.39888201
Short name T742
Test name
Test status
Simulation time 933399210 ps
CPU time 4.93 seconds
Started Mar 21 02:25:59 PM PDT 24
Finished Mar 21 02:26:04 PM PDT 24
Peak memory 219812 kb
Host smart-f48a5c20-4c21-478f-9354-ff399d555505
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39888201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.39888201
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.3819029093
Short name T166
Test name
Test status
Simulation time 3275986035 ps
CPU time 5.4 seconds
Started Mar 21 02:25:58 PM PDT 24
Finished Mar 21 02:26:03 PM PDT 24
Peak memory 234112 kb
Host smart-e79ca2e1-196d-42e5-851c-b97790f1babb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819029093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.3819029093
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.4092319537
Short name T645
Test name
Test status
Simulation time 1834067142 ps
CPU time 5.59 seconds
Started Mar 21 02:26:00 PM PDT 24
Finished Mar 21 02:26:05 PM PDT 24
Peak memory 233340 kb
Host smart-c0024023-791f-4d4b-b426-1d186064beb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4092319537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swa
p.4092319537
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.854030158
Short name T960
Test name
Test status
Simulation time 302911612 ps
CPU time 5.85 seconds
Started Mar 21 02:26:03 PM PDT 24
Finished Mar 21 02:26:09 PM PDT 24
Peak memory 237500 kb
Host smart-7fe24d53-ecde-40a6-9cff-038ab269dd6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854030158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.854030158
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.607843784
Short name T143
Test name
Test status
Simulation time 1393249809 ps
CPU time 4.62 seconds
Started Mar 21 02:26:02 PM PDT 24
Finished Mar 21 02:26:06 PM PDT 24
Peak memory 220064 kb
Host smart-e8083120-db96-4a54-962e-000907fac7cc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=607843784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dire
ct.607843784
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.2966166832
Short name T773
Test name
Test status
Simulation time 4993905605 ps
CPU time 14.42 seconds
Started Mar 21 02:25:57 PM PDT 24
Finished Mar 21 02:26:12 PM PDT 24
Peak memory 216548 kb
Host smart-6d2ef00d-b2a6-4545-a341-04b1abb87361
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2966166832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.2966166832
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.1821766131
Short name T544
Test name
Test status
Simulation time 7476670868 ps
CPU time 26.12 seconds
Started Mar 21 02:25:59 PM PDT 24
Finished Mar 21 02:26:25 PM PDT 24
Peak memory 216604 kb
Host smart-2621438b-b7a7-439e-98a4-d2d13e978928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1821766131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.1821766131
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.788466019
Short name T711
Test name
Test status
Simulation time 242704345 ps
CPU time 1.63 seconds
Started Mar 21 02:25:58 PM PDT 24
Finished Mar 21 02:26:00 PM PDT 24
Peak memory 216404 kb
Host smart-7b570827-5e89-45ed-b312-18e979b662cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=788466019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.788466019
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.2842547061
Short name T769
Test name
Test status
Simulation time 71570017 ps
CPU time 0.86 seconds
Started Mar 21 02:25:58 PM PDT 24
Finished Mar 21 02:25:59 PM PDT 24
Peak memory 205788 kb
Host smart-788a4f1a-f928-4fe7-8b93-ce7947164a3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2842547061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.2842547061
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.517386558
Short name T182
Test name
Test status
Simulation time 2783752005 ps
CPU time 4.13 seconds
Started Mar 21 02:26:00 PM PDT 24
Finished Mar 21 02:26:04 PM PDT 24
Peak memory 218852 kb
Host smart-7069b989-2b99-4fd1-ad70-fac3e23d1c9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517386558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.517386558
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.4152874673
Short name T332
Test name
Test status
Simulation time 77705229 ps
CPU time 0.72 seconds
Started Mar 21 02:26:12 PM PDT 24
Finished Mar 21 02:26:13 PM PDT 24
Peak memory 205440 kb
Host smart-7f5d53b2-be74-4cc1-bde1-786f35ac8ffd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152874673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.
4152874673
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.3495530791
Short name T907
Test name
Test status
Simulation time 197182858 ps
CPU time 2.78 seconds
Started Mar 21 02:25:58 PM PDT 24
Finished Mar 21 02:26:01 PM PDT 24
Peak memory 233964 kb
Host smart-3528c808-2905-413f-9a50-ba6fcfc9183d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3495530791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.3495530791
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.3958934823
Short name T167
Test name
Test status
Simulation time 54512571 ps
CPU time 0.75 seconds
Started Mar 21 02:25:59 PM PDT 24
Finished Mar 21 02:26:00 PM PDT 24
Peak memory 206584 kb
Host smart-fc7de72d-ca43-4cc3-821e-c1b48f7e1a81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3958934823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.3958934823
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.4100281089
Short name T305
Test name
Test status
Simulation time 23411338512 ps
CPU time 106.45 seconds
Started Mar 21 02:26:03 PM PDT 24
Finished Mar 21 02:27:50 PM PDT 24
Peak memory 266712 kb
Host smart-13cd61aa-2880-4d4a-bb2f-38ef864c1f71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4100281089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.4100281089
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.202649133
Short name T30
Test name
Test status
Simulation time 130079041346 ps
CPU time 239.16 seconds
Started Mar 21 02:26:03 PM PDT 24
Finished Mar 21 02:30:02 PM PDT 24
Peak memory 270152 kb
Host smart-17390d44-8b89-441d-830a-d5708a675c9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202649133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idle
.202649133
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.1377220906
Short name T359
Test name
Test status
Simulation time 11225313783 ps
CPU time 61.2 seconds
Started Mar 21 02:26:02 PM PDT 24
Finished Mar 21 02:27:04 PM PDT 24
Peak memory 243884 kb
Host smart-f99a5c2d-ae0d-47ef-a48a-51ef6e683753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1377220906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.1377220906
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_intercept.785081081
Short name T537
Test name
Test status
Simulation time 9176530462 ps
CPU time 8.84 seconds
Started Mar 21 02:26:00 PM PDT 24
Finished Mar 21 02:26:09 PM PDT 24
Peak memory 234660 kb
Host smart-93c3eab9-cf28-4459-86cc-1380d1edc069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=785081081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.785081081
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.1335653700
Short name T650
Test name
Test status
Simulation time 4844262970 ps
CPU time 8.04 seconds
Started Mar 21 02:25:58 PM PDT 24
Finished Mar 21 02:26:06 PM PDT 24
Peak memory 224584 kb
Host smart-9a1086e6-028e-4a9b-b1aa-4d34f612e8d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335653700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.1335653700
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.1212048951
Short name T493
Test name
Test status
Simulation time 10889496923 ps
CPU time 28.73 seconds
Started Mar 21 02:25:59 PM PDT 24
Finished Mar 21 02:26:28 PM PDT 24
Peak memory 232952 kb
Host smart-e27a5278-d4c3-4123-a8d4-dffc74449bcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1212048951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swa
p.1212048951
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.4247956135
Short name T454
Test name
Test status
Simulation time 11850547837 ps
CPU time 34.81 seconds
Started Mar 21 02:26:02 PM PDT 24
Finished Mar 21 02:26:37 PM PDT 24
Peak memory 233540 kb
Host smart-1efd03eb-c860-41f6-8ede-4b31cf5b2900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4247956135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.4247956135
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.1078351626
Short name T542
Test name
Test status
Simulation time 273051316 ps
CPU time 3.15 seconds
Started Mar 21 02:25:59 PM PDT 24
Finished Mar 21 02:26:02 PM PDT 24
Peak memory 220052 kb
Host smart-3c9e5df6-24c0-44fb-b440-db50fa407a2c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1078351626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dir
ect.1078351626
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.754433343
Short name T681
Test name
Test status
Simulation time 326039488037 ps
CPU time 500.48 seconds
Started Mar 21 02:26:03 PM PDT 24
Finished Mar 21 02:34:24 PM PDT 24
Peak memory 297528 kb
Host smart-85f22f78-12a2-4d0c-99cb-a5809d5189cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754433343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stres
s_all.754433343
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.2894151852
Short name T67
Test name
Test status
Simulation time 10708262822 ps
CPU time 44.73 seconds
Started Mar 21 02:25:58 PM PDT 24
Finished Mar 21 02:26:43 PM PDT 24
Peak memory 220972 kb
Host smart-3893283c-638b-4d7b-8f00-d197bb33ec87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2894151852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.2894151852
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.2875837835
Short name T354
Test name
Test status
Simulation time 9052391997 ps
CPU time 13.42 seconds
Started Mar 21 02:25:58 PM PDT 24
Finished Mar 21 02:26:11 PM PDT 24
Peak memory 216612 kb
Host smart-58561de0-4c4f-4c44-a404-193cc472ef32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875837835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.2875837835
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.4236434287
Short name T628
Test name
Test status
Simulation time 842052231 ps
CPU time 3.33 seconds
Started Mar 21 02:26:00 PM PDT 24
Finished Mar 21 02:26:03 PM PDT 24
Peak memory 216384 kb
Host smart-15d0cd45-4ffc-4ff5-9986-5eeafe7e91cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4236434287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.4236434287
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.2667245083
Short name T375
Test name
Test status
Simulation time 66596614 ps
CPU time 0.92 seconds
Started Mar 21 02:25:59 PM PDT 24
Finished Mar 21 02:26:00 PM PDT 24
Peak memory 205684 kb
Host smart-371ce40f-d762-4062-ada5-ef6d381f328f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2667245083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.2667245083
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.1134892162
Short name T889
Test name
Test status
Simulation time 72509337 ps
CPU time 2.26 seconds
Started Mar 21 02:25:57 PM PDT 24
Finished Mar 21 02:25:59 PM PDT 24
Peak memory 218868 kb
Host smart-7d520225-acc0-42b2-a246-0804e3b6bbb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1134892162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.1134892162
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.449999475
Short name T566
Test name
Test status
Simulation time 11501526 ps
CPU time 0.73 seconds
Started Mar 21 02:26:11 PM PDT 24
Finished Mar 21 02:26:12 PM PDT 24
Peak memory 205732 kb
Host smart-ba1683c2-f477-4ef6-9fed-a88f521f9cbd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449999475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.449999475
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.1366676300
Short name T394
Test name
Test status
Simulation time 6525325403 ps
CPU time 4.83 seconds
Started Mar 21 02:26:10 PM PDT 24
Finished Mar 21 02:26:15 PM PDT 24
Peak memory 218968 kb
Host smart-bc9256a0-c855-41df-b767-63d56791052b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1366676300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.1366676300
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.3437308126
Short name T90
Test name
Test status
Simulation time 17771389 ps
CPU time 0.82 seconds
Started Mar 21 02:26:10 PM PDT 24
Finished Mar 21 02:26:11 PM PDT 24
Peak memory 206560 kb
Host smart-4508e54f-696f-40d7-b3c2-ad2b350760cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3437308126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.3437308126
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.729964107
Short name T289
Test name
Test status
Simulation time 33113433670 ps
CPU time 41.01 seconds
Started Mar 21 02:26:13 PM PDT 24
Finished Mar 21 02:26:54 PM PDT 24
Peak memory 241180 kb
Host smart-58b6677a-70c9-457b-86ee-f034c01c25a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=729964107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.729964107
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.2602235829
Short name T349
Test name
Test status
Simulation time 7656791707 ps
CPU time 47.45 seconds
Started Mar 21 02:26:14 PM PDT 24
Finished Mar 21 02:27:01 PM PDT 24
Peak memory 235524 kb
Host smart-86b736e6-0d98-4ac1-81f7-f7975a5e792e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2602235829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.2602235829
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.3885978901
Short name T62
Test name
Test status
Simulation time 5348428504 ps
CPU time 27.65 seconds
Started Mar 21 02:26:12 PM PDT 24
Finished Mar 21 02:26:40 PM PDT 24
Peak memory 238484 kb
Host smart-ec3fcc36-2c17-4f80-b90a-986f4146e7de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885978901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.3885978901
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_intercept.2248444324
Short name T703
Test name
Test status
Simulation time 995393832 ps
CPU time 5.51 seconds
Started Mar 21 02:26:11 PM PDT 24
Finished Mar 21 02:26:17 PM PDT 24
Peak memory 233548 kb
Host smart-9fb95c9d-8f18-4fa0-ac6f-a7e0e0a4cf63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2248444324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.2248444324
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.1120124863
Short name T324
Test name
Test status
Simulation time 553502757 ps
CPU time 7.8 seconds
Started Mar 21 02:26:11 PM PDT 24
Finished Mar 21 02:26:19 PM PDT 24
Peak memory 238812 kb
Host smart-5bd54e8f-df07-421e-83ef-117affeb6810
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1120124863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.1120124863
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.2875308787
Short name T932
Test name
Test status
Simulation time 9320381150 ps
CPU time 12.64 seconds
Started Mar 21 02:26:12 PM PDT 24
Finished Mar 21 02:26:25 PM PDT 24
Peak memory 220740 kb
Host smart-8cc5ad86-20e2-4528-9b28-f1cae4e28a28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875308787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swa
p.2875308787
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.832272133
Short name T88
Test name
Test status
Simulation time 456290269 ps
CPU time 4.86 seconds
Started Mar 21 02:26:13 PM PDT 24
Finished Mar 21 02:26:18 PM PDT 24
Peak memory 233560 kb
Host smart-1ba6d1e5-2abc-43c8-b1f9-76520a69dd9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=832272133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.832272133
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.3587856194
Short name T857
Test name
Test status
Simulation time 4814457720 ps
CPU time 6.65 seconds
Started Mar 21 02:26:11 PM PDT 24
Finished Mar 21 02:26:18 PM PDT 24
Peak memory 223168 kb
Host smart-e7d3d543-7d58-49f3-bf70-cead225251a4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3587856194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dir
ect.3587856194
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.1975154991
Short name T800
Test name
Test status
Simulation time 70172523342 ps
CPU time 570.41 seconds
Started Mar 21 02:26:13 PM PDT 24
Finished Mar 21 02:35:44 PM PDT 24
Peak memory 255924 kb
Host smart-a2e5bf31-79b4-463b-a758-8107f8d23c0d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975154991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stre
ss_all.1975154991
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.2333230945
Short name T317
Test name
Test status
Simulation time 8678970408 ps
CPU time 9.08 seconds
Started Mar 21 02:26:12 PM PDT 24
Finished Mar 21 02:26:21 PM PDT 24
Peak memory 216784 kb
Host smart-b7b1d25c-deaa-4e97-9bc4-eec16de92193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2333230945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.2333230945
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.274096166
Short name T663
Test name
Test status
Simulation time 562682208 ps
CPU time 3.33 seconds
Started Mar 21 02:26:14 PM PDT 24
Finished Mar 21 02:26:18 PM PDT 24
Peak memory 216456 kb
Host smart-c0d71ce0-65a0-4a98-8a63-93f89d74604d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274096166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.274096166
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.2381460480
Short name T750
Test name
Test status
Simulation time 507576061 ps
CPU time 4.2 seconds
Started Mar 21 02:26:12 PM PDT 24
Finished Mar 21 02:26:16 PM PDT 24
Peak memory 216428 kb
Host smart-287fa935-84ed-4689-8836-450cd0e306c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381460480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.2381460480
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.534900522
Short name T636
Test name
Test status
Simulation time 32154230 ps
CPU time 0.84 seconds
Started Mar 21 02:26:12 PM PDT 24
Finished Mar 21 02:26:13 PM PDT 24
Peak memory 205768 kb
Host smart-cb79792a-10a9-48bd-957b-385d58676723
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=534900522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.534900522
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.93943519
Short name T583
Test name
Test status
Simulation time 31874360643 ps
CPU time 23.47 seconds
Started Mar 21 02:26:11 PM PDT 24
Finished Mar 21 02:26:34 PM PDT 24
Peak memory 233048 kb
Host smart-fb4b6da0-369b-4812-b99f-80e47a569eed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93943519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.93943519
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.2248354030
Short name T890
Test name
Test status
Simulation time 15093407 ps
CPU time 0.74 seconds
Started Mar 21 02:26:14 PM PDT 24
Finished Mar 21 02:26:15 PM PDT 24
Peak memory 204900 kb
Host smart-e9f4f2db-6390-46ac-b3ab-1a6ac79fee60
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248354030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.
2248354030
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.1162706962
Short name T321
Test name
Test status
Simulation time 177316343 ps
CPU time 3.58 seconds
Started Mar 21 02:26:13 PM PDT 24
Finished Mar 21 02:26:17 PM PDT 24
Peak memory 218548 kb
Host smart-8f01b713-289c-4d1c-b66e-fc2393b3e07b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162706962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.1162706962
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.227450414
Short name T793
Test name
Test status
Simulation time 118048724 ps
CPU time 0.8 seconds
Started Mar 21 02:26:12 PM PDT 24
Finished Mar 21 02:26:13 PM PDT 24
Peak memory 206900 kb
Host smart-43a87b2b-f69f-482f-8874-c7c3fb50f55c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=227450414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.227450414
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.1528594210
Short name T735
Test name
Test status
Simulation time 202478775934 ps
CPU time 459.66 seconds
Started Mar 21 02:26:15 PM PDT 24
Finished Mar 21 02:33:55 PM PDT 24
Peak memory 255796 kb
Host smart-6d4b9bf3-66fd-456c-9e62-ee0633e095e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1528594210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.1528594210
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.1094509501
Short name T11
Test name
Test status
Simulation time 5553921846 ps
CPU time 68.47 seconds
Started Mar 21 02:26:16 PM PDT 24
Finished Mar 21 02:27:25 PM PDT 24
Peak memory 254128 kb
Host smart-52cf6915-22fd-4ccf-bea0-83d0d8049757
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1094509501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.1094509501
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.347969431
Short name T900
Test name
Test status
Simulation time 11545795388 ps
CPU time 76 seconds
Started Mar 21 02:26:15 PM PDT 24
Finished Mar 21 02:27:31 PM PDT 24
Peak memory 250376 kb
Host smart-fde79535-a3da-45b8-a305-67387f05218d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=347969431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idle
.347969431
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.1295650053
Short name T941
Test name
Test status
Simulation time 1436668811 ps
CPU time 16.53 seconds
Started Mar 21 02:26:14 PM PDT 24
Finished Mar 21 02:26:31 PM PDT 24
Peak memory 235036 kb
Host smart-b9caadb2-3a5f-41fb-a4c6-09581817ed37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1295650053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.1295650053
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_intercept.3922545802
Short name T963
Test name
Test status
Simulation time 18071479641 ps
CPU time 16.33 seconds
Started Mar 21 02:26:16 PM PDT 24
Finished Mar 21 02:26:33 PM PDT 24
Peak memory 233484 kb
Host smart-d0aad978-d375-4fc1-aac0-636be0b29be9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3922545802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.3922545802
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.55482582
Short name T50
Test name
Test status
Simulation time 32920734613 ps
CPU time 28.1 seconds
Started Mar 21 02:26:16 PM PDT 24
Finished Mar 21 02:26:45 PM PDT 24
Peak memory 240380 kb
Host smart-893a9844-1422-4aaf-9351-f6db5d533520
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55482582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.55482582
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.603322312
Short name T646
Test name
Test status
Simulation time 9334292961 ps
CPU time 26.5 seconds
Started Mar 21 02:26:14 PM PDT 24
Finished Mar 21 02:26:41 PM PDT 24
Peak memory 229672 kb
Host smart-3121db34-dacc-4e00-b69e-1bc023bf0a99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=603322312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swap
.603322312
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.3456870335
Short name T598
Test name
Test status
Simulation time 6106265696 ps
CPU time 18.77 seconds
Started Mar 21 02:26:12 PM PDT 24
Finished Mar 21 02:26:31 PM PDT 24
Peak memory 235240 kb
Host smart-500aae57-ba02-4c4f-b2e8-2edf7d75bc4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3456870335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.3456870335
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.3674906977
Short name T653
Test name
Test status
Simulation time 597759453 ps
CPU time 5.07 seconds
Started Mar 21 02:26:16 PM PDT 24
Finished Mar 21 02:26:21 PM PDT 24
Peak memory 220112 kb
Host smart-987ddd28-0267-4297-93e2-7931f9a8bcd4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3674906977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dir
ect.3674906977
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.432981171
Short name T158
Test name
Test status
Simulation time 33136305180 ps
CPU time 250.17 seconds
Started Mar 21 02:26:16 PM PDT 24
Finished Mar 21 02:30:27 PM PDT 24
Peak memory 254100 kb
Host smart-bfe1b44a-96cd-40ef-8133-a7d239af945b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432981171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stres
s_all.432981171
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.1122381445
Short name T316
Test name
Test status
Simulation time 13658359516 ps
CPU time 49.6 seconds
Started Mar 21 02:26:11 PM PDT 24
Finished Mar 21 02:27:01 PM PDT 24
Peak memory 216552 kb
Host smart-a1893f3e-1055-4ac4-a51e-8c4705917c2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1122381445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.1122381445
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.998616964
Short name T657
Test name
Test status
Simulation time 9369071774 ps
CPU time 27.63 seconds
Started Mar 21 02:26:12 PM PDT 24
Finished Mar 21 02:26:40 PM PDT 24
Peak memory 216608 kb
Host smart-0b22683c-2894-4bd4-963f-a5d6b7d1a087
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=998616964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.998616964
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.3544033921
Short name T670
Test name
Test status
Simulation time 228057928 ps
CPU time 1.54 seconds
Started Mar 21 02:26:13 PM PDT 24
Finished Mar 21 02:26:15 PM PDT 24
Peak memory 216532 kb
Host smart-16c5235b-b446-47fe-a589-4c7519f6d658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3544033921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.3544033921
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.4072643453
Short name T367
Test name
Test status
Simulation time 33790874 ps
CPU time 0.79 seconds
Started Mar 21 02:26:12 PM PDT 24
Finished Mar 21 02:26:12 PM PDT 24
Peak memory 205764 kb
Host smart-f8f1b45b-0269-47dc-b644-021ee3a63939
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4072643453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.4072643453
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.4102071727
Short name T215
Test name
Test status
Simulation time 10210926531 ps
CPU time 12.78 seconds
Started Mar 21 02:26:14 PM PDT 24
Finished Mar 21 02:26:27 PM PDT 24
Peak memory 241092 kb
Host smart-e7c9bf86-4350-4bdc-9a99-2c3bb73d509e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4102071727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.4102071727
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.4211209732
Short name T518
Test name
Test status
Simulation time 13965125 ps
CPU time 0.77 seconds
Started Mar 21 02:26:16 PM PDT 24
Finished Mar 21 02:26:17 PM PDT 24
Peak memory 205428 kb
Host smart-53bd4709-592b-4cd9-9e6c-c1c8b9bda448
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211209732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.
4211209732
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.2755365456
Short name T631
Test name
Test status
Simulation time 2555202284 ps
CPU time 3.25 seconds
Started Mar 21 02:26:16 PM PDT 24
Finished Mar 21 02:26:19 PM PDT 24
Peak memory 234852 kb
Host smart-2d8694e8-0138-419d-9d15-9c330b84ee77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755365456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.2755365456
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.1695195071
Short name T170
Test name
Test status
Simulation time 38921152 ps
CPU time 0.79 seconds
Started Mar 21 02:26:16 PM PDT 24
Finished Mar 21 02:26:17 PM PDT 24
Peak memory 206396 kb
Host smart-123e950e-8ace-4075-865d-ca1822da941c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1695195071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.1695195071
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.2433085894
Short name T391
Test name
Test status
Simulation time 193180002645 ps
CPU time 237.98 seconds
Started Mar 21 02:26:15 PM PDT 24
Finished Mar 21 02:30:13 PM PDT 24
Peak memory 265052 kb
Host smart-a224f161-1042-4a2e-8c37-d340e288bbc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2433085894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.2433085894
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.3647694646
Short name T49
Test name
Test status
Simulation time 51399772677 ps
CPU time 143.72 seconds
Started Mar 21 02:26:14 PM PDT 24
Finished Mar 21 02:28:38 PM PDT 24
Peak memory 251032 kb
Host smart-abe915f1-5f8e-4825-8b54-9f969c236b88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3647694646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.3647694646
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.3978257827
Short name T798
Test name
Test status
Simulation time 13643380759 ps
CPU time 68.42 seconds
Started Mar 21 02:26:13 PM PDT 24
Finished Mar 21 02:27:22 PM PDT 24
Peak memory 250968 kb
Host smart-6e0f93ac-aaf1-47b5-9864-8c6a133805a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978257827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idl
e.3978257827
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.3477528254
Short name T523
Test name
Test status
Simulation time 4677362906 ps
CPU time 17.75 seconds
Started Mar 21 02:26:13 PM PDT 24
Finished Mar 21 02:26:31 PM PDT 24
Peak memory 232820 kb
Host smart-caf03655-6a28-4a40-aee7-dde8cd0ff234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477528254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.3477528254
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_intercept.2959432245
Short name T983
Test name
Test status
Simulation time 10215600985 ps
CPU time 9.04 seconds
Started Mar 21 02:26:16 PM PDT 24
Finished Mar 21 02:26:25 PM PDT 24
Peak memory 224716 kb
Host smart-6134502f-f784-48a4-9092-119e0e333195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2959432245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.2959432245
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.1994085283
Short name T721
Test name
Test status
Simulation time 20475540047 ps
CPU time 15.57 seconds
Started Mar 21 02:26:18 PM PDT 24
Finished Mar 21 02:26:34 PM PDT 24
Peak memory 241116 kb
Host smart-dd4b4a09-b276-4311-9832-8a29cc7adcc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1994085283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.1994085283
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.2469138502
Short name T655
Test name
Test status
Simulation time 48345594913 ps
CPU time 67.33 seconds
Started Mar 21 02:26:15 PM PDT 24
Finished Mar 21 02:27:22 PM PDT 24
Peak memory 247836 kb
Host smart-c29bb014-7e9e-4398-b0ef-df5e782324ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2469138502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swa
p.2469138502
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.276830979
Short name T748
Test name
Test status
Simulation time 6780801840 ps
CPU time 15.97 seconds
Started Mar 21 02:26:15 PM PDT 24
Finished Mar 21 02:26:31 PM PDT 24
Peak memory 219728 kb
Host smart-8369f5ba-67c6-4aff-8039-340b16019390
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=276830979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.276830979
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.2634171704
Short name T430
Test name
Test status
Simulation time 140284997 ps
CPU time 3.23 seconds
Started Mar 21 02:26:14 PM PDT 24
Finished Mar 21 02:26:17 PM PDT 24
Peak memory 218796 kb
Host smart-06311718-9623-4bb5-8b1b-ab00f67601f4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2634171704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dir
ect.2634171704
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.3427268898
Short name T712
Test name
Test status
Simulation time 34235231448 ps
CPU time 77.38 seconds
Started Mar 21 02:26:15 PM PDT 24
Finished Mar 21 02:27:32 PM PDT 24
Peak memory 249428 kb
Host smart-afb6c503-e9da-4dd0-a6d4-e223a4e3ad22
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427268898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stre
ss_all.3427268898
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.3351377867
Short name T918
Test name
Test status
Simulation time 6433390280 ps
CPU time 23.55 seconds
Started Mar 21 02:26:13 PM PDT 24
Finished Mar 21 02:26:37 PM PDT 24
Peak memory 216744 kb
Host smart-c3468432-f05e-4eed-a447-b85fbb543240
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351377867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.3351377867
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.1111363672
Short name T755
Test name
Test status
Simulation time 1198464461 ps
CPU time 2.95 seconds
Started Mar 21 02:26:13 PM PDT 24
Finished Mar 21 02:26:16 PM PDT 24
Peak memory 216660 kb
Host smart-675ff676-7bf1-488b-8dd9-b7b4d86e613f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1111363672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.1111363672
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.767412123
Short name T964
Test name
Test status
Simulation time 204553466 ps
CPU time 7.52 seconds
Started Mar 21 02:26:14 PM PDT 24
Finished Mar 21 02:26:22 PM PDT 24
Peak memory 216412 kb
Host smart-f1ab4f4c-4076-408d-9142-60e2b4c39964
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767412123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.767412123
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.238694630
Short name T913
Test name
Test status
Simulation time 60200927 ps
CPU time 0.94 seconds
Started Mar 21 02:26:16 PM PDT 24
Finished Mar 21 02:26:17 PM PDT 24
Peak memory 206740 kb
Host smart-33a0a89d-fa5e-419a-9f92-e910b3f07920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=238694630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.238694630
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.942911337
Short name T488
Test name
Test status
Simulation time 3560522259 ps
CPU time 15.7 seconds
Started Mar 21 02:26:14 PM PDT 24
Finished Mar 21 02:26:29 PM PDT 24
Peak memory 232628 kb
Host smart-990c6313-aa85-4124-bb12-c505891e3d72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=942911337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.942911337
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.670307741
Short name T625
Test name
Test status
Simulation time 48836014 ps
CPU time 0.71 seconds
Started Mar 21 02:26:26 PM PDT 24
Finished Mar 21 02:26:26 PM PDT 24
Peak memory 205756 kb
Host smart-cd9ffff2-978c-410c-8d3b-3f9c18973bad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670307741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.670307741
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.4124947072
Short name T347
Test name
Test status
Simulation time 217115685 ps
CPU time 2.44 seconds
Started Mar 21 02:26:26 PM PDT 24
Finished Mar 21 02:26:29 PM PDT 24
Peak memory 218896 kb
Host smart-80798c21-b673-4b10-a80b-bd49cabf2da2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124947072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.4124947072
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.2801937627
Short name T70
Test name
Test status
Simulation time 38784579 ps
CPU time 0.83 seconds
Started Mar 21 02:26:18 PM PDT 24
Finished Mar 21 02:26:19 PM PDT 24
Peak memory 206636 kb
Host smart-0a063536-1aa9-4bed-82c5-1987e545dec8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2801937627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.2801937627
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.4166606200
Short name T22
Test name
Test status
Simulation time 1785930090 ps
CPU time 25.78 seconds
Started Mar 21 02:26:25 PM PDT 24
Finished Mar 21 02:26:51 PM PDT 24
Peak memory 240396 kb
Host smart-9854dd4d-8f38-4e66-8572-9d7aeafd493a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4166606200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.4166606200
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.3205408820
Short name T659
Test name
Test status
Simulation time 32633460131 ps
CPU time 123.66 seconds
Started Mar 21 02:26:28 PM PDT 24
Finished Mar 21 02:28:32 PM PDT 24
Peak memory 237672 kb
Host smart-ec3ac3d9-c820-45a2-9709-10c642a26ea3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3205408820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.3205408820
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.2172482054
Short name T978
Test name
Test status
Simulation time 16222601335 ps
CPU time 52.84 seconds
Started Mar 21 02:26:27 PM PDT 24
Finished Mar 21 02:27:20 PM PDT 24
Peak memory 237956 kb
Host smart-8bf29624-526c-4366-a3ba-89292d2087ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172482054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idl
e.2172482054
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.2402438346
Short name T491
Test name
Test status
Simulation time 10806224522 ps
CPU time 56.63 seconds
Started Mar 21 02:26:27 PM PDT 24
Finished Mar 21 02:27:24 PM PDT 24
Peak memory 239328 kb
Host smart-fead41eb-24db-4217-baa1-7ec02ea1a943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2402438346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.2402438346
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_intercept.520307522
Short name T171
Test name
Test status
Simulation time 9623479852 ps
CPU time 7.03 seconds
Started Mar 21 02:26:12 PM PDT 24
Finished Mar 21 02:26:19 PM PDT 24
Peak memory 224792 kb
Host smart-df888eaa-ca13-4fe6-921f-65234dd26a4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520307522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.520307522
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.3987744790
Short name T393
Test name
Test status
Simulation time 66014433 ps
CPU time 2.57 seconds
Started Mar 21 02:26:15 PM PDT 24
Finished Mar 21 02:26:17 PM PDT 24
Peak memory 224668 kb
Host smart-07dc0de5-17f5-49e7-ba3c-84daf1c41493
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3987744790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.3987744790
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.709538763
Short name T635
Test name
Test status
Simulation time 852165437 ps
CPU time 2.89 seconds
Started Mar 21 02:26:15 PM PDT 24
Finished Mar 21 02:26:18 PM PDT 24
Peak memory 224684 kb
Host smart-d11a4034-d927-4d1b-b7ff-37f56b92bdd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=709538763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swap
.709538763
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.42036770
Short name T951
Test name
Test status
Simulation time 45801424992 ps
CPU time 14.35 seconds
Started Mar 21 02:26:16 PM PDT 24
Finished Mar 21 02:26:31 PM PDT 24
Peak memory 230764 kb
Host smart-3bb8de47-b935-4680-aa8a-008d28acc4a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42036770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.42036770
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.303030010
Short name T431
Test name
Test status
Simulation time 3117378605 ps
CPU time 6.67 seconds
Started Mar 21 02:26:27 PM PDT 24
Finished Mar 21 02:26:33 PM PDT 24
Peak memory 220164 kb
Host smart-41a3d1ea-4894-4ee4-86ab-47162f6a48c6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=303030010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dire
ct.303030010
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.564949416
Short name T202
Test name
Test status
Simulation time 43540272663 ps
CPU time 80.67 seconds
Started Mar 21 02:26:28 PM PDT 24
Finished Mar 21 02:27:49 PM PDT 24
Peak memory 255020 kb
Host smart-a2da9e45-0e02-4460-a54c-0461bb9e30fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564949416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stres
s_all.564949416
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.1263065681
Short name T54
Test name
Test status
Simulation time 944672702 ps
CPU time 5.86 seconds
Started Mar 21 02:26:15 PM PDT 24
Finished Mar 21 02:26:21 PM PDT 24
Peak memory 216436 kb
Host smart-28496617-a29e-42af-9046-e269ebafc8a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1263065681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.1263065681
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.2217520994
Short name T465
Test name
Test status
Simulation time 3577922771 ps
CPU time 15.34 seconds
Started Mar 21 02:26:16 PM PDT 24
Finished Mar 21 02:26:31 PM PDT 24
Peak memory 216596 kb
Host smart-59fdbc1f-afbd-4ccd-acd5-2ad91e43457b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2217520994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.2217520994
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.1603837672
Short name T988
Test name
Test status
Simulation time 23501237 ps
CPU time 1.33 seconds
Started Mar 21 02:26:16 PM PDT 24
Finished Mar 21 02:26:18 PM PDT 24
Peak memory 217772 kb
Host smart-b492fac5-fd78-4f93-a05b-e14fdf791838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603837672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.1603837672
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.623412415
Short name T871
Test name
Test status
Simulation time 55324034 ps
CPU time 0.71 seconds
Started Mar 21 02:26:17 PM PDT 24
Finished Mar 21 02:26:17 PM PDT 24
Peak memory 205776 kb
Host smart-1550f454-efcb-412e-8073-f688a9437197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=623412415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.623412415
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.411804777
Short name T775
Test name
Test status
Simulation time 117346566 ps
CPU time 2.21 seconds
Started Mar 21 02:26:25 PM PDT 24
Finished Mar 21 02:26:28 PM PDT 24
Peak memory 219016 kb
Host smart-e51800c6-e94d-435d-b95b-9f862329afec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411804777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.411804777
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.1420621942
Short name T966
Test name
Test status
Simulation time 47472696 ps
CPU time 0.69 seconds
Started Mar 21 02:26:26 PM PDT 24
Finished Mar 21 02:26:27 PM PDT 24
Peak memory 204864 kb
Host smart-5d99437a-5c15-4eb4-b6e7-8d4aa098e6b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420621942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.
1420621942
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.42601716
Short name T268
Test name
Test status
Simulation time 61728728 ps
CPU time 2.55 seconds
Started Mar 21 02:26:26 PM PDT 24
Finished Mar 21 02:26:28 PM PDT 24
Peak memory 218696 kb
Host smart-c2d122fe-36cd-4fad-8581-7aab3638d897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42601716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.42601716
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.3817838062
Short name T757
Test name
Test status
Simulation time 28777536 ps
CPU time 0.78 seconds
Started Mar 21 02:26:28 PM PDT 24
Finished Mar 21 02:26:29 PM PDT 24
Peak memory 206612 kb
Host smart-491288b8-6c55-402a-910a-a1734b05bf0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3817838062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.3817838062
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.3030318183
Short name T760
Test name
Test status
Simulation time 8361566226 ps
CPU time 8.42 seconds
Started Mar 21 02:26:24 PM PDT 24
Finished Mar 21 02:26:33 PM PDT 24
Peak memory 235148 kb
Host smart-271b121b-28b2-4b1e-8c6b-3b496b43944f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3030318183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.3030318183
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.452890299
Short name T58
Test name
Test status
Simulation time 28621699328 ps
CPU time 185.22 seconds
Started Mar 21 02:26:25 PM PDT 24
Finished Mar 21 02:29:31 PM PDT 24
Peak memory 257268 kb
Host smart-9d4e209a-ab39-466f-a0a2-8c0f8dc3f643
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452890299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.452890299
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.1372485454
Short name T204
Test name
Test status
Simulation time 7145242573 ps
CPU time 47.07 seconds
Started Mar 21 02:26:26 PM PDT 24
Finished Mar 21 02:27:13 PM PDT 24
Peak memory 249360 kb
Host smart-2fe1f74d-2558-4ff1-8338-44d101dbb989
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1372485454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idl
e.1372485454
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.636727107
Short name T622
Test name
Test status
Simulation time 2986243778 ps
CPU time 15.65 seconds
Started Mar 21 02:26:28 PM PDT 24
Finished Mar 21 02:26:43 PM PDT 24
Peak memory 257280 kb
Host smart-8d8b41f0-72ef-447e-bd45-670b55082063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=636727107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.636727107
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_intercept.2076204212
Short name T91
Test name
Test status
Simulation time 8280540926 ps
CPU time 13.08 seconds
Started Mar 21 02:26:30 PM PDT 24
Finished Mar 21 02:26:43 PM PDT 24
Peak memory 233452 kb
Host smart-e2bd8bea-b7f3-4bae-b635-fd5f20fdde90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2076204212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.2076204212
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.2930634938
Short name T226
Test name
Test status
Simulation time 2996880794 ps
CPU time 10.76 seconds
Started Mar 21 02:26:28 PM PDT 24
Finished Mar 21 02:26:39 PM PDT 24
Peak memory 232952 kb
Host smart-feccee96-1a3f-4a31-b224-a48405da76bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2930634938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.2930634938
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.2632020514
Short name T308
Test name
Test status
Simulation time 66215106871 ps
CPU time 12.52 seconds
Started Mar 21 02:26:28 PM PDT 24
Finished Mar 21 02:26:41 PM PDT 24
Peak memory 228968 kb
Host smart-d3c6444e-8dc0-41dc-bc7e-850912f2eb30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2632020514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swa
p.2632020514
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.2013294591
Short name T234
Test name
Test status
Simulation time 13882276626 ps
CPU time 12.79 seconds
Started Mar 21 02:26:26 PM PDT 24
Finished Mar 21 02:26:39 PM PDT 24
Peak memory 218120 kb
Host smart-0763ad95-da93-4f0d-b0c9-7f1eeea491ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2013294591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.2013294591
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.3947848211
Short name T865
Test name
Test status
Simulation time 1361509070 ps
CPU time 5.51 seconds
Started Mar 21 02:26:30 PM PDT 24
Finished Mar 21 02:26:36 PM PDT 24
Peak memory 220092 kb
Host smart-19bceec9-c615-487a-bab5-1a12de890301
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3947848211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dir
ect.3947848211
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.459276972
Short name T751
Test name
Test status
Simulation time 3180263578 ps
CPU time 22.96 seconds
Started Mar 21 02:26:26 PM PDT 24
Finished Mar 21 02:26:49 PM PDT 24
Peak memory 216640 kb
Host smart-94b66df1-d9e0-4696-8ee1-f891ad547abf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459276972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.459276972
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.3103858422
Short name T607
Test name
Test status
Simulation time 2243104028 ps
CPU time 7.16 seconds
Started Mar 21 02:26:29 PM PDT 24
Finished Mar 21 02:26:37 PM PDT 24
Peak memory 216536 kb
Host smart-c79061cd-dff0-4569-9b6c-cc3cc6bc944d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3103858422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.3103858422
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.1706886006
Short name T183
Test name
Test status
Simulation time 236055495 ps
CPU time 10.82 seconds
Started Mar 21 02:26:24 PM PDT 24
Finished Mar 21 02:26:35 PM PDT 24
Peak memory 216592 kb
Host smart-43b95147-1b68-49b0-8336-6b2f3b806c09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1706886006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.1706886006
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.263076677
Short name T606
Test name
Test status
Simulation time 408529602 ps
CPU time 0.97 seconds
Started Mar 21 02:26:24 PM PDT 24
Finished Mar 21 02:26:25 PM PDT 24
Peak memory 205748 kb
Host smart-bcb97715-eae5-4cfc-a321-ac0acd9f4fa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=263076677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.263076677
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.2355463430
Short name T527
Test name
Test status
Simulation time 3128048493 ps
CPU time 9.97 seconds
Started Mar 21 02:26:25 PM PDT 24
Finished Mar 21 02:26:36 PM PDT 24
Peak memory 233556 kb
Host smart-989b9a37-e2cf-44b3-af7e-e621ef9f346e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355463430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.2355463430
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.1527814303
Short name T529
Test name
Test status
Simulation time 13676928 ps
CPU time 0.74 seconds
Started Mar 21 02:26:28 PM PDT 24
Finished Mar 21 02:26:29 PM PDT 24
Peak memory 205408 kb
Host smart-8fe1cfc3-c68d-44ed-a958-ce4fdb7b8247
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527814303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.
1527814303
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.2663267099
Short name T815
Test name
Test status
Simulation time 147684674 ps
CPU time 2.14 seconds
Started Mar 21 02:26:31 PM PDT 24
Finished Mar 21 02:26:33 PM PDT 24
Peak memory 218424 kb
Host smart-221f3a0f-9190-495e-b454-83ed3fa6753f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2663267099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.2663267099
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.497902923
Short name T567
Test name
Test status
Simulation time 14545608 ps
CPU time 0.81 seconds
Started Mar 21 02:26:25 PM PDT 24
Finished Mar 21 02:26:26 PM PDT 24
Peak memory 206588 kb
Host smart-8f5bdbad-0e6a-4120-beee-676f2ac67eff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497902923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.497902923
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.3710322255
Short name T94
Test name
Test status
Simulation time 8349141877 ps
CPU time 68.25 seconds
Started Mar 21 02:26:27 PM PDT 24
Finished Mar 21 02:27:36 PM PDT 24
Peak memory 266720 kb
Host smart-beb4372d-8120-47cf-a048-2dce5f88d0ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3710322255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.3710322255
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.3691721968
Short name T601
Test name
Test status
Simulation time 89114318887 ps
CPU time 199.64 seconds
Started Mar 21 02:26:30 PM PDT 24
Finished Mar 21 02:29:50 PM PDT 24
Peak memory 250456 kb
Host smart-a26b1cba-ece8-41de-a991-817f2c4d43b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3691721968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idl
e.3691721968
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.1447419402
Short name T992
Test name
Test status
Simulation time 5864166479 ps
CPU time 23.83 seconds
Started Mar 21 02:26:25 PM PDT 24
Finished Mar 21 02:26:49 PM PDT 24
Peak memory 241080 kb
Host smart-753fb25d-dc53-4fe8-bad7-a95f9b811a46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447419402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.1447419402
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_intercept.1404255865
Short name T492
Test name
Test status
Simulation time 17326393106 ps
CPU time 12.66 seconds
Started Mar 21 02:26:27 PM PDT 24
Finished Mar 21 02:26:40 PM PDT 24
Peak memory 224704 kb
Host smart-5396be04-ef57-400e-8191-49f55f67e251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404255865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.1404255865
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.4057500720
Short name T576
Test name
Test status
Simulation time 286216677 ps
CPU time 3.45 seconds
Started Mar 21 02:26:25 PM PDT 24
Finished Mar 21 02:26:29 PM PDT 24
Peak memory 218568 kb
Host smart-488f98b2-52de-45ef-b5cd-c83b1c6118d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4057500720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.4057500720
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.464093393
Short name T546
Test name
Test status
Simulation time 3184701717 ps
CPU time 9.74 seconds
Started Mar 21 02:26:26 PM PDT 24
Finished Mar 21 02:26:35 PM PDT 24
Peak memory 224708 kb
Host smart-3b5a0f39-cc75-43ba-a1d7-0350e3e69bcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=464093393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swap
.464093393
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.3045641197
Short name T894
Test name
Test status
Simulation time 1143923543 ps
CPU time 6.58 seconds
Started Mar 21 02:26:24 PM PDT 24
Finished Mar 21 02:26:31 PM PDT 24
Peak memory 224660 kb
Host smart-c7f923ec-9438-4e3b-8cce-46c28d88d6dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3045641197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.3045641197
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.2948436070
Short name T839
Test name
Test status
Simulation time 1650954345 ps
CPU time 6.83 seconds
Started Mar 21 02:26:28 PM PDT 24
Finished Mar 21 02:26:35 PM PDT 24
Peak memory 219872 kb
Host smart-0dee17b3-893e-44e5-a250-0ba5c8321ac0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2948436070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir
ect.2948436070
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.2077731106
Short name T163
Test name
Test status
Simulation time 30084480670 ps
CPU time 282.88 seconds
Started Mar 21 02:26:29 PM PDT 24
Finished Mar 21 02:31:12 PM PDT 24
Peak memory 268564 kb
Host smart-ad0ea7b6-cc6f-4fd5-8014-7615495a3122
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077731106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stre
ss_all.2077731106
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.207067711
Short name T910
Test name
Test status
Simulation time 53687810457 ps
CPU time 66.85 seconds
Started Mar 21 02:26:25 PM PDT 24
Finished Mar 21 02:27:32 PM PDT 24
Peak memory 216492 kb
Host smart-d31195c0-468b-4c58-820e-b1882b9377e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207067711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.207067711
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.2774375516
Short name T342
Test name
Test status
Simulation time 1716973862 ps
CPU time 9.82 seconds
Started Mar 21 02:26:24 PM PDT 24
Finished Mar 21 02:26:35 PM PDT 24
Peak memory 216412 kb
Host smart-67ab3854-5b9c-43f4-af59-870b903d98e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2774375516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.2774375516
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.3867446861
Short name T555
Test name
Test status
Simulation time 600803334 ps
CPU time 2.84 seconds
Started Mar 21 02:26:29 PM PDT 24
Finished Mar 21 02:26:32 PM PDT 24
Peak memory 216632 kb
Host smart-0af66e39-efa4-4bab-9a0c-64a6d1694372
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867446861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.3867446861
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.3647616912
Short name T740
Test name
Test status
Simulation time 159499015 ps
CPU time 0.81 seconds
Started Mar 21 02:26:30 PM PDT 24
Finished Mar 21 02:26:31 PM PDT 24
Peak memory 205724 kb
Host smart-aedef92f-f7f8-44ef-a765-db2e507ecc1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3647616912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.3647616912
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.3090778055
Short name T32
Test name
Test status
Simulation time 245722076 ps
CPU time 2.34 seconds
Started Mar 21 02:26:25 PM PDT 24
Finished Mar 21 02:26:28 PM PDT 24
Peak memory 216872 kb
Host smart-e34fc379-c922-4ad3-8b51-51552a0bd0f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090778055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.3090778055
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.1124944469
Short name T335
Test name
Test status
Simulation time 52892916 ps
CPU time 0.7 seconds
Started Mar 21 02:26:41 PM PDT 24
Finished Mar 21 02:26:42 PM PDT 24
Peak memory 205764 kb
Host smart-74883716-636d-4746-93a1-ddaa4ae3ae4d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124944469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.
1124944469
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.703064834
Short name T484
Test name
Test status
Simulation time 1982067814 ps
CPU time 3.82 seconds
Started Mar 21 02:26:44 PM PDT 24
Finished Mar 21 02:26:48 PM PDT 24
Peak memory 224624 kb
Host smart-ff553be8-7afb-4282-a081-e8afec6f0198
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=703064834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.703064834
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.2824145584
Short name T704
Test name
Test status
Simulation time 62734108 ps
CPU time 0.76 seconds
Started Mar 21 02:26:30 PM PDT 24
Finished Mar 21 02:26:31 PM PDT 24
Peak memory 205512 kb
Host smart-fb868aae-a3cb-4044-afdf-216768df4e33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2824145584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.2824145584
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.4056862483
Short name T294
Test name
Test status
Simulation time 260003212695 ps
CPU time 134.94 seconds
Started Mar 21 02:26:38 PM PDT 24
Finished Mar 21 02:28:53 PM PDT 24
Peak memory 265692 kb
Host smart-2176a927-a419-4ecc-b20a-238b88c03143
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4056862483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.4056862483
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.346530703
Short name T87
Test name
Test status
Simulation time 50910922624 ps
CPU time 396.19 seconds
Started Mar 21 02:26:38 PM PDT 24
Finished Mar 21 02:33:14 PM PDT 24
Peak memory 257104 kb
Host smart-96d1463c-44c5-42fc-9b89-b0c406d07b25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=346530703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.346530703
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.2711186029
Short name T675
Test name
Test status
Simulation time 7087842591 ps
CPU time 80.11 seconds
Started Mar 21 02:26:40 PM PDT 24
Finished Mar 21 02:28:00 PM PDT 24
Peak memory 249616 kb
Host smart-4d377cac-945e-4c87-84da-34254f5330f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2711186029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idl
e.2711186029
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.2260413501
Short name T692
Test name
Test status
Simulation time 13938782682 ps
CPU time 20.68 seconds
Started Mar 21 02:26:43 PM PDT 24
Finished Mar 21 02:27:04 PM PDT 24
Peak memory 235340 kb
Host smart-c7cb8081-4d0f-47bc-997d-d70c3ad4bbef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2260413501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.2260413501
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_intercept.137323151
Short name T929
Test name
Test status
Simulation time 199027573 ps
CPU time 3.84 seconds
Started Mar 21 02:26:41 PM PDT 24
Finished Mar 21 02:26:45 PM PDT 24
Peak memory 217912 kb
Host smart-6ae6daa8-b838-4937-9a49-70cac81ed7a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=137323151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.137323151
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.3291427457
Short name T276
Test name
Test status
Simulation time 24098589174 ps
CPU time 20.29 seconds
Started Mar 21 02:26:49 PM PDT 24
Finished Mar 21 02:27:09 PM PDT 24
Peak memory 234028 kb
Host smart-14162d8e-628f-4f54-99fe-678653eecff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3291427457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.3291427457
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.4106351201
Short name T180
Test name
Test status
Simulation time 31941625565 ps
CPU time 21.47 seconds
Started Mar 21 02:26:38 PM PDT 24
Finished Mar 21 02:27:00 PM PDT 24
Peak memory 234360 kb
Host smart-3ab8209b-c28b-40c9-8fa4-20c0e62b382e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4106351201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa
p.4106351201
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.1927959979
Short name T808
Test name
Test status
Simulation time 1484820978 ps
CPU time 10.46 seconds
Started Mar 21 02:26:40 PM PDT 24
Finished Mar 21 02:26:51 PM PDT 24
Peak memory 233776 kb
Host smart-e52160cf-fead-421b-a094-f40eecfdd8cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1927959979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.1927959979
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.1182989824
Short name T673
Test name
Test status
Simulation time 5206885019 ps
CPU time 6.7 seconds
Started Mar 21 02:26:41 PM PDT 24
Finished Mar 21 02:26:48 PM PDT 24
Peak memory 222560 kb
Host smart-5daa3b49-fa5d-422f-8a8a-b36a25ffa1c5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1182989824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dir
ect.1182989824
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.1264798983
Short name T162
Test name
Test status
Simulation time 146246100 ps
CPU time 0.89 seconds
Started Mar 21 02:26:40 PM PDT 24
Finished Mar 21 02:26:41 PM PDT 24
Peak memory 205576 kb
Host smart-beb531f8-332d-4ac0-9f47-65bc671ccc76
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264798983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stre
ss_all.1264798983
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.3311361525
Short name T802
Test name
Test status
Simulation time 4113839590 ps
CPU time 24.97 seconds
Started Mar 21 02:26:26 PM PDT 24
Finished Mar 21 02:26:51 PM PDT 24
Peak memory 216540 kb
Host smart-6737ec6c-b3de-4958-9cb4-0e4bf2bec1f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3311361525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.3311361525
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.581118572
Short name T811
Test name
Test status
Simulation time 6369850750 ps
CPU time 15.63 seconds
Started Mar 21 02:26:28 PM PDT 24
Finished Mar 21 02:26:44 PM PDT 24
Peak memory 216504 kb
Host smart-a37b28d4-0ee7-41e4-a0f7-d0c613266c2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=581118572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.581118572
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.3405967952
Short name T385
Test name
Test status
Simulation time 509954262 ps
CPU time 1.47 seconds
Started Mar 21 02:26:37 PM PDT 24
Finished Mar 21 02:26:38 PM PDT 24
Peak memory 216520 kb
Host smart-7a8bc0b7-e19c-45f8-ac82-c8e80db29c06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3405967952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.3405967952
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.3294412379
Short name T882
Test name
Test status
Simulation time 431160623 ps
CPU time 1.13 seconds
Started Mar 21 02:26:39 PM PDT 24
Finished Mar 21 02:26:40 PM PDT 24
Peak memory 206776 kb
Host smart-9c7faa47-6b34-46c5-be34-316849f59736
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294412379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.3294412379
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.3104712160
Short name T445
Test name
Test status
Simulation time 6281073788 ps
CPU time 18.28 seconds
Started Mar 21 02:26:36 PM PDT 24
Finished Mar 21 02:26:55 PM PDT 24
Peak memory 218592 kb
Host smart-32030058-0b07-4feb-b9ab-f00e18a7e443
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104712160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.3104712160
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.2794978667
Short name T330
Test name
Test status
Simulation time 12209162 ps
CPU time 0.75 seconds
Started Mar 21 02:26:38 PM PDT 24
Finished Mar 21 02:26:39 PM PDT 24
Peak memory 205392 kb
Host smart-ad07fd86-dce9-4f32-bda4-506b84933571
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794978667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.
2794978667
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.1176555668
Short name T947
Test name
Test status
Simulation time 2691249705 ps
CPU time 6.04 seconds
Started Mar 21 02:26:39 PM PDT 24
Finished Mar 21 02:26:45 PM PDT 24
Peak memory 220128 kb
Host smart-f223b9b7-b16f-49dc-be05-c2713a9ca402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1176555668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.1176555668
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.862155118
Short name T337
Test name
Test status
Simulation time 50825038 ps
CPU time 0.77 seconds
Started Mar 21 02:26:44 PM PDT 24
Finished Mar 21 02:26:45 PM PDT 24
Peak memory 206684 kb
Host smart-d4c4b44d-d1a5-4f79-8c1a-694007714616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=862155118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.862155118
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.1806783308
Short name T517
Test name
Test status
Simulation time 78850205206 ps
CPU time 110.48 seconds
Started Mar 21 02:26:38 PM PDT 24
Finished Mar 21 02:28:29 PM PDT 24
Peak memory 256652 kb
Host smart-52e74aa9-776c-4a9e-9151-213e79e115ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806783308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.1806783308
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.1289739959
Short name T495
Test name
Test status
Simulation time 23305016725 ps
CPU time 150.33 seconds
Started Mar 21 02:26:44 PM PDT 24
Finished Mar 21 02:29:14 PM PDT 24
Peak memory 266152 kb
Host smart-103bcdd8-4ec2-46f4-bec5-7e605b4c1884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1289739959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.1289739959
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.1138476923
Short name T593
Test name
Test status
Simulation time 13695728961 ps
CPU time 91.49 seconds
Started Mar 21 02:26:39 PM PDT 24
Finished Mar 21 02:28:10 PM PDT 24
Peak memory 224372 kb
Host smart-d50f1caf-50c2-4b47-bad6-105b71a96d20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138476923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idl
e.1138476923
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_intercept.3206815496
Short name T216
Test name
Test status
Simulation time 135178130 ps
CPU time 2.74 seconds
Started Mar 21 02:26:42 PM PDT 24
Finished Mar 21 02:26:45 PM PDT 24
Peak memory 233876 kb
Host smart-b6d7386a-edad-499a-94d4-c1ef6743ed32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3206815496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.3206815496
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.1811885530
Short name T243
Test name
Test status
Simulation time 4038956550 ps
CPU time 15.81 seconds
Started Mar 21 02:26:39 PM PDT 24
Finished Mar 21 02:26:55 PM PDT 24
Peak memory 238048 kb
Host smart-697feec7-bb9c-45db-90df-2e3915b454b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811885530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.1811885530
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.1895084449
Short name T846
Test name
Test status
Simulation time 14373378258 ps
CPU time 4.88 seconds
Started Mar 21 02:26:45 PM PDT 24
Finished Mar 21 02:26:50 PM PDT 24
Peak memory 218172 kb
Host smart-79f08c22-2d44-40d0-9899-9ad5614b3cc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1895084449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swa
p.1895084449
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.3510916247
Short name T284
Test name
Test status
Simulation time 2616000438 ps
CPU time 11.89 seconds
Started Mar 21 02:26:37 PM PDT 24
Finished Mar 21 02:26:49 PM PDT 24
Peak memory 232884 kb
Host smart-a40fd1e3-a1a9-4b71-9f5e-05e91bf88ffd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510916247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.3510916247
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.1517505583
Short name T714
Test name
Test status
Simulation time 2407630447 ps
CPU time 4.41 seconds
Started Mar 21 02:26:44 PM PDT 24
Finished Mar 21 02:26:49 PM PDT 24
Peak memory 223228 kb
Host smart-897ce724-55e4-4f65-8f21-5d147960d550
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1517505583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dir
ect.1517505583
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.939505979
Short name T333
Test name
Test status
Simulation time 127206697 ps
CPU time 0.99 seconds
Started Mar 21 02:26:39 PM PDT 24
Finished Mar 21 02:26:40 PM PDT 24
Peak memory 206684 kb
Host smart-56273f2e-8bcc-4797-95e8-dfd167b486af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939505979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stres
s_all.939505979
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.1158654467
Short name T475
Test name
Test status
Simulation time 12625036522 ps
CPU time 20.28 seconds
Started Mar 21 02:26:43 PM PDT 24
Finished Mar 21 02:27:04 PM PDT 24
Peak memory 216560 kb
Host smart-b2d764d6-deb5-4dfc-b4ab-b042b95290c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1158654467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.1158654467
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.2035716940
Short name T20
Test name
Test status
Simulation time 6110447530 ps
CPU time 23.36 seconds
Started Mar 21 02:26:39 PM PDT 24
Finished Mar 21 02:27:03 PM PDT 24
Peak memory 216548 kb
Host smart-3c714fe0-dd4c-4944-acac-bd403fa628c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035716940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.2035716940
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.3766782954
Short name T574
Test name
Test status
Simulation time 48888812 ps
CPU time 1.44 seconds
Started Mar 21 02:26:46 PM PDT 24
Finished Mar 21 02:26:48 PM PDT 24
Peak memory 216500 kb
Host smart-60f5d22d-a2cb-416e-b39b-07da91135a26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766782954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.3766782954
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.1056172128
Short name T891
Test name
Test status
Simulation time 84799746 ps
CPU time 0.92 seconds
Started Mar 21 02:26:37 PM PDT 24
Finished Mar 21 02:26:38 PM PDT 24
Peak memory 205756 kb
Host smart-f353b21a-1051-4fa6-95c0-e1e0049613a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1056172128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.1056172128
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.4220331650
Short name T805
Test name
Test status
Simulation time 354115822 ps
CPU time 6.92 seconds
Started Mar 21 02:26:38 PM PDT 24
Finished Mar 21 02:26:45 PM PDT 24
Peak memory 226752 kb
Host smart-db04a1ba-6dbe-4bc7-8c38-16bc5df25b44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220331650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.4220331650
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.3223431794
Short name T608
Test name
Test status
Simulation time 30010227 ps
CPU time 0.71 seconds
Started Mar 21 02:23:30 PM PDT 24
Finished Mar 21 02:23:31 PM PDT 24
Peak memory 204872 kb
Host smart-ee686e20-6e98-4fc8-8de2-6bf5cdda5242
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223431794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.3
223431794
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.2094025081
Short name T739
Test name
Test status
Simulation time 371890376 ps
CPU time 3.11 seconds
Started Mar 21 02:23:28 PM PDT 24
Finished Mar 21 02:23:32 PM PDT 24
Peak memory 224604 kb
Host smart-22c875c9-8a29-4a01-ac54-93511ebccee3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2094025081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.2094025081
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.885977634
Short name T752
Test name
Test status
Simulation time 99790905 ps
CPU time 0.72 seconds
Started Mar 21 02:23:32 PM PDT 24
Finished Mar 21 02:23:34 PM PDT 24
Peak memory 205672 kb
Host smart-2cb7c5a7-beef-40dc-85cf-9f07ac182205
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=885977634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.885977634
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.914114973
Short name T487
Test name
Test status
Simulation time 13928914874 ps
CPU time 78.14 seconds
Started Mar 21 02:23:30 PM PDT 24
Finished Mar 21 02:24:48 PM PDT 24
Peak memory 249860 kb
Host smart-893da889-7f73-4777-a361-a7d372d21fa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=914114973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.914114973
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.2095158880
Short name T47
Test name
Test status
Simulation time 1934891439 ps
CPU time 35.28 seconds
Started Mar 21 02:23:30 PM PDT 24
Finished Mar 21 02:24:07 PM PDT 24
Peak memory 248892 kb
Host smart-f937ff19-8aae-4f57-aa8a-85fd1039c4d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2095158880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.2095158880
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.173212245
Short name T716
Test name
Test status
Simulation time 10157272921 ps
CPU time 15.99 seconds
Started Mar 21 02:23:31 PM PDT 24
Finished Mar 21 02:23:49 PM PDT 24
Peak memory 236716 kb
Host smart-1a4add90-d930-4de3-90fd-a90379b2b22e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=173212245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.173212245
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_intercept.3120884581
Short name T344
Test name
Test status
Simulation time 1822654989 ps
CPU time 3.35 seconds
Started Mar 21 02:23:30 PM PDT 24
Finished Mar 21 02:23:34 PM PDT 24
Peak memory 232904 kb
Host smart-bc9b8438-40dd-449d-a6fe-62dfcc17b05c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3120884581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.3120884581
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.831567941
Short name T233
Test name
Test status
Simulation time 40987658752 ps
CPU time 16.51 seconds
Started Mar 21 02:23:28 PM PDT 24
Finished Mar 21 02:23:45 PM PDT 24
Peak memory 226912 kb
Host smart-1194178d-5394-4bf5-a92d-27cc8bab99cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=831567941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.831567941
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_mem_parity.2752641798
Short name T726
Test name
Test status
Simulation time 16055384 ps
CPU time 1.02 seconds
Started Mar 21 02:23:28 PM PDT 24
Finished Mar 21 02:23:30 PM PDT 24
Peak memory 218212 kb
Host smart-52e513f0-37ca-4ade-822b-592a1aa5ba4a
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752641798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 4.spi_device_mem_parity.2752641798
Directory /workspace/4.spi_device_mem_parity/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.3687870844
Short name T855
Test name
Test status
Simulation time 5067522915 ps
CPU time 21.26 seconds
Started Mar 21 02:23:29 PM PDT 24
Finished Mar 21 02:23:50 PM PDT 24
Peak memory 248972 kb
Host smart-2fc4a832-80cd-458b-b6c6-bbd5dbc0c7c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3687870844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap
.3687870844
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.900630840
Short name T737
Test name
Test status
Simulation time 184072332 ps
CPU time 3.81 seconds
Started Mar 21 02:23:30 PM PDT 24
Finished Mar 21 02:23:34 PM PDT 24
Peak memory 233720 kb
Host smart-b67cf872-12b4-4bef-b284-27efb3119cd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=900630840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.900630840
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_ram_cfg.3150815965
Short name T949
Test name
Test status
Simulation time 18321051 ps
CPU time 0.74 seconds
Started Mar 21 02:23:28 PM PDT 24
Finished Mar 21 02:23:30 PM PDT 24
Peak memory 216408 kb
Host smart-77fde6d3-f8b2-4137-bf0d-7c4e0e6a829c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150815965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_ram_cfg.3150815965
Directory /workspace/4.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.1001027553
Short name T141
Test name
Test status
Simulation time 91823906 ps
CPU time 3.77 seconds
Started Mar 21 02:23:30 PM PDT 24
Finished Mar 21 02:23:34 PM PDT 24
Peak memory 221872 kb
Host smart-1ddbd801-a339-41ce-a121-f03d8421d601
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1001027553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire
ct.1001027553
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.3687303591
Short name T78
Test name
Test status
Simulation time 169280998 ps
CPU time 1.21 seconds
Started Mar 21 02:23:32 PM PDT 24
Finished Mar 21 02:23:34 PM PDT 24
Peak memory 235864 kb
Host smart-8c8963e2-e69a-454c-927c-275844c51a08
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687303591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.3687303591
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.2827509617
Short name T652
Test name
Test status
Simulation time 7891428439 ps
CPU time 98.49 seconds
Started Mar 21 02:23:31 PM PDT 24
Finished Mar 21 02:25:11 PM PDT 24
Peak memory 249576 kb
Host smart-0b47a0d0-9e37-43e6-92e2-1ccd9be0e89d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827509617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stres
s_all.2827509617
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.2536898634
Short name T506
Test name
Test status
Simulation time 43654735894 ps
CPU time 65.53 seconds
Started Mar 21 02:23:30 PM PDT 24
Finished Mar 21 02:24:37 PM PDT 24
Peak memory 216644 kb
Host smart-52ffa07b-8493-4c3d-9661-99aba4f97391
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2536898634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.2536898634
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.2808704903
Short name T777
Test name
Test status
Simulation time 440650826 ps
CPU time 1.38 seconds
Started Mar 21 02:23:30 PM PDT 24
Finished Mar 21 02:23:33 PM PDT 24
Peak memory 207032 kb
Host smart-3245d3de-2ee9-4228-be5b-56cd57212fb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2808704903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.2808704903
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.1765866263
Short name T356
Test name
Test status
Simulation time 268696136 ps
CPU time 3.76 seconds
Started Mar 21 02:23:29 PM PDT 24
Finished Mar 21 02:23:33 PM PDT 24
Peak memory 216656 kb
Host smart-f963759a-3532-47de-998b-466063628ec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1765866263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.1765866263
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.1765655650
Short name T953
Test name
Test status
Simulation time 32762757 ps
CPU time 0.81 seconds
Started Mar 21 02:23:28 PM PDT 24
Finished Mar 21 02:23:29 PM PDT 24
Peak memory 205732 kb
Host smart-6d4e29a6-1eae-40f9-9cf5-a36a28e6a435
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1765655650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.1765655650
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.516758699
Short name T447
Test name
Test status
Simulation time 1831492384 ps
CPU time 13.21 seconds
Started Mar 21 02:23:30 PM PDT 24
Finished Mar 21 02:23:45 PM PDT 24
Peak memory 238760 kb
Host smart-4046b097-d254-4202-9ddf-b6cb1ab72b6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=516758699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.516758699
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.1690942432
Short name T600
Test name
Test status
Simulation time 47121651 ps
CPU time 0.72 seconds
Started Mar 21 02:26:52 PM PDT 24
Finished Mar 21 02:26:53 PM PDT 24
Peak memory 205420 kb
Host smart-5ff3cf48-88bf-4917-9c69-9045cd541ad6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690942432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.
1690942432
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.1291554545
Short name T252
Test name
Test status
Simulation time 1930069326 ps
CPU time 2.92 seconds
Started Mar 21 02:26:51 PM PDT 24
Finished Mar 21 02:26:54 PM PDT 24
Peak memory 224576 kb
Host smart-7cf6badf-ae39-4eea-b2ab-e2b0aa36d1b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291554545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.1291554545
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.3852477263
Short name T753
Test name
Test status
Simulation time 93801452 ps
CPU time 0.81 seconds
Started Mar 21 02:26:39 PM PDT 24
Finished Mar 21 02:26:40 PM PDT 24
Peak memory 206560 kb
Host smart-33d4701b-6cfd-4181-bfed-ec025a4bd0a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852477263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.3852477263
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.92663057
Short name T427
Test name
Test status
Simulation time 34724494952 ps
CPU time 73.5 seconds
Started Mar 21 02:26:53 PM PDT 24
Finished Mar 21 02:28:06 PM PDT 24
Peak memory 237212 kb
Host smart-41923096-6575-427c-ab64-dcb4d3e701d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92663057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.92663057
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.2097030085
Short name T697
Test name
Test status
Simulation time 5878132823 ps
CPU time 22.74 seconds
Started Mar 21 02:26:58 PM PDT 24
Finished Mar 21 02:27:21 PM PDT 24
Peak memory 241100 kb
Host smart-e35cd76c-880d-455b-9d51-90079cedff47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2097030085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.2097030085
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_intercept.799394161
Short name T486
Test name
Test status
Simulation time 586108971 ps
CPU time 3.15 seconds
Started Mar 21 02:26:44 PM PDT 24
Finished Mar 21 02:26:47 PM PDT 24
Peak memory 234012 kb
Host smart-34f28b00-bacf-406b-98a7-0f1f7f6ede1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=799394161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.799394161
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.584864986
Short name T374
Test name
Test status
Simulation time 164861560 ps
CPU time 3.35 seconds
Started Mar 21 02:26:38 PM PDT 24
Finished Mar 21 02:26:41 PM PDT 24
Peak memory 233740 kb
Host smart-a4ff8626-8fec-455b-87f9-5959e47e5914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=584864986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.584864986
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.3759367561
Short name T288
Test name
Test status
Simulation time 5136567389 ps
CPU time 6.83 seconds
Started Mar 21 02:26:47 PM PDT 24
Finished Mar 21 02:26:54 PM PDT 24
Peak memory 227700 kb
Host smart-1af36718-3d84-461b-ab27-cef5d4e6d801
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759367561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swa
p.3759367561
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.1672942827
Short name T911
Test name
Test status
Simulation time 5187287253 ps
CPU time 5.49 seconds
Started Mar 21 02:26:39 PM PDT 24
Finished Mar 21 02:26:44 PM PDT 24
Peak memory 234604 kb
Host smart-0809db7d-6b54-4fed-b10a-8a57f8fe25fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1672942827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.1672942827
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.4123287322
Short name T515
Test name
Test status
Simulation time 1476037265 ps
CPU time 5.42 seconds
Started Mar 21 02:26:50 PM PDT 24
Finished Mar 21 02:26:55 PM PDT 24
Peak memory 219236 kb
Host smart-417974e0-0f7a-4f2a-b662-c69153c71c8a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4123287322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir
ect.4123287322
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.3808569231
Short name T480
Test name
Test status
Simulation time 38335468 ps
CPU time 0.93 seconds
Started Mar 21 02:26:58 PM PDT 24
Finished Mar 21 02:26:59 PM PDT 24
Peak memory 206584 kb
Host smart-fea72c69-381d-442b-bfec-06d650fa356f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808569231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stre
ss_all.3808569231
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.1144810163
Short name T923
Test name
Test status
Simulation time 476083053 ps
CPU time 3.01 seconds
Started Mar 21 02:26:38 PM PDT 24
Finished Mar 21 02:26:41 PM PDT 24
Peak memory 216648 kb
Host smart-5a6a476f-5112-4a22-ac2c-60aae12f10c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144810163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.1144810163
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.2356472271
Short name T954
Test name
Test status
Simulation time 80943567234 ps
CPU time 18.26 seconds
Started Mar 21 02:26:38 PM PDT 24
Finished Mar 21 02:26:56 PM PDT 24
Peak memory 216612 kb
Host smart-f8137131-c05e-46d8-83b1-92570b4a206f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2356472271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.2356472271
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.1900447868
Short name T84
Test name
Test status
Simulation time 34422528 ps
CPU time 1.18 seconds
Started Mar 21 02:26:39 PM PDT 24
Finished Mar 21 02:26:40 PM PDT 24
Peak memory 208012 kb
Host smart-92b3a8da-8254-4e86-a101-98aec1fae69a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1900447868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.1900447868
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.1398689691
Short name T727
Test name
Test status
Simulation time 20681234 ps
CPU time 0.73 seconds
Started Mar 21 02:26:42 PM PDT 24
Finished Mar 21 02:26:42 PM PDT 24
Peak memory 205728 kb
Host smart-ec786523-d7dd-41f6-8e66-568427502327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1398689691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.1398689691
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.1725395425
Short name T795
Test name
Test status
Simulation time 27005993905 ps
CPU time 20.26 seconds
Started Mar 21 02:26:39 PM PDT 24
Finished Mar 21 02:27:00 PM PDT 24
Peak memory 219508 kb
Host smart-e30dc523-218f-4060-9dea-242ce919bb3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1725395425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.1725395425
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.534305818
Short name T731
Test name
Test status
Simulation time 12860969 ps
CPU time 0.72 seconds
Started Mar 21 02:26:52 PM PDT 24
Finished Mar 21 02:26:53 PM PDT 24
Peak memory 205420 kb
Host smart-b498d1c0-9c7b-40d5-9e66-6012ff114a91
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534305818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.534305818
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.2766820795
Short name T169
Test name
Test status
Simulation time 383032213 ps
CPU time 3.76 seconds
Started Mar 21 02:26:51 PM PDT 24
Finished Mar 21 02:26:55 PM PDT 24
Peak memory 233336 kb
Host smart-cf5232f8-a582-4aeb-810d-d852af86a0cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2766820795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.2766820795
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.2497419881
Short name T520
Test name
Test status
Simulation time 56923311 ps
CPU time 0.77 seconds
Started Mar 21 02:26:58 PM PDT 24
Finished Mar 21 02:26:59 PM PDT 24
Peak memory 206540 kb
Host smart-236c5c12-10b6-4e83-9a5f-2dfc1fe75b4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497419881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.2497419881
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.2415871719
Short name T474
Test name
Test status
Simulation time 7520258568 ps
CPU time 49.33 seconds
Started Mar 21 02:26:51 PM PDT 24
Finished Mar 21 02:27:41 PM PDT 24
Peak memory 235404 kb
Host smart-118ec218-4588-4f31-a06b-20499642c314
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415871719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.2415871719
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.3996770965
Short name T302
Test name
Test status
Simulation time 374974657807 ps
CPU time 745.53 seconds
Started Mar 21 02:26:50 PM PDT 24
Finished Mar 21 02:39:16 PM PDT 24
Peak memory 265836 kb
Host smart-a2b0c65c-3807-454b-86a5-9f7a80b62280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996770965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idl
e.3996770965
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_intercept.3472865461
Short name T541
Test name
Test status
Simulation time 1799354749 ps
CPU time 5.06 seconds
Started Mar 21 02:26:50 PM PDT 24
Finished Mar 21 02:26:55 PM PDT 24
Peak memory 224580 kb
Host smart-47fcf138-9afe-4fdd-8f5c-e13b8f59e739
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472865461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.3472865461
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.3056971321
Short name T218
Test name
Test status
Simulation time 1398777283 ps
CPU time 11.61 seconds
Started Mar 21 02:26:53 PM PDT 24
Finished Mar 21 02:27:04 PM PDT 24
Peak memory 252888 kb
Host smart-443076b9-c394-4b72-8ee4-3214779db0ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3056971321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.3056971321
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.4153224038
Short name T280
Test name
Test status
Simulation time 1675983983 ps
CPU time 6.74 seconds
Started Mar 21 02:26:51 PM PDT 24
Finished Mar 21 02:26:58 PM PDT 24
Peak memory 233644 kb
Host smart-013d571d-1a1a-4d03-9f87-1024666c8ca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4153224038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swa
p.4153224038
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.2722385918
Short name T914
Test name
Test status
Simulation time 843383635 ps
CPU time 5.55 seconds
Started Mar 21 02:26:52 PM PDT 24
Finished Mar 21 02:26:57 PM PDT 24
Peak memory 235616 kb
Host smart-94ba22b7-0135-4de2-a463-338cec3e67a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2722385918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.2722385918
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.182542501
Short name T401
Test name
Test status
Simulation time 461239587 ps
CPU time 3.26 seconds
Started Mar 21 02:26:52 PM PDT 24
Finished Mar 21 02:26:55 PM PDT 24
Peak memory 223108 kb
Host smart-3a0451e2-d3b0-42c4-986e-632838bf2587
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=182542501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dire
ct.182542501
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.4115603431
Short name T936
Test name
Test status
Simulation time 1647408375 ps
CPU time 22.12 seconds
Started Mar 21 02:26:52 PM PDT 24
Finished Mar 21 02:27:15 PM PDT 24
Peak memory 220764 kb
Host smart-ec918d26-ffa9-47df-a540-e59cba08db4f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115603431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stre
ss_all.4115603431
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.1410434609
Short name T319
Test name
Test status
Simulation time 10161569269 ps
CPU time 32.07 seconds
Started Mar 21 02:26:50 PM PDT 24
Finished Mar 21 02:27:23 PM PDT 24
Peak memory 216616 kb
Host smart-9a01a0e7-e230-4a50-8f5c-afe86d46d13a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1410434609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.1410434609
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.753063298
Short name T569
Test name
Test status
Simulation time 12302287336 ps
CPU time 13.79 seconds
Started Mar 21 02:26:51 PM PDT 24
Finished Mar 21 02:27:05 PM PDT 24
Peak memory 216532 kb
Host smart-3edbb2e4-b68f-48c7-b054-fed087af8f2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=753063298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.753063298
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.4116698377
Short name T616
Test name
Test status
Simulation time 133623805 ps
CPU time 2.87 seconds
Started Mar 21 02:26:52 PM PDT 24
Finished Mar 21 02:26:55 PM PDT 24
Peak memory 217804 kb
Host smart-9b99924c-1e97-4201-a5ee-6736c9654ed3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116698377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.4116698377
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.3754955419
Short name T823
Test name
Test status
Simulation time 23910817 ps
CPU time 0.76 seconds
Started Mar 21 02:26:49 PM PDT 24
Finished Mar 21 02:26:50 PM PDT 24
Peak memory 205784 kb
Host smart-bc2845a5-a421-4e4b-a960-4cd9a21909da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3754955419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.3754955419
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.2210678259
Short name T256
Test name
Test status
Simulation time 697880574 ps
CPU time 5 seconds
Started Mar 21 02:26:49 PM PDT 24
Finished Mar 21 02:26:54 PM PDT 24
Peak memory 218976 kb
Host smart-346c10c6-c7a7-4320-8d91-e6bdfc8f60c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2210678259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.2210678259
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.4246665592
Short name T395
Test name
Test status
Simulation time 20585437 ps
CPU time 0.78 seconds
Started Mar 21 02:27:04 PM PDT 24
Finished Mar 21 02:27:05 PM PDT 24
Peak memory 205444 kb
Host smart-55a3dd06-52e7-4a8d-81b9-896ee729280e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246665592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
4246665592
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.108978080
Short name T962
Test name
Test status
Simulation time 2758216057 ps
CPU time 4.86 seconds
Started Mar 21 02:26:50 PM PDT 24
Finished Mar 21 02:26:54 PM PDT 24
Peak memory 219892 kb
Host smart-b6c5d65a-394d-43ae-b5a1-d60c47e99b5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108978080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.108978080
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.3815156279
Short name T370
Test name
Test status
Simulation time 22465869 ps
CPU time 0.83 seconds
Started Mar 21 02:26:58 PM PDT 24
Finished Mar 21 02:26:59 PM PDT 24
Peak memory 206900 kb
Host smart-aeee7767-c823-4561-affa-4643f1589932
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815156279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.3815156279
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.2484141523
Short name T201
Test name
Test status
Simulation time 7930418233 ps
CPU time 86.56 seconds
Started Mar 21 02:27:03 PM PDT 24
Finished Mar 21 02:28:30 PM PDT 24
Peak memory 266888 kb
Host smart-14eea2cb-13ea-4ff8-9b17-b495be2c194f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2484141523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.2484141523
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.69500986
Short name T293
Test name
Test status
Simulation time 141087863880 ps
CPU time 420.68 seconds
Started Mar 21 02:27:02 PM PDT 24
Finished Mar 21 02:34:03 PM PDT 24
Peak memory 258032 kb
Host smart-9a076622-31de-4ee6-b4d0-895f8c08ed01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69500986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.69500986
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.1204242847
Short name T315
Test name
Test status
Simulation time 4058415969 ps
CPU time 23.12 seconds
Started Mar 21 02:26:54 PM PDT 24
Finished Mar 21 02:27:17 PM PDT 24
Peak memory 241168 kb
Host smart-65fa4a65-a377-4974-b591-9022c58ae674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204242847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.1204242847
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_intercept.2959157463
Short name T556
Test name
Test status
Simulation time 1614098444 ps
CPU time 4.97 seconds
Started Mar 21 02:26:50 PM PDT 24
Finished Mar 21 02:26:56 PM PDT 24
Peak memory 224560 kb
Host smart-43ddb82c-78eb-4d0a-9a2e-182c58860e28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2959157463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.2959157463
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.2761907256
Short name T109
Test name
Test status
Simulation time 1238285729 ps
CPU time 9.62 seconds
Started Mar 21 02:26:58 PM PDT 24
Finished Mar 21 02:27:07 PM PDT 24
Peak memory 231944 kb
Host smart-bcba7da1-8af0-4816-8f26-bc8c57301d02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761907256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.2761907256
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.2810809060
Short name T545
Test name
Test status
Simulation time 32148116606 ps
CPU time 12.11 seconds
Started Mar 21 02:26:50 PM PDT 24
Finished Mar 21 02:27:03 PM PDT 24
Peak memory 241020 kb
Host smart-1f17cadb-0ce8-497b-810f-35621bab30c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2810809060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swa
p.2810809060
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.3106580455
Short name T181
Test name
Test status
Simulation time 13527820857 ps
CPU time 13.6 seconds
Started Mar 21 02:26:51 PM PDT 24
Finished Mar 21 02:27:05 PM PDT 24
Peak memory 233768 kb
Host smart-ec55766b-f44e-4630-a1d3-f5389a761cde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3106580455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.3106580455
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.920147935
Short name T878
Test name
Test status
Simulation time 1588948667 ps
CPU time 3.35 seconds
Started Mar 21 02:27:03 PM PDT 24
Finished Mar 21 02:27:07 PM PDT 24
Peak memory 219200 kb
Host smart-456f3e2a-99e2-4bab-a5e9-66aa59c3c6ac
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=920147935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dire
ct.920147935
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.3322761160
Short name T303
Test name
Test status
Simulation time 176714387758 ps
CPU time 402.21 seconds
Started Mar 21 02:27:07 PM PDT 24
Finished Mar 21 02:33:49 PM PDT 24
Peak memory 253272 kb
Host smart-b2ce41ed-0a97-47a3-9371-c4db8f338ea8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322761160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stre
ss_all.3322761160
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.2081423676
Short name T764
Test name
Test status
Simulation time 2841914939 ps
CPU time 30.84 seconds
Started Mar 21 02:26:49 PM PDT 24
Finished Mar 21 02:27:19 PM PDT 24
Peak memory 220264 kb
Host smart-be51ef91-9f23-4830-8be1-00522c739b7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2081423676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.2081423676
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.2659423712
Short name T327
Test name
Test status
Simulation time 11525995279 ps
CPU time 31.74 seconds
Started Mar 21 02:26:54 PM PDT 24
Finished Mar 21 02:27:26 PM PDT 24
Peak memory 216552 kb
Host smart-2352b81e-5424-4300-ab41-85e7afd742ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2659423712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.2659423712
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.500907381
Short name T647
Test name
Test status
Simulation time 94995656 ps
CPU time 2.09 seconds
Started Mar 21 02:26:51 PM PDT 24
Finished Mar 21 02:26:53 PM PDT 24
Peak memory 216460 kb
Host smart-287f19a0-bf44-45d1-b997-907979efd44d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500907381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.500907381
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.2807775842
Short name T414
Test name
Test status
Simulation time 68566300 ps
CPU time 0.73 seconds
Started Mar 21 02:26:52 PM PDT 24
Finished Mar 21 02:26:53 PM PDT 24
Peak memory 205756 kb
Host smart-97c95230-5a3e-43c7-8252-4703297f0885
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807775842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.2807775842
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.433445800
Short name T267
Test name
Test status
Simulation time 12363362698 ps
CPU time 18.07 seconds
Started Mar 21 02:26:52 PM PDT 24
Finished Mar 21 02:27:11 PM PDT 24
Peak memory 249376 kb
Host smart-f3017286-cf5f-43d5-9742-d7acc9a90bae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=433445800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.433445800
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.169793372
Short name T632
Test name
Test status
Simulation time 136375974 ps
CPU time 0.76 seconds
Started Mar 21 02:27:04 PM PDT 24
Finished Mar 21 02:27:05 PM PDT 24
Peak memory 205796 kb
Host smart-a71a1c80-6d83-4455-bd01-6faa3e2ff719
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169793372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.169793372
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.1217266517
Short name T563
Test name
Test status
Simulation time 1148416914 ps
CPU time 4.7 seconds
Started Mar 21 02:27:01 PM PDT 24
Finished Mar 21 02:27:06 PM PDT 24
Peak memory 220416 kb
Host smart-aa9f115c-4b5a-4961-8d8b-8a5941037c0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1217266517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.1217266517
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.2678568638
Short name T434
Test name
Test status
Simulation time 53199853 ps
CPU time 0.78 seconds
Started Mar 21 02:27:04 PM PDT 24
Finished Mar 21 02:27:05 PM PDT 24
Peak memory 205536 kb
Host smart-f5b2e4ed-6542-495b-955b-cbc590ba397d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2678568638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.2678568638
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.1260624124
Short name T194
Test name
Test status
Simulation time 236550227069 ps
CPU time 256.69 seconds
Started Mar 21 02:27:04 PM PDT 24
Finished Mar 21 02:31:21 PM PDT 24
Peak memory 249404 kb
Host smart-71a515dd-d401-4d52-a8d3-dd8f355ba3b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260624124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.1260624124
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.2144341399
Short name T557
Test name
Test status
Simulation time 22655007904 ps
CPU time 63.24 seconds
Started Mar 21 02:27:01 PM PDT 24
Finished Mar 21 02:28:04 PM PDT 24
Peak memory 253448 kb
Host smart-9520562e-0ad3-42bf-9aef-3b87a87e7947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2144341399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.2144341399
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.2236542337
Short name T456
Test name
Test status
Simulation time 19903337588 ps
CPU time 38.44 seconds
Started Mar 21 02:27:00 PM PDT 24
Finished Mar 21 02:27:39 PM PDT 24
Peak memory 233832 kb
Host smart-5d9501a5-1fdd-4865-a60d-047f64eac115
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2236542337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.2236542337
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_intercept.4225393171
Short name T85
Test name
Test status
Simulation time 8761711044 ps
CPU time 9.42 seconds
Started Mar 21 02:27:03 PM PDT 24
Finished Mar 21 02:27:13 PM PDT 24
Peak memory 234128 kb
Host smart-65bc3c99-cb90-4185-a1b0-141a86d125bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4225393171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.4225393171
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.3574324039
Short name T253
Test name
Test status
Simulation time 3116315962 ps
CPU time 5.1 seconds
Started Mar 21 02:27:02 PM PDT 24
Finished Mar 21 02:27:07 PM PDT 24
Peak memory 233960 kb
Host smart-0b61012b-8a16-4583-957a-22ac427ea732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3574324039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.3574324039
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.3063888935
Short name T235
Test name
Test status
Simulation time 670655449 ps
CPU time 8.46 seconds
Started Mar 21 02:27:03 PM PDT 24
Finished Mar 21 02:27:12 PM PDT 24
Peak memory 240940 kb
Host smart-a2d287cf-bdcc-45d5-917c-4dbd993282f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063888935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swa
p.3063888935
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.918553098
Short name T412
Test name
Test status
Simulation time 543720259 ps
CPU time 3.85 seconds
Started Mar 21 02:27:00 PM PDT 24
Finished Mar 21 02:27:04 PM PDT 24
Peak memory 233544 kb
Host smart-b4a1b103-97ac-4b56-8e9a-868d08f9fe1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918553098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.918553098
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.3733061014
Short name T559
Test name
Test status
Simulation time 836379499 ps
CPU time 5.36 seconds
Started Mar 21 02:27:02 PM PDT 24
Finished Mar 21 02:27:08 PM PDT 24
Peak memory 222860 kb
Host smart-bbc10c10-53dc-4d3d-ac8a-49031c19876c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3733061014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dir
ect.3733061014
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.712313512
Short name T237
Test name
Test status
Simulation time 330332642983 ps
CPU time 664.82 seconds
Started Mar 21 02:27:01 PM PDT 24
Finished Mar 21 02:38:06 PM PDT 24
Peak memory 265828 kb
Host smart-2d027f8e-91b3-4eb1-bd3b-6adbfb1f3f74
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712313512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stres
s_all.712313512
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.973633469
Short name T683
Test name
Test status
Simulation time 2378668181 ps
CPU time 19.29 seconds
Started Mar 21 02:27:03 PM PDT 24
Finished Mar 21 02:27:22 PM PDT 24
Peak memory 216632 kb
Host smart-a7167269-8b6e-4804-bc24-4c339e13c3d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=973633469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.973633469
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.3494526152
Short name T384
Test name
Test status
Simulation time 26575057351 ps
CPU time 19.92 seconds
Started Mar 21 02:27:03 PM PDT 24
Finished Mar 21 02:27:24 PM PDT 24
Peak memory 216476 kb
Host smart-a5c9b8cf-2510-45af-8db7-6bb47dee211c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3494526152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.3494526152
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.1173903348
Short name T362
Test name
Test status
Simulation time 116588235 ps
CPU time 6.19 seconds
Started Mar 21 02:27:04 PM PDT 24
Finished Mar 21 02:27:10 PM PDT 24
Peak memory 216740 kb
Host smart-914b83a8-aa31-4afa-b581-7beeb9d804df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1173903348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.1173903348
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.2351010577
Short name T461
Test name
Test status
Simulation time 331965879 ps
CPU time 1.03 seconds
Started Mar 21 02:27:03 PM PDT 24
Finished Mar 21 02:27:05 PM PDT 24
Peak memory 205744 kb
Host smart-e5530a39-a36f-4e30-87ba-09824f55bf69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2351010577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.2351010577
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.2781315043
Short name T862
Test name
Test status
Simulation time 2197338240 ps
CPU time 3.02 seconds
Started Mar 21 02:27:01 PM PDT 24
Finished Mar 21 02:27:04 PM PDT 24
Peak memory 218712 kb
Host smart-940b3490-2204-4594-9db5-133ec285ba56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2781315043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.2781315043
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.1818936397
Short name T322
Test name
Test status
Simulation time 51341580 ps
CPU time 0.76 seconds
Started Mar 21 02:27:09 PM PDT 24
Finished Mar 21 02:27:10 PM PDT 24
Peak memory 205456 kb
Host smart-697b9eb7-6315-411e-bcf0-bcc884edaef6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818936397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.
1818936397
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.1177872925
Short name T634
Test name
Test status
Simulation time 857683184 ps
CPU time 4.22 seconds
Started Mar 21 02:27:04 PM PDT 24
Finished Mar 21 02:27:08 PM PDT 24
Peak memory 224624 kb
Host smart-5152f04f-1094-4bd9-ae0e-6f875f34442a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177872925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.1177872925
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.2150024852
Short name T386
Test name
Test status
Simulation time 15817007 ps
CPU time 0.82 seconds
Started Mar 21 02:27:03 PM PDT 24
Finished Mar 21 02:27:04 PM PDT 24
Peak memory 206896 kb
Host smart-c752951c-1bc6-408a-8b83-0830d33aba8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2150024852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.2150024852
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.1424556247
Short name T722
Test name
Test status
Simulation time 17717771256 ps
CPU time 40.63 seconds
Started Mar 21 02:27:07 PM PDT 24
Finished Mar 21 02:27:48 PM PDT 24
Peak memory 249264 kb
Host smart-90871b1d-2a27-4677-bb38-2d16f2e14bc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1424556247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.1424556247
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.920067897
Short name T298
Test name
Test status
Simulation time 42141014146 ps
CPU time 73.14 seconds
Started Mar 21 02:27:10 PM PDT 24
Finished Mar 21 02:28:23 PM PDT 24
Peak memory 236008 kb
Host smart-e796a9a5-7bfa-46c4-9a89-666ed39d7e44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920067897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idle
.920067897
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.2133344505
Short name T554
Test name
Test status
Simulation time 3608443140 ps
CPU time 11.41 seconds
Started Mar 21 02:27:07 PM PDT 24
Finished Mar 21 02:27:19 PM PDT 24
Peak memory 249044 kb
Host smart-26ff10b7-201e-41b8-bd59-db80a68c49f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2133344505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.2133344505
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_intercept.2040911686
Short name T490
Test name
Test status
Simulation time 694240522 ps
CPU time 4.73 seconds
Started Mar 21 02:27:04 PM PDT 24
Finished Mar 21 02:27:09 PM PDT 24
Peak memory 236552 kb
Host smart-b6aa3278-20df-43ef-b344-e2291cc2e455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040911686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.2040911686
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.2655004208
Short name T193
Test name
Test status
Simulation time 6291328862 ps
CPU time 14.73 seconds
Started Mar 21 02:27:04 PM PDT 24
Finished Mar 21 02:27:19 PM PDT 24
Peak memory 228792 kb
Host smart-66723999-7e33-4a7a-9579-a9d5e742956b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2655004208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.2655004208
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.2591152413
Short name T588
Test name
Test status
Simulation time 562511484 ps
CPU time 4.31 seconds
Started Mar 21 02:27:04 PM PDT 24
Finished Mar 21 02:27:08 PM PDT 24
Peak memory 217908 kb
Host smart-0914a106-1d37-4aa8-ac4b-568089e9e997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2591152413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swa
p.2591152413
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.2634030861
Short name T38
Test name
Test status
Simulation time 5845312012 ps
CPU time 9.8 seconds
Started Mar 21 02:27:01 PM PDT 24
Finished Mar 21 02:27:11 PM PDT 24
Peak memory 248044 kb
Host smart-5220bd8a-2899-4185-9ca0-ef0faa9d014a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2634030861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.2634030861
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.1143019557
Short name T993
Test name
Test status
Simulation time 106925508 ps
CPU time 3.32 seconds
Started Mar 21 02:27:08 PM PDT 24
Finished Mar 21 02:27:11 PM PDT 24
Peak memory 220132 kb
Host smart-0cec65f0-ff33-4d8d-9454-6050beca444c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1143019557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dir
ect.1143019557
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.3130080789
Short name T942
Test name
Test status
Simulation time 10866308906 ps
CPU time 65.54 seconds
Started Mar 21 02:27:01 PM PDT 24
Finished Mar 21 02:28:06 PM PDT 24
Peak memory 216532 kb
Host smart-e676efd2-00ad-41e4-9889-920c1d23d507
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3130080789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.3130080789
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.2078412251
Short name T376
Test name
Test status
Simulation time 3876054863 ps
CPU time 8.61 seconds
Started Mar 21 02:27:03 PM PDT 24
Finished Mar 21 02:27:12 PM PDT 24
Peak memory 216524 kb
Host smart-c51dc892-b3d8-47a9-8a41-8acfd0c08e4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2078412251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.2078412251
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.1216802422
Short name T602
Test name
Test status
Simulation time 1891037823 ps
CPU time 2.49 seconds
Started Mar 21 02:27:10 PM PDT 24
Finished Mar 21 02:27:12 PM PDT 24
Peak memory 216528 kb
Host smart-20783e4c-d846-43ac-b8fe-c71d542c1c2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216802422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.1216802422
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.451168246
Short name T348
Test name
Test status
Simulation time 44832118 ps
CPU time 0.74 seconds
Started Mar 21 02:27:00 PM PDT 24
Finished Mar 21 02:27:01 PM PDT 24
Peak memory 205760 kb
Host smart-502d2867-6432-497d-b475-7fcd8d37b116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=451168246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.451168246
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.3193488035
Short name T709
Test name
Test status
Simulation time 83936241 ps
CPU time 2.65 seconds
Started Mar 21 02:27:05 PM PDT 24
Finished Mar 21 02:27:08 PM PDT 24
Peak memory 234420 kb
Host smart-96e460ea-4a37-4f05-b6f7-f8cb719d910f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3193488035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.3193488035
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.1025021519
Short name T696
Test name
Test status
Simulation time 12671989 ps
CPU time 0.72 seconds
Started Mar 21 02:27:14 PM PDT 24
Finished Mar 21 02:27:15 PM PDT 24
Peak memory 205408 kb
Host smart-37deb202-d120-4e55-a391-d11716a85de1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025021519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.
1025021519
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.1505302975
Short name T665
Test name
Test status
Simulation time 106855686 ps
CPU time 3.17 seconds
Started Mar 21 02:27:23 PM PDT 24
Finished Mar 21 02:27:27 PM PDT 24
Peak memory 233924 kb
Host smart-9fdaa831-9415-4eca-b1e5-67b129382bac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1505302975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.1505302975
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.2147509293
Short name T728
Test name
Test status
Simulation time 34405949 ps
CPU time 0.73 seconds
Started Mar 21 02:27:10 PM PDT 24
Finished Mar 21 02:27:10 PM PDT 24
Peak memory 205564 kb
Host smart-62b37d41-dc02-43e9-831b-a29712dc89e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2147509293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.2147509293
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.427269697
Short name T93
Test name
Test status
Simulation time 29009406589 ps
CPU time 78.98 seconds
Started Mar 21 02:27:18 PM PDT 24
Finished Mar 21 02:28:37 PM PDT 24
Peak memory 249356 kb
Host smart-c9812bce-730c-4fa6-b45f-675fe6518fd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427269697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.427269697
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.3349644818
Short name T540
Test name
Test status
Simulation time 55778290791 ps
CPU time 109.58 seconds
Started Mar 21 02:27:21 PM PDT 24
Finished Mar 21 02:29:11 PM PDT 24
Peak memory 249436 kb
Host smart-04e631fd-868f-48fc-93fa-5367edd99133
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3349644818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.3349644818
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.2142908474
Short name T229
Test name
Test status
Simulation time 15223906015 ps
CPU time 98.89 seconds
Started Mar 21 02:27:17 PM PDT 24
Finished Mar 21 02:28:56 PM PDT 24
Peak memory 255472 kb
Host smart-48f52d11-adb5-4a95-87f1-e311b73fa182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142908474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idl
e.2142908474
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.2083560233
Short name T944
Test name
Test status
Simulation time 18316864104 ps
CPU time 50.66 seconds
Started Mar 21 02:27:21 PM PDT 24
Finished Mar 21 02:28:11 PM PDT 24
Peak memory 246792 kb
Host smart-0a040536-ee21-48ab-bbd9-f3d50663d08c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083560233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.2083560233
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_intercept.2257045303
Short name T509
Test name
Test status
Simulation time 1217820620 ps
CPU time 4.25 seconds
Started Mar 21 02:27:16 PM PDT 24
Finished Mar 21 02:27:21 PM PDT 24
Peak memory 233332 kb
Host smart-d83fd810-9040-4c17-a59f-40bbd509caab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2257045303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.2257045303
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.3363943373
Short name T455
Test name
Test status
Simulation time 157733296 ps
CPU time 3.27 seconds
Started Mar 21 02:27:14 PM PDT 24
Finished Mar 21 02:27:18 PM PDT 24
Peak memory 224720 kb
Host smart-9312bead-6524-494d-ae95-0f5d61c373a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3363943373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.3363943373
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.3649855993
Short name T530
Test name
Test status
Simulation time 6614929253 ps
CPU time 21.41 seconds
Started Mar 21 02:27:15 PM PDT 24
Finished Mar 21 02:27:37 PM PDT 24
Peak memory 239048 kb
Host smart-fbfdf38f-81b8-4663-bf16-cf0f80fd3ea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3649855993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swa
p.3649855993
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.2531463703
Short name T937
Test name
Test status
Simulation time 76873241653 ps
CPU time 49.48 seconds
Started Mar 21 02:27:15 PM PDT 24
Finished Mar 21 02:28:05 PM PDT 24
Peak memory 241200 kb
Host smart-3ee1503a-3bc7-4561-9d11-bdec619f9199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2531463703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.2531463703
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.1526876116
Short name T710
Test name
Test status
Simulation time 1460422009 ps
CPU time 6.38 seconds
Started Mar 21 02:27:18 PM PDT 24
Finished Mar 21 02:27:25 PM PDT 24
Peak memory 220296 kb
Host smart-bfbd717f-cfa2-4899-8a1c-0c5040c6bdff
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1526876116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dir
ect.1526876116
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.136393068
Short name T176
Test name
Test status
Simulation time 79279270 ps
CPU time 0.98 seconds
Started Mar 21 02:27:18 PM PDT 24
Finished Mar 21 02:27:19 PM PDT 24
Peak memory 206892 kb
Host smart-6ac0c15a-0ba1-4dce-b812-705c48588a37
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136393068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stres
s_all.136393068
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.3535371204
Short name T609
Test name
Test status
Simulation time 9245462825 ps
CPU time 17.45 seconds
Started Mar 21 02:27:07 PM PDT 24
Finished Mar 21 02:27:25 PM PDT 24
Peak memory 216536 kb
Host smart-d6c61873-f287-41f1-b5c8-8e121d91f2e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3535371204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.3535371204
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.650580123
Short name T874
Test name
Test status
Simulation time 2474399932 ps
CPU time 13.12 seconds
Started Mar 21 02:27:08 PM PDT 24
Finished Mar 21 02:27:22 PM PDT 24
Peak memory 216528 kb
Host smart-b1f8cc5a-ab00-44de-b86b-fe9037b28c28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=650580123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.650580123
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.493260287
Short name T621
Test name
Test status
Simulation time 189318757 ps
CPU time 2.11 seconds
Started Mar 21 02:27:07 PM PDT 24
Finished Mar 21 02:27:10 PM PDT 24
Peak memory 216472 kb
Host smart-13778fca-f0a2-4f18-8860-6f1119bde57e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=493260287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.493260287
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.1207953818
Short name T428
Test name
Test status
Simulation time 39017988 ps
CPU time 0.88 seconds
Started Mar 21 02:27:02 PM PDT 24
Finished Mar 21 02:27:04 PM PDT 24
Peak memory 205768 kb
Host smart-0dc60f39-620a-49ed-a970-56e0f63f6c86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207953818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.1207953818
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.2007817095
Short name T241
Test name
Test status
Simulation time 4128801950 ps
CPU time 12.75 seconds
Started Mar 21 02:27:16 PM PDT 24
Finished Mar 21 02:27:29 PM PDT 24
Peak memory 218708 kb
Host smart-2c5dd98f-7e29-47bc-9c26-39be8e1b22a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007817095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.2007817095
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.2889781929
Short name T644
Test name
Test status
Simulation time 17020741 ps
CPU time 0.7 seconds
Started Mar 21 02:27:18 PM PDT 24
Finished Mar 21 02:27:18 PM PDT 24
Peak memory 205452 kb
Host smart-7bf698de-02e3-4517-94cb-598b9bceba01
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889781929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.
2889781929
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.381911920
Short name T381
Test name
Test status
Simulation time 183709746 ps
CPU time 3.02 seconds
Started Mar 21 02:27:21 PM PDT 24
Finished Mar 21 02:27:24 PM PDT 24
Peak memory 217768 kb
Host smart-6b294e7a-5ec4-482b-b0fc-b571d2272def
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381911920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.381911920
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.4107795131
Short name T829
Test name
Test status
Simulation time 43722393 ps
CPU time 0.75 seconds
Started Mar 21 02:27:21 PM PDT 24
Finished Mar 21 02:27:22 PM PDT 24
Peak memory 206624 kb
Host smart-5d7b148e-c1af-4367-9972-08d904f372a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4107795131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.4107795131
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.3880341395
Short name T309
Test name
Test status
Simulation time 224192023472 ps
CPU time 331.68 seconds
Started Mar 21 02:27:22 PM PDT 24
Finished Mar 21 02:32:54 PM PDT 24
Peak memory 264644 kb
Host smart-71ed9bc5-6b40-4afc-ac52-9bcf4fee57bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3880341395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.3880341395
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.427544454
Short name T780
Test name
Test status
Simulation time 20910281610 ps
CPU time 47.66 seconds
Started Mar 21 02:27:18 PM PDT 24
Finished Mar 21 02:28:06 PM PDT 24
Peak memory 233020 kb
Host smart-87367011-69ea-4e6f-9afd-fa69d49e6742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427544454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.427544454
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.1181522408
Short name T713
Test name
Test status
Simulation time 48819198841 ps
CPU time 295.86 seconds
Started Mar 21 02:27:18 PM PDT 24
Finished Mar 21 02:32:13 PM PDT 24
Peak memory 257624 kb
Host smart-db0b608a-1658-4c6f-aadf-d028d047ad2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1181522408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idl
e.1181522408
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.1373208478
Short name T345
Test name
Test status
Simulation time 5004474327 ps
CPU time 18.95 seconds
Started Mar 21 02:27:22 PM PDT 24
Finished Mar 21 02:27:41 PM PDT 24
Peak memory 241140 kb
Host smart-61b8791a-8b94-4049-ba3c-56ddcdd1d24b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1373208478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.1373208478
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_intercept.1614235525
Short name T12
Test name
Test status
Simulation time 1890502574 ps
CPU time 6.91 seconds
Started Mar 21 02:27:16 PM PDT 24
Finished Mar 21 02:27:23 PM PDT 24
Peak memory 239696 kb
Host smart-6466c439-d13a-40d8-8f0d-3f1a3af440ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1614235525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.1614235525
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.1726267531
Short name T266
Test name
Test status
Simulation time 415739890 ps
CPU time 7.22 seconds
Started Mar 21 02:27:14 PM PDT 24
Finished Mar 21 02:27:21 PM PDT 24
Peak memory 248824 kb
Host smart-4bfb03a2-2db7-4653-86b2-816c96bbf9f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1726267531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.1726267531
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.2980673397
Short name T448
Test name
Test status
Simulation time 2311374343 ps
CPU time 3.94 seconds
Started Mar 21 02:27:14 PM PDT 24
Finished Mar 21 02:27:19 PM PDT 24
Peak memory 232992 kb
Host smart-d6195308-6a16-4097-918d-59e8127a1ee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2980673397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swa
p.2980673397
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.2332457262
Short name T533
Test name
Test status
Simulation time 12001376875 ps
CPU time 25.82 seconds
Started Mar 21 02:27:16 PM PDT 24
Finished Mar 21 02:27:42 PM PDT 24
Peak memory 232960 kb
Host smart-93e1769e-1745-42b6-b3e6-b06bc1cf5891
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2332457262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.2332457262
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.1942807153
Short name T405
Test name
Test status
Simulation time 3115216548 ps
CPU time 5.38 seconds
Started Mar 21 02:27:17 PM PDT 24
Finished Mar 21 02:27:23 PM PDT 24
Peak memory 220892 kb
Host smart-00381f1e-b7ff-4dce-b88f-1511807cd9ad
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1942807153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dir
ect.1942807153
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.2245056777
Short name T157
Test name
Test status
Simulation time 3303726016 ps
CPU time 24.31 seconds
Started Mar 21 02:27:22 PM PDT 24
Finished Mar 21 02:27:46 PM PDT 24
Peak memory 241160 kb
Host smart-0658a33b-5434-4173-9146-52e5fd79e2d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245056777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stre
ss_all.2245056777
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.439589833
Short name T943
Test name
Test status
Simulation time 9018694484 ps
CPU time 40.47 seconds
Started Mar 21 02:27:19 PM PDT 24
Finished Mar 21 02:28:00 PM PDT 24
Peak memory 216680 kb
Host smart-66b75e3d-fc0a-453d-b9cb-22b0cc330c12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439589833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.439589833
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.4145635308
Short name T14
Test name
Test status
Simulation time 113783545 ps
CPU time 1.41 seconds
Started Mar 21 02:27:16 PM PDT 24
Finished Mar 21 02:27:17 PM PDT 24
Peak memory 207976 kb
Host smart-74fac726-e845-45da-a372-ea9c83dd0953
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4145635308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.4145635308
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.703590425
Short name T599
Test name
Test status
Simulation time 711539371 ps
CPU time 3.3 seconds
Started Mar 21 02:27:14 PM PDT 24
Finished Mar 21 02:27:17 PM PDT 24
Peak memory 216432 kb
Host smart-f3a59b91-d034-4a25-932b-764bb69f2eba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=703590425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.703590425
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.1374271471
Short name T521
Test name
Test status
Simulation time 154568493 ps
CPU time 1.01 seconds
Started Mar 21 02:27:24 PM PDT 24
Finished Mar 21 02:27:25 PM PDT 24
Peak memory 206792 kb
Host smart-b567f812-53f7-4626-a3bc-618d81cb1242
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1374271471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.1374271471
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.1171047548
Short name T572
Test name
Test status
Simulation time 5606053372 ps
CPU time 18.48 seconds
Started Mar 21 02:27:14 PM PDT 24
Finished Mar 21 02:27:32 PM PDT 24
Peak memory 221404 kb
Host smart-83def5a1-f3de-46c1-bcae-7a1c7830b2ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1171047548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.1171047548
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.2997268496
Short name T467
Test name
Test status
Simulation time 258614103 ps
CPU time 0.75 seconds
Started Mar 21 02:27:26 PM PDT 24
Finished Mar 21 02:27:27 PM PDT 24
Peak memory 204860 kb
Host smart-8b313629-8b01-44b1-81d3-07685977727e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997268496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.
2997268496
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.1781065275
Short name T420
Test name
Test status
Simulation time 3773279380 ps
CPU time 7.64 seconds
Started Mar 21 02:27:28 PM PDT 24
Finished Mar 21 02:27:37 PM PDT 24
Peak memory 219864 kb
Host smart-c7a304f9-cf60-4fc5-9eab-61e24f4f9276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1781065275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.1781065275
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.2405723990
Short name T870
Test name
Test status
Simulation time 24806403 ps
CPU time 0.75 seconds
Started Mar 21 02:27:21 PM PDT 24
Finished Mar 21 02:27:22 PM PDT 24
Peak memory 206452 kb
Host smart-c7986450-5438-492c-8519-d01079714928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405723990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.2405723990
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.4150250832
Short name T791
Test name
Test status
Simulation time 15167486215 ps
CPU time 26.26 seconds
Started Mar 21 02:27:24 PM PDT 24
Finished Mar 21 02:27:51 PM PDT 24
Peak memory 232896 kb
Host smart-6469eadc-de94-42a4-b9aa-76f1f3483e52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4150250832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.4150250832
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.3036002144
Short name T196
Test name
Test status
Simulation time 11399343688 ps
CPU time 93.75 seconds
Started Mar 21 02:27:29 PM PDT 24
Finished Mar 21 02:29:04 PM PDT 24
Peak memory 255096 kb
Host smart-ac732686-792d-4538-86d8-3a60cc71da65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3036002144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.3036002144
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.2716966904
Short name T25
Test name
Test status
Simulation time 2248854993 ps
CPU time 50.33 seconds
Started Mar 21 02:27:27 PM PDT 24
Finished Mar 21 02:28:19 PM PDT 24
Peak memory 251588 kb
Host smart-9286ed58-7710-47e4-93a7-f78a1a63b00f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716966904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idl
e.2716966904
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.3721250228
Short name T768
Test name
Test status
Simulation time 1892170697 ps
CPU time 23.39 seconds
Started Mar 21 02:27:35 PM PDT 24
Finished Mar 21 02:27:58 PM PDT 24
Peak memory 239228 kb
Host smart-b9edf5aa-1688-406c-9675-48607a05a291
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3721250228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.3721250228
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_intercept.76757955
Short name T440
Test name
Test status
Simulation time 3684159645 ps
CPU time 13.12 seconds
Started Mar 21 02:27:21 PM PDT 24
Finished Mar 21 02:27:34 PM PDT 24
Peak memory 235272 kb
Host smart-e3e58246-c828-4305-8911-673c636e9aa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76757955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.76757955
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.1039388714
Short name T415
Test name
Test status
Simulation time 438408389 ps
CPU time 6.54 seconds
Started Mar 21 02:27:23 PM PDT 24
Finished Mar 21 02:27:30 PM PDT 24
Peak memory 241016 kb
Host smart-4ee682a1-f288-449a-a7dd-25c2ddf0f7e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039388714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.1039388714
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.3843171756
Short name T853
Test name
Test status
Simulation time 81594913580 ps
CPU time 48.35 seconds
Started Mar 21 02:27:23 PM PDT 24
Finished Mar 21 02:28:12 PM PDT 24
Peak memory 248504 kb
Host smart-20f59782-c154-4161-82ff-4ff416e51de6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3843171756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swa
p.3843171756
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.1123838027
Short name T227
Test name
Test status
Simulation time 16353350924 ps
CPU time 26.02 seconds
Started Mar 21 02:27:15 PM PDT 24
Finished Mar 21 02:27:41 PM PDT 24
Peak memory 233524 kb
Host smart-acaf50f8-1552-41d6-9d5a-0c376a15c4c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1123838027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.1123838027
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.1528215037
Short name T623
Test name
Test status
Simulation time 378913497 ps
CPU time 3.44 seconds
Started Mar 21 02:27:31 PM PDT 24
Finished Mar 21 02:27:35 PM PDT 24
Peak memory 223000 kb
Host smart-836743fd-bf22-4897-84ff-4a7573f4b25c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1528215037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir
ect.1528215037
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.2618860233
Short name T23
Test name
Test status
Simulation time 107388523130 ps
CPU time 550.46 seconds
Started Mar 21 02:27:28 PM PDT 24
Finished Mar 21 02:36:41 PM PDT 24
Peak memory 282328 kb
Host smart-1c867c80-25b4-4989-a848-47a0fbd5db56
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618860233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stre
ss_all.2618860233
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.3112234383
Short name T827
Test name
Test status
Simulation time 3259118309 ps
CPU time 31.99 seconds
Started Mar 21 02:27:22 PM PDT 24
Finished Mar 21 02:27:54 PM PDT 24
Peak memory 216548 kb
Host smart-f9c675d1-e63e-4ab9-acfe-9d891bda20ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3112234383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.3112234383
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.1766223005
Short name T585
Test name
Test status
Simulation time 2541515324 ps
CPU time 9.76 seconds
Started Mar 21 02:27:15 PM PDT 24
Finished Mar 21 02:27:25 PM PDT 24
Peak memory 216588 kb
Host smart-4194f012-4be4-4b3b-ab11-0b9bec56eca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1766223005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.1766223005
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.3058780880
Short name T323
Test name
Test status
Simulation time 1436839510 ps
CPU time 4.1 seconds
Started Mar 21 02:27:25 PM PDT 24
Finished Mar 21 02:27:29 PM PDT 24
Peak memory 216568 kb
Host smart-157bee7e-7b44-482e-b445-b9997ad008d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058780880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.3058780880
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.491806772
Short name T881
Test name
Test status
Simulation time 251920416 ps
CPU time 0.89 seconds
Started Mar 21 02:27:23 PM PDT 24
Finished Mar 21 02:27:24 PM PDT 24
Peak memory 205740 kb
Host smart-61e07851-2890-434b-8bc8-84cac40acae1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=491806772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.491806772
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.1504290120
Short name T749
Test name
Test status
Simulation time 204434217 ps
CPU time 4.41 seconds
Started Mar 21 02:27:17 PM PDT 24
Finished Mar 21 02:27:22 PM PDT 24
Peak memory 227648 kb
Host smart-c8ab0f8b-b141-4565-9034-aa0ea4bbd825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1504290120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.1504290120
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.995947654
Short name T346
Test name
Test status
Simulation time 12539607 ps
CPU time 0.71 seconds
Started Mar 21 02:27:28 PM PDT 24
Finished Mar 21 02:27:30 PM PDT 24
Peak memory 205408 kb
Host smart-21f1b3c9-f67e-474e-8e61-f86256f012bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995947654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.995947654
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.1964589434
Short name T519
Test name
Test status
Simulation time 496735855 ps
CPU time 3.4 seconds
Started Mar 21 02:27:26 PM PDT 24
Finished Mar 21 02:27:31 PM PDT 24
Peak memory 218848 kb
Host smart-ca8536ff-53d8-4002-a430-60755db5b7ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1964589434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.1964589434
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.3093536017
Short name T485
Test name
Test status
Simulation time 89387665 ps
CPU time 0.74 seconds
Started Mar 21 02:27:30 PM PDT 24
Finished Mar 21 02:27:33 PM PDT 24
Peak memory 205556 kb
Host smart-755d29ae-0191-433b-b50b-392cb9b7f975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3093536017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.3093536017
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.871557474
Short name T810
Test name
Test status
Simulation time 109158344079 ps
CPU time 145.34 seconds
Started Mar 21 02:27:35 PM PDT 24
Finished Mar 21 02:30:01 PM PDT 24
Peak memory 257144 kb
Host smart-b6d27f8e-a735-4bb7-b226-158e36c8ffda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=871557474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.871557474
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.1666020371
Short name T732
Test name
Test status
Simulation time 106488443635 ps
CPU time 350.57 seconds
Started Mar 21 02:27:28 PM PDT 24
Finished Mar 21 02:33:20 PM PDT 24
Peak memory 254736 kb
Host smart-9bd63000-691b-4f14-acd3-f0b3d1b756a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666020371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.1666020371
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.2369237030
Short name T501
Test name
Test status
Simulation time 20591062961 ps
CPU time 24.87 seconds
Started Mar 21 02:27:26 PM PDT 24
Finished Mar 21 02:27:52 PM PDT 24
Peak memory 237944 kb
Host smart-fef19415-8fee-4d07-9b26-4e9ec4fc5886
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369237030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.2369237030
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_intercept.1161326502
Short name T328
Test name
Test status
Simulation time 181004698 ps
CPU time 2.61 seconds
Started Mar 21 02:27:28 PM PDT 24
Finished Mar 21 02:27:32 PM PDT 24
Peak memory 217032 kb
Host smart-225674c0-fe70-4bac-ac4b-aa9a409c9f35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1161326502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.1161326502
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.2253949838
Short name T917
Test name
Test status
Simulation time 31257457928 ps
CPU time 20.92 seconds
Started Mar 21 02:27:28 PM PDT 24
Finished Mar 21 02:27:51 PM PDT 24
Peak memory 232944 kb
Host smart-56239713-d4ab-43b6-a7fc-80e894d0567a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253949838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.2253949838
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.4263538237
Short name T570
Test name
Test status
Simulation time 1300389523 ps
CPU time 3.34 seconds
Started Mar 21 02:27:27 PM PDT 24
Finished Mar 21 02:27:32 PM PDT 24
Peak memory 216980 kb
Host smart-e742d653-71aa-45eb-8217-cf87b07b4828
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4263538237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swa
p.4263538237
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.2419604303
Short name T879
Test name
Test status
Simulation time 609229425 ps
CPU time 3.36 seconds
Started Mar 21 02:27:34 PM PDT 24
Finished Mar 21 02:27:37 PM PDT 24
Peak memory 233668 kb
Host smart-7d8e56f5-b738-4c6e-a00e-1947f1a2b5da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2419604303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.2419604303
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.1007421863
Short name T754
Test name
Test status
Simulation time 5070821924 ps
CPU time 5.3 seconds
Started Mar 21 02:27:27 PM PDT 24
Finished Mar 21 02:27:33 PM PDT 24
Peak memory 220632 kb
Host smart-962fe860-fd89-4b17-bc26-57a69091f61e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1007421863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir
ect.1007421863
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.1214632771
Short name T174
Test name
Test status
Simulation time 320005176879 ps
CPU time 402.13 seconds
Started Mar 21 02:27:29 PM PDT 24
Finished Mar 21 02:34:13 PM PDT 24
Peak memory 263492 kb
Host smart-b6600bd9-1c53-416c-bd5e-026a5d064564
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214632771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stre
ss_all.1214632771
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.2898520983
Short name T761
Test name
Test status
Simulation time 5127945016 ps
CPU time 11.59 seconds
Started Mar 21 02:27:26 PM PDT 24
Finished Mar 21 02:27:39 PM PDT 24
Peak memory 216668 kb
Host smart-272a1fec-38f6-4aaf-818c-527d3a2dcb4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898520983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.2898520983
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.2939180745
Short name T661
Test name
Test status
Simulation time 13983661046 ps
CPU time 8.97 seconds
Started Mar 21 02:27:34 PM PDT 24
Finished Mar 21 02:27:43 PM PDT 24
Peak memory 216580 kb
Host smart-0554a01b-a5d4-448c-921a-c49301634730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2939180745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.2939180745
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.2654862094
Short name T838
Test name
Test status
Simulation time 78613894 ps
CPU time 2.43 seconds
Started Mar 21 02:27:29 PM PDT 24
Finished Mar 21 02:27:33 PM PDT 24
Peak memory 216580 kb
Host smart-b8a3edae-4dc2-4840-a385-a1f35b18113e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2654862094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.2654862094
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.2583992532
Short name T584
Test name
Test status
Simulation time 378054849 ps
CPU time 1.05 seconds
Started Mar 21 02:27:26 PM PDT 24
Finished Mar 21 02:27:28 PM PDT 24
Peak memory 206820 kb
Host smart-5ed26b1e-79c8-4b72-b112-cf72b2a49b51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2583992532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.2583992532
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.377382053
Short name T564
Test name
Test status
Simulation time 7427509180 ps
CPU time 24.6 seconds
Started Mar 21 02:27:29 PM PDT 24
Finished Mar 21 02:27:55 PM PDT 24
Peak memory 233032 kb
Host smart-f842ca68-ff7d-4be4-8662-1e732626a3d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377382053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.377382053
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.850348160
Short name T71
Test name
Test status
Simulation time 10477705 ps
CPU time 0.69 seconds
Started Mar 21 02:27:30 PM PDT 24
Finished Mar 21 02:27:32 PM PDT 24
Peak memory 205412 kb
Host smart-cdb626d1-26be-41ee-bbb4-6516837fcc00
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850348160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.850348160
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.1408332318
Short name T421
Test name
Test status
Simulation time 129523605 ps
CPU time 4.03 seconds
Started Mar 21 02:27:29 PM PDT 24
Finished Mar 21 02:27:34 PM PDT 24
Peak memory 234364 kb
Host smart-82f6deff-e17e-4a21-81bd-06f709abc490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408332318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.1408332318
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.144320194
Short name T553
Test name
Test status
Simulation time 22148140 ps
CPU time 0.76 seconds
Started Mar 21 02:27:27 PM PDT 24
Finished Mar 21 02:27:29 PM PDT 24
Peak memory 205884 kb
Host smart-790c68bc-7cef-44b9-b754-6ee2c863fe4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=144320194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.144320194
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.1070755033
Short name T481
Test name
Test status
Simulation time 5393105924 ps
CPU time 60.29 seconds
Started Mar 21 02:27:27 PM PDT 24
Finished Mar 21 02:28:29 PM PDT 24
Peak memory 257444 kb
Host smart-9fe57ccc-14da-4fc2-ab69-8a3e74c1ff69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1070755033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.1070755033
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.1895496083
Short name T974
Test name
Test status
Simulation time 10417918592 ps
CPU time 84.04 seconds
Started Mar 21 02:27:28 PM PDT 24
Finished Mar 21 02:28:54 PM PDT 24
Peak memory 252312 kb
Host smart-2515cee0-b56e-4c46-a7d6-985585786f8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1895496083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.1895496083
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.2831725980
Short name T273
Test name
Test status
Simulation time 4231118397 ps
CPU time 79.27 seconds
Started Mar 21 02:27:29 PM PDT 24
Finished Mar 21 02:28:50 PM PDT 24
Peak memory 252948 kb
Host smart-8d71a8c2-2035-4f61-bfe0-df0e16427c0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2831725980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idl
e.2831725980
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.2580757059
Short name T453
Test name
Test status
Simulation time 56331890964 ps
CPU time 70.83 seconds
Started Mar 21 02:27:28 PM PDT 24
Finished Mar 21 02:28:40 PM PDT 24
Peak memory 248268 kb
Host smart-6aa137af-f2fb-4a43-bfd7-8138ca123235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2580757059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.2580757059
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_intercept.1042454812
Short name T610
Test name
Test status
Simulation time 3130960210 ps
CPU time 7.4 seconds
Started Mar 21 02:27:29 PM PDT 24
Finished Mar 21 02:27:38 PM PDT 24
Peak memory 233964 kb
Host smart-aed7491c-22b5-4213-8e73-b3c0bfee9f03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1042454812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.1042454812
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.698953738
Short name T547
Test name
Test status
Simulation time 7516723634 ps
CPU time 21.22 seconds
Started Mar 21 02:27:29 PM PDT 24
Finished Mar 21 02:27:52 PM PDT 24
Peak memory 232376 kb
Host smart-7fabbf4a-7cbb-481e-8e4e-6ca7c35a16ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=698953738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.698953738
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.858831950
Short name T279
Test name
Test status
Simulation time 18185996607 ps
CPU time 16.86 seconds
Started Mar 21 02:27:27 PM PDT 24
Finished Mar 21 02:27:45 PM PDT 24
Peak memory 224776 kb
Host smart-9cde86a4-5ba5-4dee-8633-447d654bc113
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=858831950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swap
.858831950
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.1290373727
Short name T788
Test name
Test status
Simulation time 819707783 ps
CPU time 7.14 seconds
Started Mar 21 02:27:26 PM PDT 24
Finished Mar 21 02:27:34 PM PDT 24
Peak memory 236652 kb
Host smart-98fd07d4-90f4-4f7d-a199-1af52bdb0aa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1290373727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.1290373727
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.4192099730
Short name T756
Test name
Test status
Simulation time 926009995 ps
CPU time 4.5 seconds
Started Mar 21 02:27:30 PM PDT 24
Finished Mar 21 02:27:36 PM PDT 24
Peak memory 222400 kb
Host smart-e1248df0-86e8-4fca-8a3e-434edad4a863
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4192099730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dir
ect.4192099730
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.3388991531
Short name T843
Test name
Test status
Simulation time 14072238863 ps
CPU time 66.66 seconds
Started Mar 21 02:27:28 PM PDT 24
Finished Mar 21 02:28:36 PM PDT 24
Peak memory 216640 kb
Host smart-71afdd8d-ae9b-4c58-b930-6c92505b6afc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3388991531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.3388991531
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.30795722
Short name T363
Test name
Test status
Simulation time 6964412231 ps
CPU time 11.68 seconds
Started Mar 21 02:27:28 PM PDT 24
Finished Mar 21 02:27:42 PM PDT 24
Peak memory 216572 kb
Host smart-6492507a-4970-4b5f-94aa-afe973d79ac3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30795722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.30795722
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.3930720912
Short name T460
Test name
Test status
Simulation time 814758218 ps
CPU time 2.63 seconds
Started Mar 21 02:27:27 PM PDT 24
Finished Mar 21 02:27:31 PM PDT 24
Peak memory 216620 kb
Host smart-e9bada82-07c5-4074-a850-2fd01a0f3abe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930720912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.3930720912
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.1034342487
Short name T392
Test name
Test status
Simulation time 64519181 ps
CPU time 0.94 seconds
Started Mar 21 02:27:26 PM PDT 24
Finished Mar 21 02:27:28 PM PDT 24
Peak memory 205960 kb
Host smart-e14e90b8-bb07-4c64-ad08-54398ebc4339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034342487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.1034342487
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.3754848049
Short name T925
Test name
Test status
Simulation time 6638035233 ps
CPU time 24.63 seconds
Started Mar 21 02:27:26 PM PDT 24
Finished Mar 21 02:27:52 PM PDT 24
Peak memory 232776 kb
Host smart-bc3f1c36-ebb5-43f6-a202-4bf35ad78e84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3754848049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.3754848049
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.1154910078
Short name T852
Test name
Test status
Simulation time 20587041 ps
CPU time 0.72 seconds
Started Mar 21 02:23:35 PM PDT 24
Finished Mar 21 02:23:36 PM PDT 24
Peak memory 205772 kb
Host smart-6bf5cf76-0da6-4941-a344-bf5056a8bfbf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154910078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.1
154910078
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.3179314699
Short name T331
Test name
Test status
Simulation time 1987275855 ps
CPU time 10.07 seconds
Started Mar 21 02:23:37 PM PDT 24
Finished Mar 21 02:23:47 PM PDT 24
Peak memory 224608 kb
Host smart-3eb25db1-d986-4553-b630-09abdeefbf08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179314699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.3179314699
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.3936860035
Short name T912
Test name
Test status
Simulation time 21482886 ps
CPU time 0.82 seconds
Started Mar 21 02:23:34 PM PDT 24
Finished Mar 21 02:23:35 PM PDT 24
Peak memory 206612 kb
Host smart-faa8188d-c068-44cf-b85e-41519575c434
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936860035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.3936860035
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.1021362919
Short name T778
Test name
Test status
Simulation time 9866382330 ps
CPU time 51.55 seconds
Started Mar 21 02:23:38 PM PDT 24
Finished Mar 21 02:24:29 PM PDT 24
Peak memory 241216 kb
Host smart-5c8948bd-0bf2-4010-93f6-830428c147c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1021362919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.1021362919
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.667522775
Short name T801
Test name
Test status
Simulation time 113299707357 ps
CPU time 350.78 seconds
Started Mar 21 02:23:35 PM PDT 24
Finished Mar 21 02:29:26 PM PDT 24
Peak memory 265948 kb
Host smart-9b5a5be8-9c46-4654-b713-24d335532162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=667522775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle.
667522775
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.2334112355
Short name T994
Test name
Test status
Simulation time 18731366623 ps
CPU time 80.81 seconds
Started Mar 21 02:23:37 PM PDT 24
Finished Mar 21 02:24:58 PM PDT 24
Peak memory 249312 kb
Host smart-ecd987b6-ca5f-4901-a01a-715e128a8711
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334112355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.2334112355
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_intercept.3439543808
Short name T766
Test name
Test status
Simulation time 14640334325 ps
CPU time 12.66 seconds
Started Mar 21 02:23:35 PM PDT 24
Finished Mar 21 02:23:48 PM PDT 24
Peak memory 236076 kb
Host smart-8ab33b10-266b-40cc-9a6d-2d9f254aa9d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3439543808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.3439543808
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.2430946852
Short name T244
Test name
Test status
Simulation time 3328196402 ps
CPU time 8.79 seconds
Started Mar 21 02:23:37 PM PDT 24
Finished Mar 21 02:23:46 PM PDT 24
Peak memory 237076 kb
Host smart-4abaa921-a5f3-4b66-a610-6dce044a4c87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2430946852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.2430946852
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_mem_parity.2587322606
Short name T551
Test name
Test status
Simulation time 14651628 ps
CPU time 1.11 seconds
Started Mar 21 02:23:30 PM PDT 24
Finished Mar 21 02:23:32 PM PDT 24
Peak memory 216976 kb
Host smart-58edb752-6901-4dd6-b5fd-83ea30d2dac1
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587322606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 5.spi_device_mem_parity.2587322606
Directory /workspace/5.spi_device_mem_parity/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.3445248032
Short name T508
Test name
Test status
Simulation time 996752726 ps
CPU time 4.09 seconds
Started Mar 21 02:23:39 PM PDT 24
Finished Mar 21 02:23:43 PM PDT 24
Peak memory 217004 kb
Host smart-228d5f91-6d97-4669-b84a-ab0ed627faf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3445248032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.3445248032
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.2747268649
Short name T228
Test name
Test status
Simulation time 5540660999 ps
CPU time 13.42 seconds
Started Mar 21 02:23:37 PM PDT 24
Finished Mar 21 02:23:51 PM PDT 24
Peak memory 229592 kb
Host smart-b94c1339-7a69-4bf0-a405-52198adf8bc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747268649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.2747268649
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_ram_cfg.2325674773
Short name T463
Test name
Test status
Simulation time 111329234 ps
CPU time 0.7 seconds
Started Mar 21 02:23:30 PM PDT 24
Finished Mar 21 02:23:31 PM PDT 24
Peak memory 216344 kb
Host smart-d37e9d93-c624-4265-8a70-07ffa23c8893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2325674773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_ram_cfg.2325674773
Directory /workspace/5.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.2168411650
Short name T343
Test name
Test status
Simulation time 450425892 ps
CPU time 3.62 seconds
Started Mar 21 02:23:37 PM PDT 24
Finished Mar 21 02:23:40 PM PDT 24
Peak memory 220200 kb
Host smart-f8e9322c-4daf-485b-8f56-e0471c531af5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2168411650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_dire
ct.2168411650
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.2722532085
Short name T590
Test name
Test status
Simulation time 241378531385 ps
CPU time 244.13 seconds
Started Mar 21 02:23:35 PM PDT 24
Finished Mar 21 02:27:39 PM PDT 24
Peak memory 283172 kb
Host smart-696f6d4f-5b63-45c6-96db-88f73d1aaa15
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722532085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stres
s_all.2722532085
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.1500023042
Short name T835
Test name
Test status
Simulation time 229016089 ps
CPU time 2.64 seconds
Started Mar 21 02:23:36 PM PDT 24
Finished Mar 21 02:23:38 PM PDT 24
Peak memory 216388 kb
Host smart-dc5ef60e-8c66-4103-b3b1-ad7cfabc3c0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1500023042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.1500023042
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.3512571367
Short name T476
Test name
Test status
Simulation time 69681922282 ps
CPU time 13.77 seconds
Started Mar 21 02:23:37 PM PDT 24
Finished Mar 21 02:23:52 PM PDT 24
Peak memory 216548 kb
Host smart-05e56928-e4a2-4d2e-9823-ed6700624193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3512571367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.3512571367
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.3669861313
Short name T630
Test name
Test status
Simulation time 1082566685 ps
CPU time 3.07 seconds
Started Mar 21 02:23:36 PM PDT 24
Finished Mar 21 02:23:40 PM PDT 24
Peak memory 216496 kb
Host smart-0b9d9e36-4adf-45bb-873e-d3505fe9f132
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3669861313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.3669861313
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.778956227
Short name T782
Test name
Test status
Simulation time 20490361 ps
CPU time 0.73 seconds
Started Mar 21 02:23:37 PM PDT 24
Finished Mar 21 02:23:38 PM PDT 24
Peak memory 205740 kb
Host smart-e4b36a6f-a003-48fb-bbe3-6883818dfe26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778956227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.778956227
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.3562075537
Short name T807
Test name
Test status
Simulation time 823449110 ps
CPU time 6.47 seconds
Started Mar 21 02:23:36 PM PDT 24
Finished Mar 21 02:23:42 PM PDT 24
Peak memory 218756 kb
Host smart-0f7c8c1a-f872-4a30-ad0e-c0744b783d5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3562075537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.3562075537
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.2349245389
Short name T822
Test name
Test status
Simulation time 20350006 ps
CPU time 0.74 seconds
Started Mar 21 02:23:50 PM PDT 24
Finished Mar 21 02:23:51 PM PDT 24
Peak memory 205776 kb
Host smart-6e66cdba-ab45-4f82-b191-43ea48a68aec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349245389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.2
349245389
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.1259154521
Short name T373
Test name
Test status
Simulation time 285143040 ps
CPU time 3.02 seconds
Started Mar 21 02:23:35 PM PDT 24
Finished Mar 21 02:23:39 PM PDT 24
Peak memory 233976 kb
Host smart-ea8007c8-9e65-4c7e-8002-0fbed1b72903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1259154521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.1259154521
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.792908457
Short name T165
Test name
Test status
Simulation time 47309244 ps
CPU time 0.76 seconds
Started Mar 21 02:23:35 PM PDT 24
Finished Mar 21 02:23:36 PM PDT 24
Peak memory 205820 kb
Host smart-efebe907-003f-4424-968e-f0da40551be4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792908457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.792908457
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.4189898861
Short name T734
Test name
Test status
Simulation time 7102273949 ps
CPU time 36.82 seconds
Started Mar 21 02:23:36 PM PDT 24
Finished Mar 21 02:24:13 PM PDT 24
Peak memory 249352 kb
Host smart-909d1d7a-bf52-4aa0-b745-450693f7bd7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189898861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.4189898861
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.3498723387
Short name T938
Test name
Test status
Simulation time 33499693036 ps
CPU time 296.31 seconds
Started Mar 21 02:23:48 PM PDT 24
Finished Mar 21 02:28:45 PM PDT 24
Peak memory 273536 kb
Host smart-79cffef7-c807-48d5-9b15-52b0bfa9722d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3498723387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.3498723387
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.2123612686
Short name T92
Test name
Test status
Simulation time 17042331213 ps
CPU time 85.96 seconds
Started Mar 21 02:23:51 PM PDT 24
Finished Mar 21 02:25:18 PM PDT 24
Peak memory 267816 kb
Host smart-901b7f95-34e1-45f3-973b-553e57332f86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2123612686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle
.2123612686
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.2601616877
Short name T887
Test name
Test status
Simulation time 4490269224 ps
CPU time 30.4 seconds
Started Mar 21 02:23:37 PM PDT 24
Finished Mar 21 02:24:08 PM PDT 24
Peak memory 230984 kb
Host smart-e9b983b5-b1a6-4975-85f3-334bd3e19ac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2601616877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.2601616877
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_intercept.1175485804
Short name T214
Test name
Test status
Simulation time 2099407979 ps
CPU time 6.94 seconds
Started Mar 21 02:23:38 PM PDT 24
Finished Mar 21 02:23:46 PM PDT 24
Peak memory 224476 kb
Host smart-b194fbec-0c89-43fc-bef7-724c49842923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1175485804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.1175485804
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.217089765
Short name T195
Test name
Test status
Simulation time 455631310 ps
CPU time 7.26 seconds
Started Mar 21 02:23:36 PM PDT 24
Finished Mar 21 02:23:43 PM PDT 24
Peak memory 239944 kb
Host smart-b5a0068d-5737-4cf6-8451-d3f6eaba9e61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=217089765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.217089765
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_mem_parity.4176765226
Short name T905
Test name
Test status
Simulation time 31355766 ps
CPU time 1.06 seconds
Started Mar 21 02:23:38 PM PDT 24
Finished Mar 21 02:23:40 PM PDT 24
Peak memory 218204 kb
Host smart-06920435-74e2-43e9-ad09-ea6f6575e722
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176765226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 6.spi_device_mem_parity.4176765226
Directory /workspace/6.spi_device_mem_parity/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.486524669
Short name T771
Test name
Test status
Simulation time 28505391115 ps
CPU time 22.32 seconds
Started Mar 21 02:23:37 PM PDT 24
Finished Mar 21 02:24:00 PM PDT 24
Peak memory 233860 kb
Host smart-8687978f-6ee4-4e80-b4c8-32cf243f4ab1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=486524669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap.
486524669
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.1050277705
Short name T847
Test name
Test status
Simulation time 50126207 ps
CPU time 2.58 seconds
Started Mar 21 02:23:38 PM PDT 24
Finished Mar 21 02:23:41 PM PDT 24
Peak memory 232888 kb
Host smart-35eaf4fe-7aa4-42d2-a3e1-79ee8b0e1cf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1050277705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.1050277705
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_ram_cfg.4082575817
Short name T893
Test name
Test status
Simulation time 16159781 ps
CPU time 0.75 seconds
Started Mar 21 02:23:36 PM PDT 24
Finished Mar 21 02:23:37 PM PDT 24
Peak memory 216404 kb
Host smart-b142e25d-7351-44d8-b309-9363b7fdaccb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082575817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_ram_cfg.4082575817
Directory /workspace/6.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.2252264635
Short name T896
Test name
Test status
Simulation time 380603038 ps
CPU time 3.39 seconds
Started Mar 21 02:23:36 PM PDT 24
Finished Mar 21 02:23:40 PM PDT 24
Peak memory 218904 kb
Host smart-ade24df0-9a17-4343-a78d-a0bbd6221c74
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2252264635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_dire
ct.2252264635
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.854030891
Short name T849
Test name
Test status
Simulation time 4403437233 ps
CPU time 60.14 seconds
Started Mar 21 02:23:50 PM PDT 24
Finished Mar 21 02:24:51 PM PDT 24
Peak memory 241256 kb
Host smart-42e02ae3-5637-4710-991d-44658d75b31a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854030891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stress
_all.854030891
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.425225781
Short name T840
Test name
Test status
Simulation time 4356550048 ps
CPU time 25.27 seconds
Started Mar 21 02:23:38 PM PDT 24
Finished Mar 21 02:24:04 PM PDT 24
Peak memory 216704 kb
Host smart-6a20f55a-2cc9-431e-8a00-60819c3bd36c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=425225781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.425225781
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.592628654
Short name T6
Test name
Test status
Simulation time 1580382898 ps
CPU time 4.94 seconds
Started Mar 21 02:23:37 PM PDT 24
Finished Mar 21 02:23:42 PM PDT 24
Peak memory 216408 kb
Host smart-274996e6-d60b-4de5-8dae-a1dcd3772622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=592628654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.592628654
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.311527780
Short name T56
Test name
Test status
Simulation time 41593686 ps
CPU time 1.05 seconds
Started Mar 21 02:23:37 PM PDT 24
Finished Mar 21 02:23:38 PM PDT 24
Peak memory 207252 kb
Host smart-79f80c26-b1c0-452e-b982-9a3d46f41376
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311527780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.311527780
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.216042704
Short name T677
Test name
Test status
Simulation time 114306599 ps
CPU time 0.92 seconds
Started Mar 21 02:23:38 PM PDT 24
Finished Mar 21 02:23:40 PM PDT 24
Peak memory 205792 kb
Host smart-3e8e82c0-4e79-41c2-bf6d-99770484f08a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=216042704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.216042704
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.3193410273
Short name T624
Test name
Test status
Simulation time 11850544 ps
CPU time 0.71 seconds
Started Mar 21 02:23:51 PM PDT 24
Finished Mar 21 02:23:52 PM PDT 24
Peak memory 204852 kb
Host smart-89760a36-4be5-4024-aa2a-84ec313608b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193410273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.3
193410273
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.2169800513
Short name T524
Test name
Test status
Simulation time 216253007 ps
CPU time 2.62 seconds
Started Mar 21 02:23:50 PM PDT 24
Finished Mar 21 02:23:54 PM PDT 24
Peak memory 234260 kb
Host smart-43661588-cbf8-43cd-89fd-9acd962c4d2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2169800513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.2169800513
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.2872645082
Short name T338
Test name
Test status
Simulation time 37672646 ps
CPU time 0.77 seconds
Started Mar 21 02:23:51 PM PDT 24
Finished Mar 21 02:23:53 PM PDT 24
Peak memory 206916 kb
Host smart-49363088-97b3-43de-b992-73bf4aa9f04c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872645082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.2872645082
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.3209602917
Short name T222
Test name
Test status
Simulation time 53671660699 ps
CPU time 132.61 seconds
Started Mar 21 02:23:50 PM PDT 24
Finished Mar 21 02:26:03 PM PDT 24
Peak memory 265772 kb
Host smart-a333147c-dc74-4a63-9ffa-00acc37bd157
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3209602917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.3209602917
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.3043918650
Short name T135
Test name
Test status
Simulation time 14869579945 ps
CPU time 134.95 seconds
Started Mar 21 02:23:59 PM PDT 24
Finished Mar 21 02:26:14 PM PDT 24
Peak memory 249428 kb
Host smart-663dd85a-0d98-4364-a4e9-fcfad3ff9a67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3043918650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.3043918650
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.3206101987
Short name T271
Test name
Test status
Simulation time 151042837538 ps
CPU time 310.44 seconds
Started Mar 21 02:23:48 PM PDT 24
Finished Mar 21 02:28:59 PM PDT 24
Peak memory 255344 kb
Host smart-af31efc5-4403-4cfa-a2a2-b3d154cd4cb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3206101987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle
.3206101987
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.1405671646
Short name T580
Test name
Test status
Simulation time 21016569287 ps
CPU time 29.58 seconds
Started Mar 21 02:23:52 PM PDT 24
Finished Mar 21 02:24:22 PM PDT 24
Peak memory 233008 kb
Host smart-33ca8167-349f-4258-ae9a-ed1c4a05a4b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1405671646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.1405671646
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_intercept.1247384559
Short name T678
Test name
Test status
Simulation time 637023141 ps
CPU time 2.74 seconds
Started Mar 21 02:23:50 PM PDT 24
Finished Mar 21 02:23:53 PM PDT 24
Peak memory 216724 kb
Host smart-49b47ecd-264e-473f-a7fd-0673911c5b9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1247384559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.1247384559
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.2262136389
Short name T693
Test name
Test status
Simulation time 456161879 ps
CPU time 2.33 seconds
Started Mar 21 02:23:49 PM PDT 24
Finished Mar 21 02:23:52 PM PDT 24
Peak memory 216820 kb
Host smart-6dfe8897-22e5-465a-9d5d-8ecd827f14d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2262136389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.2262136389
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_mem_parity.312994174
Short name T27
Test name
Test status
Simulation time 23328945 ps
CPU time 1.08 seconds
Started Mar 21 02:23:50 PM PDT 24
Finished Mar 21 02:23:51 PM PDT 24
Peak memory 218188 kb
Host smart-8310d3b4-84ec-4402-93b2-2cccf1836ce2
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312994174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.spi_device_mem_parity.312994174
Directory /workspace/7.spi_device_mem_parity/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.2676168036
Short name T682
Test name
Test status
Simulation time 31185149022 ps
CPU time 19.63 seconds
Started Mar 21 02:23:51 PM PDT 24
Finished Mar 21 02:24:11 PM PDT 24
Peak memory 228476 kb
Host smart-c71db654-5ef6-4493-9172-47b45d9d0fa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2676168036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap
.2676168036
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.4264679788
Short name T254
Test name
Test status
Simulation time 2765437835 ps
CPU time 7.59 seconds
Started Mar 21 02:23:50 PM PDT 24
Finished Mar 21 02:23:59 PM PDT 24
Peak memory 221060 kb
Host smart-a192e4b7-7c12-43c2-a376-0854894dbb9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4264679788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.4264679788
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_ram_cfg.390584785
Short name T744
Test name
Test status
Simulation time 24727858 ps
CPU time 0.74 seconds
Started Mar 21 02:23:50 PM PDT 24
Finished Mar 21 02:23:51 PM PDT 24
Peak memory 216420 kb
Host smart-59552d19-2583-471f-9e30-5d9f433a3be0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390584785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_ram_cfg.390584785
Directory /workspace/7.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.585669292
Short name T620
Test name
Test status
Simulation time 2633054932 ps
CPU time 5.32 seconds
Started Mar 21 02:23:51 PM PDT 24
Finished Mar 21 02:23:57 PM PDT 24
Peak memory 223184 kb
Host smart-cd4a4feb-610b-4b0f-90ef-e58373fb6604
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=585669292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_direc
t.585669292
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.2916928425
Short name T161
Test name
Test status
Simulation time 333690619425 ps
CPU time 602.76 seconds
Started Mar 21 02:23:51 PM PDT 24
Finished Mar 21 02:33:54 PM PDT 24
Peak memory 268472 kb
Host smart-e0ddca16-7b59-4c7d-9901-b559e75d4e96
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916928425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stres
s_all.2916928425
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.3715428885
Short name T55
Test name
Test status
Simulation time 4113127096 ps
CPU time 35.39 seconds
Started Mar 21 02:23:50 PM PDT 24
Finished Mar 21 02:24:26 PM PDT 24
Peak memory 216524 kb
Host smart-42f28737-4713-4f2e-b9e9-a021c06409b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3715428885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.3715428885
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.2111361263
Short name T821
Test name
Test status
Simulation time 1833498593 ps
CPU time 4.82 seconds
Started Mar 21 02:23:51 PM PDT 24
Finished Mar 21 02:23:56 PM PDT 24
Peak memory 216440 kb
Host smart-d35b9752-de47-4ec8-96e7-d9a3333f42d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2111361263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.2111361263
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.1441257477
Short name T784
Test name
Test status
Simulation time 163292439 ps
CPU time 1.34 seconds
Started Mar 21 02:23:49 PM PDT 24
Finished Mar 21 02:23:51 PM PDT 24
Peak memory 216416 kb
Host smart-802b12df-4b11-4ca3-a24e-f9a08aa39fa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1441257477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.1441257477
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.3059809357
Short name T589
Test name
Test status
Simulation time 34421472 ps
CPU time 0.77 seconds
Started Mar 21 02:23:50 PM PDT 24
Finished Mar 21 02:23:51 PM PDT 24
Peak memory 205764 kb
Host smart-ea602740-68b6-4dcf-bd0f-929557bb8459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3059809357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.3059809357
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.199460732
Short name T265
Test name
Test status
Simulation time 7284784457 ps
CPU time 10.94 seconds
Started Mar 21 02:23:51 PM PDT 24
Finished Mar 21 02:24:02 PM PDT 24
Peak memory 219140 kb
Host smart-47872f91-597b-4252-a331-65d23d2b3128
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=199460732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.199460732
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.353459305
Short name T72
Test name
Test status
Simulation time 26162869 ps
CPU time 0.76 seconds
Started Mar 21 02:24:04 PM PDT 24
Finished Mar 21 02:24:05 PM PDT 24
Peak memory 204744 kb
Host smart-d2dee81f-0c5e-4aa5-922a-b0bd576ea202
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353459305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.353459305
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.883420604
Short name T850
Test name
Test status
Simulation time 6837439459 ps
CPU time 5.67 seconds
Started Mar 21 02:24:01 PM PDT 24
Finished Mar 21 02:24:07 PM PDT 24
Peak memory 222820 kb
Host smart-9f4bc5b3-db90-4263-87ec-c5288bcfcf69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=883420604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.883420604
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.2694244999
Short name T854
Test name
Test status
Simulation time 23219405 ps
CPU time 0.85 seconds
Started Mar 21 02:23:51 PM PDT 24
Finished Mar 21 02:23:52 PM PDT 24
Peak memory 206596 kb
Host smart-1e039c84-889e-44e1-9814-c59497d9dbfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2694244999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.2694244999
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.2104907629
Short name T206
Test name
Test status
Simulation time 737545818 ps
CPU time 13.14 seconds
Started Mar 21 02:24:03 PM PDT 24
Finished Mar 21 02:24:16 PM PDT 24
Peak memory 224608 kb
Host smart-0ec5ac3a-4b9a-4031-8236-4d5537212c14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2104907629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.2104907629
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.1158146359
Short name T928
Test name
Test status
Simulation time 59457760961 ps
CPU time 281.37 seconds
Started Mar 21 02:24:03 PM PDT 24
Finished Mar 21 02:28:45 PM PDT 24
Peak memory 263280 kb
Host smart-a5719ff2-df37-4ac3-a6ce-d77870f8f47c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1158146359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.1158146359
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.4000740102
Short name T60
Test name
Test status
Simulation time 49297796061 ps
CPU time 140.08 seconds
Started Mar 21 02:24:03 PM PDT 24
Finished Mar 21 02:26:24 PM PDT 24
Peak memory 263652 kb
Host smart-6452ece8-c2e8-4f9f-bf8f-d709e658aa70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4000740102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle
.4000740102
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.1590621894
Short name T562
Test name
Test status
Simulation time 843632115 ps
CPU time 24.13 seconds
Started Mar 21 02:24:03 PM PDT 24
Finished Mar 21 02:24:27 PM PDT 24
Peak memory 241024 kb
Host smart-ef4775b6-39a6-4a59-8a91-56eda4332f32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590621894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.1590621894
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_intercept.1095576774
Short name T205
Test name
Test status
Simulation time 5212550894 ps
CPU time 11.91 seconds
Started Mar 21 02:24:01 PM PDT 24
Finished Mar 21 02:24:13 PM PDT 24
Peak memory 224632 kb
Host smart-7c0a6fca-d719-4e0b-aa70-62ca99e7a795
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1095576774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.1095576774
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.4034626374
Short name T723
Test name
Test status
Simulation time 21677926597 ps
CPU time 15.03 seconds
Started Mar 21 02:24:02 PM PDT 24
Finished Mar 21 02:24:17 PM PDT 24
Peak memory 232940 kb
Host smart-d302c839-7e0d-434b-bb27-3092b020aa3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4034626374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.4034626374
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_mem_parity.1065444925
Short name T990
Test name
Test status
Simulation time 18073125 ps
CPU time 1.02 seconds
Started Mar 21 02:23:50 PM PDT 24
Finished Mar 21 02:23:51 PM PDT 24
Peak memory 218136 kb
Host smart-99f95d76-72ba-4d53-85df-ffdca3d3f182
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065444925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 8.spi_device_mem_parity.1065444925
Directory /workspace/8.spi_device_mem_parity/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.2300862994
Short name T858
Test name
Test status
Simulation time 3263679245 ps
CPU time 6.25 seconds
Started Mar 21 02:24:04 PM PDT 24
Finished Mar 21 02:24:10 PM PDT 24
Peak memory 233744 kb
Host smart-2554e09e-ee15-4063-a196-7f61ad2cf148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300862994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap
.2300862994
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.3651276922
Short name T258
Test name
Test status
Simulation time 5749186188 ps
CPU time 7.63 seconds
Started Mar 21 02:23:50 PM PDT 24
Finished Mar 21 02:23:58 PM PDT 24
Peak memory 218240 kb
Host smart-f3891755-5b9c-4d80-b8ff-3770283d5e16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3651276922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.3651276922
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_ram_cfg.3855700177
Short name T864
Test name
Test status
Simulation time 17819942 ps
CPU time 0.76 seconds
Started Mar 21 02:23:50 PM PDT 24
Finished Mar 21 02:23:51 PM PDT 24
Peak memory 216388 kb
Host smart-ff7b7fa0-b6d4-4338-b958-b10c9701ff41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3855700177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_ram_cfg.3855700177
Directory /workspace/8.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.3085914615
Short name T968
Test name
Test status
Simulation time 1382366895 ps
CPU time 6.24 seconds
Started Mar 21 02:24:03 PM PDT 24
Finished Mar 21 02:24:09 PM PDT 24
Peak memory 220508 kb
Host smart-08de1470-76bb-4d9f-8c8d-91ee7dea02ef
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3085914615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_dire
ct.3085914615
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.3341517745
Short name T469
Test name
Test status
Simulation time 6876067213 ps
CPU time 29.01 seconds
Started Mar 21 02:23:51 PM PDT 24
Finished Mar 21 02:24:21 PM PDT 24
Peak memory 216588 kb
Host smart-44828777-4474-4dc2-b0a8-cc98c6859ecc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341517745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.3341517745
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.2661135789
Short name T904
Test name
Test status
Simulation time 760141323 ps
CPU time 3.2 seconds
Started Mar 21 02:23:52 PM PDT 24
Finished Mar 21 02:23:56 PM PDT 24
Peak memory 216428 kb
Host smart-ff567366-667e-4f10-8200-6ed0cb3b138b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661135789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.2661135789
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.1184359506
Short name T352
Test name
Test status
Simulation time 43880991 ps
CPU time 1.48 seconds
Started Mar 21 02:23:51 PM PDT 24
Finished Mar 21 02:23:53 PM PDT 24
Peak memory 208500 kb
Host smart-652df34f-400e-40f8-ad55-496a1cfba615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1184359506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.1184359506
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.342375130
Short name T15
Test name
Test status
Simulation time 184504277 ps
CPU time 0.97 seconds
Started Mar 21 02:23:51 PM PDT 24
Finished Mar 21 02:23:52 PM PDT 24
Peak memory 206760 kb
Host smart-5ad8dbbb-aae9-4c42-9484-b518c9c9f31f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=342375130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.342375130
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.2919975753
Short name T220
Test name
Test status
Simulation time 3908447385 ps
CPU time 9.2 seconds
Started Mar 21 02:24:05 PM PDT 24
Finished Mar 21 02:24:14 PM PDT 24
Peak memory 235988 kb
Host smart-2a9c84ac-035d-4b7d-96a5-e1c8941782c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2919975753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.2919975753
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.1982576095
Short name T471
Test name
Test status
Simulation time 12249877 ps
CPU time 0.78 seconds
Started Mar 21 02:24:04 PM PDT 24
Finished Mar 21 02:24:05 PM PDT 24
Peak memory 205396 kb
Host smart-42853833-2001-4571-ac5b-266ee980a583
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982576095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.1
982576095
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.2898732621
Short name T641
Test name
Test status
Simulation time 325085970 ps
CPU time 3.38 seconds
Started Mar 21 02:24:02 PM PDT 24
Finished Mar 21 02:24:05 PM PDT 24
Peak memory 218068 kb
Host smart-5b7fd91e-66ad-4ff8-a229-c47c9d2a9995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898732621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.2898732621
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.3519281456
Short name T695
Test name
Test status
Simulation time 17288009 ps
CPU time 1.01 seconds
Started Mar 21 02:24:02 PM PDT 24
Finished Mar 21 02:24:04 PM PDT 24
Peak memory 206576 kb
Host smart-084cc5f3-5608-418b-8693-dd9571ba33f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3519281456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.3519281456
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.1242824733
Short name T223
Test name
Test status
Simulation time 376802755648 ps
CPU time 272.75 seconds
Started Mar 21 02:24:02 PM PDT 24
Finished Mar 21 02:28:34 PM PDT 24
Peak memory 250168 kb
Host smart-83d79b66-d505-465c-86ca-e2e504b88827
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242824733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.1242824733
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_intercept.928894418
Short name T240
Test name
Test status
Simulation time 2051187607 ps
CPU time 6.52 seconds
Started Mar 21 02:24:03 PM PDT 24
Finished Mar 21 02:24:09 PM PDT 24
Peak memory 224600 kb
Host smart-2c2259c5-5834-4d96-959a-dfdf96a8f3d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928894418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.928894418
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.1815947187
Short name T450
Test name
Test status
Simulation time 205725074 ps
CPU time 3.67 seconds
Started Mar 21 02:24:02 PM PDT 24
Finished Mar 21 02:24:05 PM PDT 24
Peak memory 233904 kb
Host smart-09bf5e2a-a245-46f7-959a-6b1de1a74461
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1815947187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.1815947187
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_mem_parity.3938013574
Short name T459
Test name
Test status
Simulation time 60764050 ps
CPU time 1.09 seconds
Started Mar 21 02:24:03 PM PDT 24
Finished Mar 21 02:24:04 PM PDT 24
Peak memory 216992 kb
Host smart-18bd331e-846d-4831-96da-5a5060037867
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938013574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 9.spi_device_mem_parity.3938013574
Directory /workspace/9.spi_device_mem_parity/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.3653698039
Short name T581
Test name
Test status
Simulation time 10309423461 ps
CPU time 9.31 seconds
Started Mar 21 02:24:04 PM PDT 24
Finished Mar 21 02:24:13 PM PDT 24
Peak memory 228172 kb
Host smart-7a5ac755-7a56-49a5-87c9-9c37f7891f9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3653698039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap
.3653698039
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.3046292216
Short name T436
Test name
Test status
Simulation time 240584593 ps
CPU time 3.58 seconds
Started Mar 21 02:24:03 PM PDT 24
Finished Mar 21 02:24:07 PM PDT 24
Peak memory 233776 kb
Host smart-f067a67e-e070-41d1-8108-6708c333a09c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3046292216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.3046292216
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_ram_cfg.910362874
Short name T368
Test name
Test status
Simulation time 18909549 ps
CPU time 0.75 seconds
Started Mar 21 02:24:04 PM PDT 24
Finished Mar 21 02:24:05 PM PDT 24
Peak memory 216308 kb
Host smart-f1eed6b0-50cd-4ca3-b91f-7f8ec887a7d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=910362874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_ram_cfg.910362874
Directory /workspace/9.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.1791990670
Short name T139
Test name
Test status
Simulation time 168154443 ps
CPU time 4.5 seconds
Started Mar 21 02:24:03 PM PDT 24
Finished Mar 21 02:24:08 PM PDT 24
Peak memory 222440 kb
Host smart-80325dfe-e7dc-4b62-bba0-34f14c697ce8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1791990670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_dire
ct.1791990670
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.1641741952
Short name T82
Test name
Test status
Simulation time 3658772829 ps
CPU time 58.36 seconds
Started Mar 21 02:24:02 PM PDT 24
Finished Mar 21 02:25:00 PM PDT 24
Peak memory 254640 kb
Host smart-9dae8192-9dc2-4812-8fe3-9453355270fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641741952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stres
s_all.1641741952
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.4165802735
Short name T935
Test name
Test status
Simulation time 10400047672 ps
CPU time 13.54 seconds
Started Mar 21 02:24:05 PM PDT 24
Finished Mar 21 02:24:19 PM PDT 24
Peak memory 216616 kb
Host smart-55145d64-e766-4743-b6c1-22900f2589e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4165802735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.4165802735
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.229874134
Short name T679
Test name
Test status
Simulation time 6467710844 ps
CPU time 6.29 seconds
Started Mar 21 02:24:05 PM PDT 24
Finished Mar 21 02:24:12 PM PDT 24
Peak memory 216624 kb
Host smart-3a0f518b-b01c-4ef7-803e-880cc7a71577
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=229874134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.229874134
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.702667867
Short name T7
Test name
Test status
Simulation time 106780547 ps
CPU time 1.2 seconds
Started Mar 21 02:24:04 PM PDT 24
Finished Mar 21 02:24:05 PM PDT 24
Peak memory 207696 kb
Host smart-430ce56e-49a5-4828-ae69-c5da513ec9aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=702667867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.702667867
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.1303641373
Short name T568
Test name
Test status
Simulation time 171305738 ps
CPU time 0.94 seconds
Started Mar 21 02:24:03 PM PDT 24
Finished Mar 21 02:24:04 PM PDT 24
Peak memory 206744 kb
Host smart-8a989452-c858-403e-b3c9-da2cde8211d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303641373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.1303641373
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.1980665251
Short name T699
Test name
Test status
Simulation time 6552892410 ps
CPU time 19.81 seconds
Started Mar 21 02:24:04 PM PDT 24
Finished Mar 21 02:24:24 PM PDT 24
Peak memory 219312 kb
Host smart-c23e8681-dbe4-42f3-90b8-eaecc35a84ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1980665251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.1980665251
Directory /workspace/9.spi_device_upload/latest
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