Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	6425990	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

6548138

1

T2

1

T3

892

T4

877

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	8423324	1			T1	1		T2	1		T3	12
values[0x0]	2276128	1			T1	1		T2	5		T3	446
values[0x1]	2274676	1			T2	5		T3	447		T4	429

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4641177	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

8332951

1

T2

2

T3

895

T4

878

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	52070	1			T4	5		T5	471		T8	429
valid_sources[0x01]	52099	1			T4	4		T5	536		T7	1
valid_sources[0x02]	48961	1			T4	6		T5	568		T8	384
valid_sources[0x03]	50342	1			T2	3		T4	6		T5	538
valid_sources[0x04]	51072	1			T4	6		T5	528		T8	442
valid_sources[0x05]	50609	1			T4	5		T5	525		T8	454
valid_sources[0x06]	54849	1			T4	3		T5	512		T8	340
valid_sources[0x07]	49300	1			T4	2		T5	577		T8	458
valid_sources[0x08]	49881	1			T4	7		T5	515		T8	399
valid_sources[0x09]	52986	1			T4	4		T5	559		T8	385
valid_sources[0x0a]	49474	1			T4	2		T5	544		T8	361
valid_sources[0x0b]	51446	1			T2	2		T4	3		T5	541
valid_sources[0x0c]	49724	1			T4	5		T5	534		T8	484
valid_sources[0x0d]	51397	1			T4	2		T5	523		T8	386
valid_sources[0x0e]	48243	1			T4	2		T5	568		T8	407
valid_sources[0x0f]	50312	1			T4	2		T5	576		T8	377
valid_sources[0x10]	50516	1			T4	2		T5	476		T8	418
valid_sources[0x11]	49907	1			T4	1		T5	532		T8	444
valid_sources[0x12]	50191	1			T4	2		T5	448		T8	415
valid_sources[0x13]	49364	1			T4	2		T5	511		T8	375
valid_sources[0x14]	53851	1			T4	6		T5	519		T7	4
valid_sources[0x15]	49246	1			T5	536		T7	1		T8	445
valid_sources[0x16]	49329	1			T4	5		T5	588		T8	439
valid_sources[0x17]	52279	1			T4	1		T5	554		T8	416
valid_sources[0x18]	48959	1			T4	5		T5	496		T8	419
valid_sources[0x19]	49481	1			T4	4		T5	508		T8	432
valid_sources[0x1a]	54177	1			T4	7		T5	524		T8	346
valid_sources[0x1b]	51055	1			T4	4		T5	508		T8	426
valid_sources[0x1c]	50881	1			T4	3		T5	508		T8	465
valid_sources[0x1d]	53113	1			T4	2		T5	564		T8	411
valid_sources[0x1e]	48892	1			T4	2		T5	468		T7	1
valid_sources[0x1f]	48279	1			T4	5		T5	482		T8	396
valid_sources[0x20]	53240	1			T4	2		T5	508		T8	415
valid_sources[0x21]	46898	1			T5	488		T7	1		T8	375
valid_sources[0x22]	53005	1			T4	1		T5	502		T7	1
valid_sources[0x23]	49241	1			T3	455		T4	3		T5	477
valid_sources[0x24]	51356	1			T5	494		T7	1		T8	387
valid_sources[0x25]	46471	1			T4	2		T5	590		T8	455
valid_sources[0x26]	52526	1			T4	4		T5	455		T8	415
valid_sources[0x27]	50990	1			T5	475		T8	446		T11	26
valid_sources[0x28]	49163	1			T4	5		T5	527		T8	454
valid_sources[0x29]	47911	1			T4	3		T5	620		T7	3
valid_sources[0x2a]	48347	1			T4	4		T5	521		T8	377
valid_sources[0x2b]	51115	1			T4	6		T5	507		T8	417
valid_sources[0x2c]	57577	1			T4	2		T5	487		T8	427
valid_sources[0x2d]	49502	1			T4	3		T5	595		T8	460
valid_sources[0x2e]	49390	1			T4	6		T5	495		T8	368
valid_sources[0x2f]	51456	1			T4	1		T5	519		T8	417
valid_sources[0x30]	50007	1			T4	5		T5	517		T8	444
valid_sources[0x31]	51181	1			T5	481		T8	364		T11	26
valid_sources[0x32]	49380	1			T4	5		T5	528		T8	431
valid_sources[0x33]	51128	1			T4	4		T5	485		T8	425
valid_sources[0x34]	55659	1			T4	4		T5	534		T8	445
valid_sources[0x35]	54423	1			T4	2		T5	497		T8	421
valid_sources[0x36]	53200	1			T4	1		T5	495		T8	430
valid_sources[0x37]	47252	1			T4	6		T5	506		T8	393
valid_sources[0x38]	49311	1			T4	1		T5	548		T8	361
valid_sources[0x39]	49414	1			T4	4		T5	610		T7	1
valid_sources[0x3a]	55944	1			T4	5		T5	496		T8	377
valid_sources[0x3b]	51157	1			T4	1		T5	504		T8	436
valid_sources[0x3c]	52089	1			T4	3		T5	556		T8	433
valid_sources[0x3d]	49902	1			T4	3		T5	575		T8	448
valid_sources[0x3e]	49326	1			T4	8		T5	461		T8	384
valid_sources[0x3f]	53190	1			T4	5		T5	476		T8	469
valid_sources[0x40]	49771	1			T4	1		T5	615		T7	1
valid_sources[0x41]	49641	1			T4	4		T5	521		T7	1
valid_sources[0x42]	51021	1			T4	3		T5	483		T8	402
valid_sources[0x43]	53565	1			T4	1		T5	479		T8	424
valid_sources[0x44]	53508	1			T4	3		T5	495		T8	441
valid_sources[0x45]	50626	1			T5	491		T8	389		T11	25
valid_sources[0x46]	53476	1			T4	2		T5	510		T8	391
valid_sources[0x47]	49021	1			T4	3		T5	525		T7	1
valid_sources[0x48]	52668	1			T4	2		T5	595		T8	459
valid_sources[0x49]	50112	1			T4	5		T5	466		T8	453
valid_sources[0x4a]	50559	1			T4	3		T5	561		T8	443
valid_sources[0x4b]	49985	1			T4	2		T5	515		T8	418
valid_sources[0x4c]	50029	1			T4	6		T5	552		T8	383
valid_sources[0x4d]	49667	1			T4	4		T5	557		T8	403
valid_sources[0x4e]	52732	1			T4	3		T5	576		T8	479
valid_sources[0x4f]	48222	1			T4	2		T5	542		T8	450
valid_sources[0x50]	53574	1			T4	4		T5	496		T8	375
valid_sources[0x51]	51169	1			T1	2		T4	2		T5	539
valid_sources[0x52]	51309	1			T4	3		T5	469		T8	489
valid_sources[0x53]	48781	1			T2	1		T4	7		T5	525
valid_sources[0x54]	48884	1			T4	5		T5	496		T8	354
valid_sources[0x55]	54054	1			T4	3		T5	481		T8	424
valid_sources[0x56]	50801	1			T4	5		T5	532		T8	384
valid_sources[0x57]	52048	1			T4	4		T5	535		T8	413
valid_sources[0x58]	50703	1			T4	4		T5	522		T8	343
valid_sources[0x59]	51086	1			T4	5		T5	481		T8	392
valid_sources[0x5a]	50257	1			T4	3		T5	454		T8	404
valid_sources[0x5b]	51684	1			T4	4		T5	531		T8	435
valid_sources[0x5c]	52540	1			T4	4		T5	491		T8	465
valid_sources[0x5d]	59244	1			T4	7		T5	524		T8	418
valid_sources[0x5e]	51832	1			T4	6		T5	506		T7	1
valid_sources[0x5f]	54205	1			T4	1		T5	467		T8	422
valid_sources[0x60]	48562	1			T4	5		T5	581		T8	370
valid_sources[0x61]	54240	1			T4	5		T5	533		T7	1
valid_sources[0x62]	52508	1			T4	4		T5	549		T8	406
valid_sources[0x63]	49656	1			T4	5		T5	568		T8	458
valid_sources[0x64]	54005	1			T4	3		T5	542		T7	2
valid_sources[0x65]	54048	1			T4	7		T5	509		T8	384
valid_sources[0x66]	49979	1			T4	3		T5	564		T8	451
valid_sources[0x67]	49692	1			T4	2		T5	532		T8	427
valid_sources[0x68]	46781	1			T4	1		T5	548		T8	426
valid_sources[0x69]	49909	1			T4	2		T5	573		T8	428
valid_sources[0x6a]	49588	1			T4	3		T5	461		T8	427
valid_sources[0x6b]	48307	1			T4	4		T5	490		T8	374
valid_sources[0x6c]	52101	1			T5	585		T8	352		T10	5
valid_sources[0x6d]	47486	1			T4	3		T5	548		T8	391
valid_sources[0x6e]	56473	1			T4	5		T5	512		T8	399
valid_sources[0x6f]	50817	1			T4	3		T5	530		T7	1
valid_sources[0x70]	48707	1			T4	1		T5	532		T8	393
valid_sources[0x71]	49760	1			T4	6		T5	470		T8	466
valid_sources[0x72]	53373	1			T4	1		T5	566		T8	369
valid_sources[0x73]	53155	1			T4	4		T5	482		T8	390
valid_sources[0x74]	52634	1			T4	3		T5	518		T8	429
valid_sources[0x75]	49848	1			T4	4		T5	581		T8	447
valid_sources[0x76]	46439	1			T4	4		T5	497		T8	443
valid_sources[0x77]	50472	1			T4	2		T5	490		T8	419
valid_sources[0x78]	48490	1			T4	6		T5	523		T8	436
valid_sources[0x79]	52608	1			T4	2		T5	493		T8	477
valid_sources[0x7a]	49875	1			T4	1		T5	489		T8	453
valid_sources[0x7b]	53583	1			T4	6		T5	550		T8	429
valid_sources[0x7c]	54461	1			T4	6		T5	458		T8	372
valid_sources[0x7d]	50287	1			T4	5		T5	559		T8	445
valid_sources[0x7e]	49732	1			T4	2		T5	470		T8	369
valid_sources[0x7f]	51157	1			T4	5		T5	584		T7	3
valid_sources[0x80]	51172	1			T4	2		T5	471		T7	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

2492136

1

T2

1

T3

3

T4

2

values[0x0]

all_enables

biggest_size

2045987

1

T3

444

T4

448

T5

17340

values[0x1]

all_enables

biggest_size

2010015

1

T3

445

T4

427

T5

16904