Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

6444022

1

T1

2

T2

10

T3

13

full_word

6547029

1

T2

1

T3

892

T4

877

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	12990651	1			T1	2		T2	11		T3	905
auto[TlIntgErrCmd]	126	1			T82	3		T83	2		T87	3
auto[TlIntgErrData]	145	1			T82	11		T83	2		T87	4
auto[TlIntgErrBoth]	129	1			T82	6		T83	6		T87	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8424742

1

T1

1

T2

1

T3

12

auto[1]

4566309

1

T1

1

T2

10

T3

893

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	5932362	1			T1	1		T3	9		T4	1
auto[TlIntgErrNone]	partial	auto[1]	511303	1			T1	1		T2	10		T3	4
auto[TlIntgErrNone]	full_word	auto[0]	2492183	1			T2	1		T3	3		T4	2
auto[TlIntgErrNone]	full_word	auto[1]	4054803	1			T3	889		T4	875		T5	34244
auto[TlIntgErrCmd]	partial	auto[0]	55	1			T87	1		T88	5		T92	3
auto[TlIntgErrCmd]	partial	auto[1]	62	1			T82	3		T83	2		T87	1
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T151	2		T152	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T87	1		T92	1		T153	1
auto[TlIntgErrData]	partial	auto[0]	68	1			T82	7		T83	1		T87	2
auto[TlIntgErrData]	partial	auto[1]	57	1			T82	4		T87	2		T88	2
auto[TlIntgErrData]	full_word	auto[0]	8	1			T83	1		T88	1		T92	1
auto[TlIntgErrData]	full_word	auto[1]	12	1			T88	1		T92	1		T105	1
auto[TlIntgErrBoth]	partial	auto[0]	56	1			T82	1		T83	3		T87	1
auto[TlIntgErrBoth]	partial	auto[1]	59	1			T82	2		T83	3		T87	2
auto[TlIntgErrBoth]	full_word	auto[0]	7	1			T82	2		T105	1		T154	1
auto[TlIntgErrBoth]	full_word	auto[1]	7	1			T82	1		T92	1		T105	1