Unified Coverage Report :: Module :: prim_pulse_sync

Module : prim_pulse_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_flash_readbuf_watermark_pulse_sync	100.00	100.00	100.00			100.00	100.00
tb.dut.u_flash_readbuf_flip_pulse_sync	100.00	100.00	100.00			100.00	100.00
tb.dut.u_upload.u_payloadptr_clr_psync	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.69	94.25	84.31	96.94		87.50	95.45	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.69	94.25	84.31	96.94		87.50	95.45	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_upload.u_payloadptr_clr_psync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.37	100.00	86.11		100.00	95.74	100.00	u_upload

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

Line Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Module : prim_pulse_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T5
0	1	Covered	T5,T8,T11
1	0	Covered	T5,T8,T11
1	1	Covered	T5,T8,T11

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T8,T11
1	0	Covered	T5,T8,T11
1	1	Covered	T5,T8,T11

---

Branch Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T4,T5

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_pulse_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1731202557	3390	0	0
SrcPulseCheck_M	544143843	3390	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1731202557	3390	0	0
T5	522705	30	0	0
T6	68813	0	0	0
T7	887	0	0	0
T8	798326	25	0	0
T9	116208	0	0	0
T10	4196	0	0	0
T11	120165	4	0	0
T13	0	14	0	0
T14	175812	7	0	0
T15	546450	4	0	0
T16	38890	0	0	0
T17	1359	0	0	0
T18	932648	0	0	0
T27	267394	7	0	0
T28	1568618	0	0	0
T29	1587790	6	0	0
T30	0	6	0	0
T31	901152	22	0	0
T39	0	7	0	0
T40	0	7	0	0
T41	1682900	0	0	0
T43	0	19	0	0
T52	0	1	0	0
T59	16302	0	0	0
T69	11182	0	0	0
T70	252732	0	0	0
T122	0	6	0	0
T123	0	7	0	0
T124	0	5	0	0
T125	0	27	0	0
T126	0	7	0	0
T127	0	23	0	0
T128	0	16	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	544143843	3390	0	0
T5	857134	30	0	0
T6	16400	0	0	0
T8	131561	25	0	0
T9	22396	0	0	0
T10	1403	0	0	0
T11	230353	4	0	0
T12	214636	0	0	0
T13	104920	14	0	0
T14	28256	7	0	0
T15	1444902	4	0	0
T16	24290	0	0	0
T18	190695	0	0	0
T27	212492	7	0	0
T28	267878	0	0	0
T29	719566	6	0	0
T30	0	6	0	0
T31	1481098	22	0	0
T39	0	7	0	0
T40	0	7	0	0
T41	419558	0	0	0
T43	0	19	0	0
T52	0	1	0	0
T69	544	0	0	0
T70	40368	0	0	0
T71	1584	0	0	0
T122	0	6	0	0
T123	0	7	0	0
T124	0	5	0	0
T125	0	27	0	0
T126	0	7	0	0
T127	0	23	0	0
T128	0	16	0	0

Line Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T5
0	1	Covered	T14,T39,T40
1	0	Covered	T14,T39,T40
1	1	Covered	T14,T39,T40

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T14,T39,T40
1	0	Covered	T14,T39,T40
1	1	Covered	T14,T39,T40

---

Branch Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T4,T5

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	577067519	397	0	0
SrcPulseCheck_M	181381281	397	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577067519	397	0	0
T14	87906	2	0	0
T15	273225	0	0	0
T27	133697	0	0	0
T28	784309	0	0	0
T29	793895	0	0	0
T31	450576	0	0	0
T39	0	4	0	0
T40	0	2	0	0
T41	841450	0	0	0
T52	0	1	0	0
T59	8151	0	0	0
T69	5591	0	0	0
T70	126366	0	0	0
T122	0	3	0	0
T123	0	2	0	0
T124	0	3	0	0
T125	0	14	0	0
T126	0	2	0	0
T127	0	12	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	181381281	397	0	0
T14	14128	2	0	0
T15	722451	0	0	0
T27	106246	0	0	0
T28	133939	0	0	0
T29	359783	0	0	0
T31	740549	0	0	0
T39	0	4	0	0
T40	0	2	0	0
T41	209779	0	0	0
T52	0	1	0	0
T69	272	0	0	0
T70	20184	0	0	0
T71	792	0	0	0
T122	0	3	0	0
T123	0	2	0	0
T124	0	3	0	0
T125	0	14	0	0
T126	0	2	0	0
T127	0	12	0	0

Line Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T5
0	1	Covered	T14,T39,T40
1	0	Covered	T14,T39,T40
1	1	Covered	T14,T39,T40

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T14,T39,T40
1	0	Covered	T14,T39,T40
1	1	Covered	T14,T39,T40

---

Branch Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T4,T5

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	577067519	559	0	0
SrcPulseCheck_M	181381281	559	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577067519	559	0	0
T14	87906	5	0	0
T15	273225	0	0	0
T27	133697	0	0	0
T28	784309	0	0	0
T29	793895	0	0	0
T31	450576	0	0	0
T39	0	3	0	0
T40	0	5	0	0
T41	841450	0	0	0
T59	8151	0	0	0
T69	5591	0	0	0
T70	126366	0	0	0
T122	0	3	0	0
T123	0	5	0	0
T124	0	2	0	0
T125	0	13	0	0
T126	0	5	0	0
T127	0	11	0	0
T128	0	16	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	181381281	559	0	0
T14	14128	5	0	0
T15	722451	0	0	0
T27	106246	0	0	0
T28	133939	0	0	0
T29	359783	0	0	0
T31	740549	0	0	0
T39	0	3	0	0
T40	0	5	0	0
T41	209779	0	0	0
T69	272	0	0	0
T70	20184	0	0	0
T71	792	0	0	0
T122	0	3	0	0
T123	0	5	0	0
T124	0	2	0	0
T125	0	13	0	0
T126	0	5	0	0
T127	0	11	0	0
T128	0	16	0	0

Line Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T5
0	1	Covered	T5,T8,T11
1	0	Covered	T5,T8,T11
1	1	Covered	T5,T8,T11

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T8,T11
1	0	Covered	T5,T8,T11
1	1	Covered	T5,T8,T11

---

Branch Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T4,T5

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	577067519	2434	0	0
SrcPulseCheck_M	181381281	2434	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577067519	2434	0	0
T5	522705	30	0	0
T6	68813	0	0	0
T7	887	0	0	0
T8	798326	25	0	0
T9	116208	0	0	0
T10	4196	0	0	0
T11	120165	4	0	0
T13	0	14	0	0
T15	0	4	0	0
T16	38890	0	0	0
T17	1359	0	0	0
T18	932648	0	0	0
T27	0	7	0	0
T29	0	6	0	0
T30	0	6	0	0
T31	0	22	0	0
T43	0	19	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	181381281	2434	0	0
T5	857134	30	0	0
T6	16400	0	0	0
T8	131561	25	0	0
T9	22396	0	0	0
T10	1403	0	0	0
T11	230353	4	0	0
T12	214636	0	0	0
T13	104920	14	0	0
T15	0	4	0	0
T16	24290	0	0	0
T18	190695	0	0	0
T27	0	7	0	0
T29	0	6	0	0
T30	0	6	0	0
T31	0	22	0	0
T43	0	19	0	0